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15.4.1.4 ICR Register (Offset = Ch) [reset = X]
ICR is shown in Figure 15-5 and described in Table 15-5.
Interrupt Clear
Figure 15-5. ICR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDTICR
W-X
Table 15-5. ICR Register Field Descriptions
Bit Field Type Reset Description
31-0 WDTICR W X
This register is the interrupt clear register. A write of any value to this
register clears the WDT interrupt and reloads the 32-bit counter from
the LOAD register.
1149
SWCU117A–February 2015–Revised March 2015 Watchdog Timer
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