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15.4.1.3 CTL Register (Offset = 8h) [reset = X]
CTL is shown in Figure 15-4 and described in Table 15-4.
Control
Figure 15-4. CTL Register
31 30 29 28 27 26 25 24
RESERVED
R-X
23 22 21 20 19 18 17 16
RESERVED
R-X
15 14 13 12 11 10 9 8
RESERVED
R-X
7 6 5 4 3 2 1 0
RESERVED INTTYPE RESEN INTEN
R-X R/W-X R/W-X R/W-X
Table 15-4. CTL Register Field Descriptions
Bit Field Type Reset Description
31-3 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
2 INTTYPE R/W X
WDT Interrupt Type 0: WDT interrupt is a standard interrupt. 1: WDT
interrupt is a non-maskable interrupt.
0h = Maskable interrupt
1h = Non-maskable interrupt
1 RESEN R/W X
WDT Reset Enable. Defines the function of the WDT reset source
(see PRCM:WARMRESET.WDT_STAT if enabled) 0: Disabled. 1:
Enable the Watchdog reset output.
0h = Reset output Disabled
1h = Reset output Enabled
0 INTEN R/W X
WDT Interrupt Enable 0: Interrupt event disabled. 1: Interrupt event
enabled. Once set, this bit can only be cleared by a hardware reset.
0h = Interrupt Disabled
1h = Interrupt Enabled
1148
Watchdog Timer SWCU117A–February 2015–Revised March 2015
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