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Watchdog Timer Registers

15.4.1 WDT Registers

Table 15-1 lists the memory-mapped registers for the WDT. All register offset addresses not listed in

Table 15-1 should be considered as reserved locations and the register contents should not be modified.

Table 15-1. WDT Registers

Offset Acronym Register Name Section

0h LOAD Configuration Section 15.4.1.1

4h VALUE Current Count Value Section 15.4.1.2

8h CTL Control Section 15.4.1.3

Ch ICR Interrupt Clear Section 15.4.1.4

10h RIS Raw Interrupt Status Section 15.4.1.5

14h MIS Masked Interrupt Status Section 15.4.1.6

418h TEST Test Mode Section 15.4.1.7

41Ch INT_CAUS Interrupt Cause Test Mode Section 15.4.1.8

C00h LOCK Lock Section 15.4.1.9

1145

SWCU117A–February 2015–Revised March 2015 Watchdog Timer

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