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WDT Introduction

15.1 WDT Introduction

WDT has the following features:

• 32-bit downcounter with a programmable load register

• Programmable interrupt generation logic with interrupt masking and optional NMI function

• Lock register protection from runaway software

• Reset generation logic with an enable or disable

• User-enabled stalling when the microcontroller asserts the CPU Halt flag during debug

The WDT can be configured to generate an interrupt to the controller on its first time-out, and to generate

a reset signal on its second time-out. Once the WDT has been configured, the lock register can be written

to prevent the timer configuration from being inadvertently altered.

There are two possible interrupts that can be driven out of the WDT. The interrupt choice is controlled

using the [WDT:CTL:INTTYPE] register.

15.2 WDT Functional Description

The WDT module generates the first time-out signal when the 32-bit counter reaches the zero state after

being enabled; enabling the counter also enables the WDT interrupt. Figure 15-1 shows the WDT block

diagram.

The watchdog interrupt can be programmed to be a nonmaskable interrupt (NMI) using the

[WDT:CTL:INTTYPE] register. After the first time-out event, the 32-bit counter is reloaded with the value of

the WDT load register [WDT:LOAD], and the timer resumes counting down from that value. To prevent the

WDT configuration from being inadvertently altered by software, the write access to the watchdog

registers can be locked by writing the [WDT:LOCK] register to any value. To unlock the WDT, write the

[WDT:LOCK] register to the value 0x1ACC E551.

If the timer counts down to its zero state again before the first time-out interrupt is cleared, and the reset

signal has been enabled by setting the [WDT:CTL:RESEN] register to 1, the WDT asserts its reset signal

to the system. If the interrupt is cleared before the 32-bit counter reaches its second time-out, the 32-bit

counter is loaded with the value in the [WDT:LOAD] register, and counting resumes from that value.

If the [WDT:LOAD] register is written with a new value while the WDT counter is counting, then the

counter is loaded with the new value and continues counting.

Writing to the [WDT:LOAD] register does not clear an active interrupt. An interrupt must be cleared by

writing to the watchdog interrupt clear [WDT:ICR] register. The watchdog module interrupt and reset

generation can be enabled or disabled as required. When the interrupt is enabled again, the 32-bit counter

is preloaded with the load register value (not its last state).

1143

SWCU117A–February 2015–Revised March 2015 Watchdog Timer

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