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Real-Time Clock Registers

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14.4.1.11 CH1CAPT Register (Offset = 28h) [reset = X]

CH1CAPT is shown in Figure 14-12 and described in Table 14-12.

Channel 1 Capture Value If CHCTL.CH1_EN = 1and CHCTL.CH1_CAPT_EN = 1, capture occurs on each

rising edge of the event selected in AON_EVENT:RTCSEL.

Figure 14-12. CH1CAPT Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SEC SUBSEC

R-X R-X

Table 14-12. CH1CAPT Register Field Descriptions

Bit Field Type Reset Description

31-16 SEC R X

Value of SEC.VALUE bits 15:0 at capture time.

15-0 SUBSEC R X

Value of SUBSEC.VALUE bits 31:16 at capture time.

1140

Real-Time Clock SWCU117A–February 2015–Revised March 2015

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