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Real-Time Clock Registers

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14.4.1.7 CH0CMP Register (Offset = 18h) [reset = X]

CH0CMP is shown in Figure 14-8 and described in Table 14-8.

Channel 0 Compare Value

Figure 14-8. CH0CMP Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

VALUE

R/W-X

Table 14-8. CH0CMP Register Field Descriptions

Bit Field Type Reset Description

31-0 VALUE R/W X

RTC Channel 0 compare value. Bit 31 to 16 represents seconds and

bits 15 to 0 represents subseconds of the compare value. The

compare value is compared against SEC.VALUE (15:0) and

SUBSEC.VALUE (31:16) values of the Real Time Clock register. A

Cannel 0 event is generated when

{SEC.VALUE(15:0),SUBSEC.VALUE (31:16)} is reaching or exciting

the compare value. Writing to this register can trigger an immediate*)

event in case the new compare value matches a Real Time Clock

value from 1 second in the past up till current Real Time Clock value.

Example: To generate a compare 5.5 seconds RTC start,- set this

value = 0x0005_8000 *) It can take up to 2 SCLK_LF clock cycles

before event occurs due to synchronization.

1136

Real-Time Clock SWCU117A–February 2015–Revised March 2015

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