User manual

www.ti.com Real-Time Clock Registers
14.4.1.6 CHCTL Register (Offset = 14h) [reset = X]
CHCTL is shown in Figure 14-7 and described in Table 14-7.
Channel Configuration
Figure 14-7. CHCTL Register
31 30 29 28 27 26 25 24
RESERVED
R-X
23 22 21 20 19 18 17 16
RESERVED CH2_CONT_E RESERVED CH2_EN
N
R-X R/W-X R-X R/W-X
15 14 13 12 11 10 9 8
RESERVED CH1_CAPT_E CH1_EN
N
R-X R/W-X R/W-X
7 6 5 4 3 2 1 0
RESERVED CH0_EN
R-X R/W-X
Table 14-7. CHCTL Register Field Descriptions
Bit Field Type Reset Description
31-19 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
18 CH2_CONT_EN R/W X
Set to enable continuous opereation of Channel 2
17 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
16 CH2_EN R/W X
RTC Channel 2 Enable 0: Disable RTC Channel 2 1: Enable RTC
Channel 2
15-10 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
9 CH1_CAPT_EN R/W X
Set Channel 1 mode 0: Compare mode (default) 1: Capture mode
8 CH1_EN R/W X
RTC Channel 1 Enable 0: Disable RTC Channel 1 1: Enable RTC
Channel 1
7-1 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
0 CH0_EN R/W X
RTC Channel 0 Enable 0: Disable RTC Channel 0 1: Enable RTC
Channel 0
1135
SWCU117A–February 2015–Revised March 2015 Real-Time Clock
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated