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General-Purpose Timer Registers

13.5.1.30 ANDCCP Register (Offset = FB4h) [reset = X]

ANDCCP is shown in Figure 13-38 and described in Table 13-37.

Combined CCP Output This register is used to logically AND CCP output pairs for each timer

Figure 13-38. ANDCCP Register

31 30 29 28 27 26 25 24

RESERVED

R-X

23 22 21 20 19 18 17 16

RESERVED

R-X

15 14 13 12 11 10 9 8

RESERVED

R-X

7 6 5 4 3 2 1 0

RESERVED CCP_AND_EN

R-X R/W-X

Table 13-37. ANDCCP Register Field Descriptions

Bit Field Type Reset Description

31-1 RESERVED R X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

0 CCP_AND_EN R/W X

Enables anding of the CCP outputs for timers A and B

1123

SWCU117A–February 2015–Revised March 2015 Timers

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