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13.5.1.22 RTCPD Register (Offset = 58h) [reset = X]
RTCPD is shown in Figure 13-30 and described in Table 13-29.
RTC Pre-divide Value This register shows the current value of the RTC pre-divider in RTC mode. Note:
When the alternate timer clock (TIMCLK) is enabled; a read of a timer value will return the current count -
1.
Figure 13-30. RTCPD Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RTCPD
R-X R-7FFFh
Table 13-29. RTCPD Register Field Descriptions
Bit Field Type Reset Description
31-16 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
15-0 RTCPD R 7FFFh
GPT RTC Pre-divider
1115
SWCU117A–February 2015–Revised March 2015 Timers
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