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General-Purpose Timer Registers

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13.5.1.13 TBMATCHR Register (Offset = 34h) [reset = FFFFh]

TBMATCHR is shown in Figure 13-21 and described in Table 13-20.

Timer B Match Register When a GPT is configured to one of the 32-bit modes, the contents of bits 15:0 in

this register are loaded into the upper 16 bits of TAMATCHR. Reads from this register return the current

match value of Timer B and writes are ignored. In a 16-bit mode, bits 15:0 are used for the match value.

Bits 31:16 are reserved in both cases.

Figure 13-21. TBMATCHR Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TBMATCHR

R/W-FFFFh

Table 13-20. TBMATCHR Register Field Descriptions

Bit Field Type Reset Description

31-0 TBMATCHR R/W FFFFh

GPT Timer B Match Register

1106

Timers SWCU117A–February 2015–Revised March 2015

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