TEXAS INSTRUMENTS PCB design board : User manual : Page 1105

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General-Purpose Timer Registers

13.5.1.12 TAMATCHR Register (Offset = 30h) [reset = FFFFFFFFh]

TAMATCHR is shown in Figure 13-20 and described in Table 13-19.

Timer A Match Register This register is loaded with a match value. Interrupts can be generated when the

timer value is equal to the value in this register in one-shot or periodic mode. In Edge-Count mode, this

register along with TAILR, determines how many edge events are counted. The total number of edge

events counted is equal to the value in TAILR minus this value. Note that in edge-count mode, when

executing an up-count, the value of TAPR and TAILR must be greater than the value of TAPMR and

TAMATCHR. In PWM mode, this value along with TAILR, determines the duty cycle of the output PWM

signal. When a 16/32-bit GPT is configured to one of the 32-bit modes, TAMATCHR appears as a 32-bit

register. (The upper 16-bits correspond to the contents TBMATCHR). In a 16-bit mode, the upper 16 bits

of this register read as 0s and have no effect on the state of TBMATCHR.

Figure 13-20. TAMATCHR Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TAMATCHR

R/W-FFFFFFFFh

Table 13-19. TAMATCHR Register Field Descriptions

Bit Field Type Reset Description

31-0 TAMATCHR R/W FFFFFFFFh

GPT Timer A Match Register

1105

SWCU117A–February 2015–Revised March 2015 Timers

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