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General-Purpose Timer Registers www.ti.com
13.5.1.11 TBILR Register (Offset = 2Ch) [reset = FFFFh]
TBILR is shown in Figure 13-19 and described in Table 13-18.
Timer B Interval Load Register
Figure 13-19. TBILR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBILR
R/W-FFFFh
Table 13-18. TBILR Register Field Descriptions
Bit Field Type Reset Description
31-0 TBILR R/W FFFFh
GPT Timer B Interval Load Register
1104
Timers SWCU117A–February 2015–Revised March 2015
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