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General-Purpose Timer Registers

Table 13-14. RIS Register Field Descriptions (continued)

Bit Field Type Reset Description

3 RTCRIS R X

GPT RTC Raw Interrupt 0: The RTC event has not occured 1: The

RTC event has occured

2 CAERIS R X

GPT Timer A Capture Mode Event Raw Interrupt 0: The event has

not occured. 1: The event has occured. This interrupt asserts when

the subtimer is configured in Input Edge-Time mode

1 CAMRIS R X

GPT Timer A Capture Mode Match Raw Interrupt 0: Match for Timer

A has not occured 1: Match for Timer A has occurred This interrupt

asserts when the values in the TAR and TAPR match values in the

TAMATCHR and TAPMR, and when configured in Input Edge-Time

mode (reg-ref instead!!)

0 TATORIS R X

GPT Timer A Time-out Raw Interrupt 0: Timer A has not timed out 1:

Timer A has timed out. This interrupt is asserted when a one-shot or

periodic mode timer reaches it's count limit. The count limit is 0 or

the value loaded into TAILR, depending on the count direction.

1099

SWCU117A–February 2015–Revised March 2015 Timers

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