User manual

General-Purpose Timer Registers www.ti.com
13.5.1.7 RIS Register (Offset = 1Ch) [reset = X]
RIS is shown in Figure 13-15 and described in Table 13-14.
Raw Interrupt Status Associated registers: IMR, MIS, ICLR
Figure 13-15. RIS Register
31 30 29 28 27 26 25 24
RESERVED
R-X
23 22 21 20 19 18 17 16
RESERVED WURIS
R-X R-X
15 14 13 12 11 10 9 8
RESERVED DMABRIS RESERVED TBMRIS CBERIS CBMRIS TBTORIS
R-X R-X R-X R-X R-X R-X R-X
7 6 5 4 3 2 1 0
RESERVED DMAARIS TAMRIS RTCRIS CAERIS CAMRIS TATORIS
R-X R-X R-X R-X R-X R-X R-X
Table 13-14. RIS Register Field Descriptions
Bit Field Type Reset Description
31-17 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
16 WURIS R X
GPT Write Update Error Raw Interrupt 0: No error. 1: Either Timer A
or B was written twice in a Row or Timer A was written before the
corresponding Timer B was written.
15-14 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
13 DMABRIS R X
GPT Timer B DMA Done Raw Interrupt Status 0: Transfer has not
completed 1: Transfer has completed
12 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
11 TBMRIS R X
GPT Timer B Match Raw Interrupt 0: The match value has not been
reached 1: The match value is reached. TBMR.TBMIE is set, and
the match values in TBMATCHR and optionally TBPMR have been
reached when configured in one-shot or periodic mode.
10 CBERIS R X
GPT Timer B Capture Mode Event Raw Interrupt 0: The event has
not occured. 1: The event has occured. This interrupt asserts when
the subtimer is configured in Input Edge-Time mode
9 CBMRIS R X
GPT Timer B Capture Mode Match Raw Interrupt 0: Match for Timer
B has not occured 1: Match for Timer B has occurred. This interrupt
asserts when the values in the TBR and TBPR match values in the
TBMATCHR and TBPMR, and when configured in Input Edge-Time
mode (reg-ref instead!!)
8 TBTORIS R X
GPT Timer B Time-out Raw Interrupt 0: Timer B has not timed out 1:
Timer B has timed out. This interrupt is asserted when a one-shot or
periodic mode timer reaches it's count limit. The count limit is 0 or
the value loaded into TBILR, depending on the count direction.
7-6 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
5 DMAARIS R X
GPT Timer A DMA Done Raw Interrupt Status 0: Transfer has not
completed 1: Transfer has completed
4 TAMRIS R X
**GPT **Timer A Match Raw Interrupt 0: The match value has not
been reached 1: The match value is reached. TAMR.TAMIE is set,
and the match values in TAMATCHR and optionally TAPMR have
been reached when configured in one-shot or periodic mode.
1098
Timers SWCU117A–February 2015–Revised March 2015
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated