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General-Purpose Timer Registers
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13.5.1.6 IMR Register (Offset = 18h) [reset = X]
IMR is shown in Figure 13-14 and described in Table 13-13.
Interrupt Mask This register is used to enable the interrupts. Associated registers: RIS, MIS, ICLR
Figure 13-14. IMR Register
31 30 29 28 27 26 25 24
RESERVED
R-X
23 22 21 20 19 18 17 16
RESERVED WUMIS
R-X R/W-X
15 14 13 12 11 10 9 8
RESERVED DMABIM RESERVED TBMIM CBEIM CBMIM TBTOIM
R-X R/W-X R-X R/W-X R/W-X R/W-X R/W-X
7 6 5 4 3 2 1 0
RESERVED DMAAIM TAMIM RTCIM CAEIM CAMIM TATOIM
R-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X
Table 13-13. IMR Register Field Descriptions
Bit Field Type Reset Description
31-17 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
16 WUMIS R/W X
Enabling this bit will make the RIS.WURIS interrupt propagate to
MIS.WUMIS
0h = Disable Interrupt
1h = Enable Interrupt
15-14 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
13 DMABIM R/W X
Enabling this bit will make the RIS.DMABRIS interrupt propagate to
MIS.DMABMIS
0h = Disable Interrupt
1h = Enable Interrupt
12 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
11 TBMIM R/W X
Enabling this bit will make the RIS.TBMRIS interrupt propagate to
MIS.TBMMIS
0h = Disable Interrupt
1h = Enable Interrupt
10 CBEIM R/W X
Enabling this bit will make the RIS.CBERIS interrupt propagate to
MIS.CBEMIS
0h = Disable Interrupt
1h = Enable Interrupt
9 CBMIM R/W X
Enabling this bit will make the RIS.CBMRIS interrupt propagate to
MIS.CBMMIS
0h = Disable Interrupt
1h = Enable Interrupt
8 TBTOIM R/W X
Enabling this bit will make the RIS.TBTORIS interrupt propagate to
MIS.TBTOMIS
0h = Disable Interrupt
1h = Enable Interrupt
7-6 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
1096
Timers SWCU117AFebruary 2015Revised March 2015
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