User manual

General-Purpose Timer Registers

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Table 13-11. CTL Register Field Descriptions (continued)

Bit Field Type Reset Description

4 RTCEN R/W X

GPT RTC Enable

0h = RTC counting is disabled.

1h = RTC counting is enabled.

3-2 TAEVENT R/W X

GPT Timer A Event Mode

0h = Positive edge

1h = Negative edge

3h = Both edges

1 TASTALL R/W X

GPT Timer A Stall Enable

0h = Timer A continues counting while the processor is halted by the

debugger.

1h = Timer A freezes counting while the processor is halted by the

debugger.

0 TAEN R/W X

GPT Timer A Enable

0h = Timer A is disabled.

1h = Timer A is enabled and begins counting or the capture logic is

enabled based on the CFG register.

1094

Timers SWCU117A–February 2015–Revised March 2015

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