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13.5.1.2 TAMR Register (Offset = 4h) [reset = X]
TAMR is shown in Figure 13-10 and described in Table 13-9.
Timer A Mode
Figure 13-10. TAMR Register
31 30 29 28 27 26 25 24
RESERVED
R-X
23 22 21 20 19 18 17 16
RESERVED
R-X
15 14 13 12 11 10 9 8
TCACT TACINTD TAPLO TAMRSU TAPWMIE TAILD
R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X
7 6 5 4 3 2 1 0
TASNAPS TAWOT TAMIE TACDIR TAAMS TACM TAMR
R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X
Table 13-9. TAMR Register Field Descriptions
Bit Field Type Reset Description
31-16 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
15-13 TCACT R/W X
Timer Compare Action Select
0h = DIS_CMP : Disable compare operations
1h = Toggle State on Time-Out
2h = Clear CCP output pin on Time-Out
3h = Set CCP output pin on Time-Out
4h = Set CCP output pin immediately and toggle on Time-Out
5h = Clear CCP output pin immediately and toggle on Time-Out
6h = Set CCP output pin immediately and clear on Time-Out
7h = Clear CCP output pin immediately and set on Time-Out
12 TACINTD R/W X
One-Shot/Periodic Interrupt Disable
0h = Time-out interrupt function as normal
1h = Time-out interrupt are disabled
11 TAPLO R/W X
Legacy PWM operation
0h = Legacy operation
1h = CCP output pin is set to 1 on time-out
10 TAMRSU R/W X
Timer A Match Register Update mode If the timer is disabled
(CTL.TAEN = 0) when this bit is set, TAMATCHR and TAPR are
updated when the timer is enabled. If the timer is stalled
(CTL.TASTALL is set), TAMATCHR and TAPR are updated
according to the configuration of this bit.
0h = Update TAMATCHR and TAPR, if used, on the next cycle.
1h = Update TAMATCHR and TAPR, if used, on the next time-out.
9 TAPWMIE R/W X
GPT Timer A PWM Interrupt Enable This bit enables interrupts in
PWM mode on rising, falling, or both edges of the CCP output.
0h = Interrupt is disabled.
1h = Interrupt is enabled. This bit is only valid in PWM mode.
1089
SWCU117A–February 2015–Revised March 2015 Timers
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