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General-Purpose Timer Registers

13.5.1 GPT Registers

Table 13-7 lists the memory-mapped registers for the GPT. All register offset addresses not listed in

Table 13-7 should be considered as reserved locations and the register contents should not be modified.

Table 13-7. GPT Registers

Offset Acronym Register Name Section

0h CFG Configuration Section 13.5.1.1

4h TAMR Timer A Mode Section 13.5.1.2

8h TBMR Timer B Mode Section 13.5.1.3

Ch CTL Control Section 13.5.1.4

10h SYNC Synch Register Section 13.5.1.5

18h IMR Interrupt Mask Section 13.5.1.6

1Ch RIS Raw Interrupt Status Section 13.5.1.7

20h MIS Masked Interrupt Status Section 13.5.1.8

24h ICLR Interrupt Clear Section 13.5.1.9

28h TAILR Timer A Interval Load Register Section 13.5.1.10

2Ch TBILR Timer B Interval Load Register Section 13.5.1.11

30h TAMATCHR Timer A Match Register Section 13.5.1.12

34h TBMATCHR Timer B Match Register Section 13.5.1.13

38h TAPR Timer A Pre-scale Section 13.5.1.14

3Ch TBPR Timer B Pre-scale Section 13.5.1.15

40h TAPMR Timer A Pre-scale Match Section 13.5.1.16

44h TBPMR Timer B Pre-scale Match Section 13.5.1.17

48h TAR Timer A Register Section 13.5.1.18

4Ch TBR Timer B Register Section 13.5.1.19

50h TAV Timer A Value Section 13.5.1.20

54h TBV Timer B Value Section 13.5.1.21

58h RTCPD RTC Pre-divide Value Section 13.5.1.22

5Ch TAPS Timer A Pre-scale Snap-shot Section 13.5.1.23

60h TBPS Timer A Pre-scale Snap-shot Section 13.5.1.24

64h TAPV Timer A Pre-scale Value Section 13.5.1.25

68h TBPV Timer B Pre-scale Value Section 13.5.1.26

6Ch DMAEV DMA Event Section 13.5.1.27

70h ADCEV ADC Event Section 13.5.1.28

FB0h VERSION Peripheral Version Section 13.5.1.29

FB4h ANDCCP Combined CCP Output Section 13.5.1.30

1087

SWCU117A–February 2015–Revised March 2015 Timers

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