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13.4.4 PWM Mode
A timer is configured to PWM mode using the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Write the GPTM Configuration [GPT_CFG] register with a value of 0x0000 0004.
3. In the GPTM Timer Mode [GPT_TnMR] register, write the TnCMR field to 0x1 and the TnMR field to
0x2.
4. Configure the output state of the PWM signal (whether or not it is inverted) in the TnPWML field of the
GPTM Control [GPT_CTL] register.
5. If a prescaler is to be used, write the prescale value to the GPTM Timer n Prescale Register
[GPT_TnPR].
6. If PWM interrupts are used, configure the interrupt condition in the TnEVENT field in the GPT_CTL
register, and enable the interrupts by setting the TnPWMIE bit in the [GPT_TnMR] register.
7. Load the timer start value into the GPTM Timer n Interval Load [GPT_TnILR] register.
8. Load the GPTM Timer n Match [GPT_TnMATCHR] register with the match value.
9. Set the TnEN bit in the GPTM Control [GPT_CTL] register to enable the timer and begin generation of
the output PWM signal.
In PWM Timing mode, the timer continues running after the PWM signal has been generated. The PWM
period can be adjusted at any time by writing the [GPTMTnILR] register, and the change takes effect at
the next cycle after the write.
13.4.5 Producing DMA Trigger
The GPT can produce DMA trigger events via the event handler. Single or burst requests can be passed
to the uDMA controller by selecting the trigger source for uDMA channels via the event fabric. Each timer
only produces one signal per A and B, but this signal can be selected as either single or burst in the event
module. The DMA done interrupt is routed back to the timer module that originated the trigger. Following
is a procedure for configuring uDMA triggers by GPT events.
1. Configure the GPT operation.
2. Configure the [GPT_DMAEV] register to enable the appropriate timer event to DMA. Application can
select match, capture or time-out event for each timer.
3. Configure the event fabric (see Chapter 4, Interrupts and Events) to select the appropriate timer. The
event fabric supports five channels for GP timer DMA event out of which four are dedicated to the GPT
block. These dedicated channels are: 9, 10, 11, and 12. Single requests and burst requests are
supported on channels 9 through 12 for GP timer DMA events. The fifth supported channel is 14,
which is configurable for GPT support and handles only burst requests. The configuration is done
through the [EVENT_UDMACHcrSEL] register where c is channel number and r is either S (single) or
B (burst) option. The configuration for channel 14 can be done using the [EVENT_UDMACH14BSEL]
register. Each timer produces only one signal per A and B, but this signal can be selected as either
single or burst in the event module.
4. Enable the General Purpose Timer.
5. The DMA done interrupt is routed back to the timer module that originated the trigger. DMAnRIS bit in
[GPT_RIS] register gives the DMA transfer completed information.
13.5 General-Purpose Timer Registers
1086
Timers SWCU117A–February 2015–Revised March 2015
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