User manual

ManualsBrandsTEXAS INSTRUMENTS ManualsDev KitsPCB design board

1081

Functional Description

www.ti.com

13.3.5 Accessing Concatenated 16- and 32-Bit GPTM Register Values

The GPTM is placed into concatenated mode by writing a 0x0 or a 0x1 to the GPTMCFG bit field in the

GPTM Configuration [GPT_CFG] register. In both configurations, certain 16- and 32-bit GPTM registers

are concatenated to form pseudo 32-bit registers. These registers include:

• GPTM Timer A Interval Load [GPT_TAILR] register [15:0]

• GPTM Timer B Interval Load [GPT_TBILR] register [15:0]

• GPTM Timer A [GPT_TAR] register [15:0]

• GPTM Timer B [GPT_TBR] register [15:0]

• GPTM Timer A Value [GPT_TAV] register [15:0]

• GPTM Timer B Value [GPT_TBV] register [15:0]

• GPTM Timer A Match [GPT_TAMATCHR] register [15:0]

• GPTM Timer B Match [GPT_TBMATCHR] register [15:0]

In the 32-bit modes, the GPTM translates a 32-bit write access to the [GPT_TAILR] register into a write

access to both the [GPT_TAILR] and the [GPT_TBILR] registers. The resulting word ordering for such a

write operation is:

GPTMTBILR[15:0]:GPTMTAILR[15:0]. Likewise, a 32-bit read access to [GPT_TAR]

the value:GPTMTBV[15:0]:GPTMTAV[15:0]

13.4 Initialization and Configuration

To use a GPT module, enable the peripheral domain and the appropriate GPT module in the PRCM by

writing to the [PRCM_GPTCLKGR], [PRCM_GPTCLKGS], and [PRCM_GPTCLKGDS] registers, or by

using the driver library functions PRCMPeripheralRunEnable(uint32_t, ui32Peripheral),

PRCMPeripheralSleepEnable(uint32_t,

ui32Peripheral), and

PRCMPeripheralDeepSLeepEnable(uint32_t, ui32Peripheral) and then loading the setting to

clock controller by writing to the [PRCM_CLKLOADCTL] register. Configure the IOC module to route the

output from the timer output from IOs to the GPT module. For this, [IOCFGxx.PORTID] should be written

to the correct PORTIDs.

This section shows module initialization and configuration examples for each of the supported timer

modes.

13.4.1 One-Shot and Periodic Timer Modes

The GPTM is configured for one-shot and periodic modes by the following sequence:

1. Ensure the timer is disabled (the TnEN bit in the [GPT_CTL] register is cleared) before making any

changes.

2. Write the GPTM Configuration Register [GPT_CFG] with a value of 0x0000 0000.

3. Configure the TnMR field in the GPTM Timer n Mode Register [GPT_TnMR]:

(a) Write a value of 0x1 for one-shot mode.

(b) Write a value of 0x2 for periodic mode.

4. Optionally, configure the TnSNAPS, TnWOT, TnMTE, and TnCDIR bits in the [GPT_TnMR] register to

select whether to capture the value of the free-running timer at time-out, use an external trigger to start

counting, configure an additional trigger or interrupt, and count up or down.

5. Load the start value into the GPTM Timer n Interval Load Register [GPT_TnILR].

6. If interrupts are required, set the appropriate bits in the GPTM Interrupt Mask Register [GPT_IMR].

7. Set the TnEN bit in the [GPT_CTL] register to enable the timer and start counting.

8. Poll the [GPT_MRIS] register or wait for the interrupt to be generated (if enabled). In both cases, the

status flags are cleared by writing a 1 to the appropriate bit of the GPTM Interrupt Clear Register

[GPT_ICR].

1084

Timers SWCU117A–February 2015–Revised March 2015

Submit Documentation Feedback