User manual

GPTMnMATCHR = GPTMnILR-1
GPTMnMATCHR = GPTMnILR-2
GPTMnILR
GPTMnMATCHR == 0
CCP
CCP
CCP
Pulse width is 1 clock when GPTMnMATCHR = GPTMnILR - 1
Pulse width is 2 clocks when GPTMnMATCHR = GPTMnILR - 2
Pulse width is GPTMnMATCHR clocks when GPTMnMATCHR= 0
CCP
CCP not set if GPTMnMATCHR = GPTMnILR
GPTMnMATCHR
CounterValue
GPTMnILR
CCP
CounterValue
GPTMnMATCHR
GPTMnILR
CCP set if GPTMnMATCHR GPTMnILR≠
Functional Description www.ti.com
Figure 13-5. CCP Output, GPT_TnMATCHR > GPT_TnILR
Figure 13-6 shows how the CCP output operates when the PLO and MRSU bits are set and the
[GPT_TnMATCHR] register value is the same as the [GPT_TnILR] register value. In this situation, if the
PLO bit is 0, the CCP signal goes high when the [GPT_TnILR] register value is loaded, and the match
would be essentially ignored.
Figure 13-6. CCP Output, GPT_TnMATCHR = GPT_TnILR
Figure 13-7 shows how the CCP output operates when the PLO and MRSU bits are set and the
[GPT_TnILR] register value is greater than the [GPT_TnMATCHR] register value.
Figure 13-7. CCP Output, GPT_TnILR > GPT_TnMATCHR
1082
Timers SWCU117A–February 2015–Revised March 2015
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