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1071

Input Signal

Timer stops,

flags

asserted

Timer reload

on next cycle

Ignored Ignored

Count

0x000A

0x0006

0x0007

0x0008

0x0009

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Functional Description

Figure 13-2 shows how Input Edge-Count mode works. In this case, the timer start value is set to

GPT_TnILR =0x000A, and the match value is set to GPT_TnMATCHR =0x0006 so that four edge events

are counted. The counter is configured to detect both edges of the input signal.

Note that the last two edges are not counted, because the timer automatically clears the TnEN bit after the

current count matches the value in the [GPT_TnMATCHR] register.

Figure 13-2. Input Edge-Count Mode Example, Counting Down

13.3.2.3 Input Edge-Time Mode

NOTE: For rising-edge detection, the input signal must be High for at least two system clock periods

following the rising edge. Similarly, for falling-edge detection, the input signal must be Low

for at least two system clock periods following the falling edge. Based on this criteria, the

maximum input frequency for edge detection is ¼ of the system frequency.

In Edge-Time mode, the timer is configured as a 24-bit down-counter, including the optional prescaler with

the upper timer value stored in the [GPT_TnPR] register and the lower bits in the [GPT_TnILR] register. In

this mode, the timer is initialized to the value loaded in the [GPT_TnILR] and [GPT_TnPR] registers when

counting down, and 0x0 when counting up. The timer is capable of capturing three types of events: rising

edge, falling edge, or both. The timer is placed into Edge-Time mode by setting the TnCM bit in the

[GPT_TnMR] register, and the type of event that the timer captures is determined by the TnEVENT fields

of the [GPT_CTL] register. Table 13-4 shows the values that are loaded into the timer registers when the

timer is enabled.

Table 13-4. Counter Values When the Timer is Enabled in Input Event-Count Mode

GPT_TnR GPT_TnILR 0x0

GPT_TnV GPT_TnILR 0x0

GPT_TnPV GPT_TnPR 0x0

When software writes the TnEN bit in the [GPT_CTL] register, the timer is enabled for event capture.

When the selected input event is detected, the current timer counter value is captured in the [GPT_TnR]

GPTM Raw Interrupt Status [GPT_RIS] register, and holds it until it is cleared by writing the GPTM

Interrupt Clear [GPT_ICR] register. If the capture mode event interrupt is enabled in the GPTM Interrupt

1079

SWCU117A–February 2015–Revised March 2015 Timers

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