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12.5.1.17 ERROR Register (Offset = 4Ch) [reset = X]
ERROR is shown in Figure 12-23 and described in Table 12-24.
Error Status and Clear
Figure 12-23. ERROR Register
31 30 29 28 27 26 25 24
RESERVED
W-X
23 22 21 20 19 18 17 16
RESERVED
W-X
15 14 13 12 11 10 9 8
RESERVED
W-X
7 6 5 4 3 2 1 0
RESERVED STATUS
W-X R/W-X
Table 12-24. ERROR Register Field Descriptions
Bit Field Type Reset Description
31-1 RESERVED W X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
0 STATUS R/W X
Returns the status of bus error flag in uDMA, or clears this bit Read
as: 0: No bus error detected 1: Bus error detected Write as: 0: No
effect, status of bus error flag is unchanged. 1: Clears the bus error
flag.
1070
Micro Direct Memory Access (µDMA) SWCU117A–February 2015–Revised March 2015
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