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µDMA Registers

12.5.1.16 CLEARCHNLPRIORITY Register (Offset = 3Ch) [reset = X]

CLEARCHNLPRIORITY is shown in Figure 12-22 and described in Table 12-23.

Clear Channel Priority

Figure 12-22. CLEARCHNLPRIORITY Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CHNLS

W-X

Table 12-23. CLEARCHNLPRIORITY Register Field Descriptions

Bit Field Type Reset Description

31-0 CHNLS W X

Clear the appropriate bit to select the default priority level for the

specified uDMA channel. Write as: Bit [Ch] = 0: No effect. Use the

SETCHNLPRIORITY.CHNLS to set channel Ch to the high priority

level. Bit [Ch] = 1: Channel Ch uses the default priority level. Writing

to a bit where a uDMA channel is not implemented has no effect

1069

SWCU117A–February 2015–Revised March 2015 Micro Direct Memory Access (µDMA)

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