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µDMA Registers

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12.5.1.15 SETCHNLPRIORITY Register (Offset = 38h) [reset = X]

SETCHNLPRIORITY is shown in Figure 12-21 and described in Table 12-22.

Set Channel Priority

Figure 12-21. SETCHNLPRIORITY Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CHNLS

R/W-X

Table 12-22. SETCHNLPRIORITY Register Field Descriptions

Bit Field Type Reset Description

31-0 CHNLS R/W X

Returns the channel priority mask status, or sets the channel priority

to high. Read as: Bit [Ch] = 0: uDMA channel Ch is using the default

priority level. Bit [Ch] = 1: uDMA channel Ch is using a high priority

level. Write as: Bit [Ch] = 0: No effect. Use the

CLEARCHNLPRIORITY.CHNLS to set channel Ch to the default

priority level. Bit [Ch] = 1: Channel Ch uses the high priority level.

Writing to a bit where a uDMA channel is not implemented has no

effect

1068

Micro Direct Memory Access (µDMA) SWCU117A–February 2015–Revised March 2015

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