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µDMA Registers

12.5.1.12 CLEARCHANNELEN Register (Offset = 2Ch) [reset = X]

CLEARCHANNELEN is shown in Figure 12-18 and described in Table 12-19.

Clear Channel Enable

Figure 12-18. CLEARCHANNELEN Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CHNLS

W-X

Table 12-19. CLEARCHANNELEN Register Field Descriptions

Bit Field Type Reset Description

31-0 CHNLS W X

Set the appropriate bit to disable the corresponding uDMA channel.

Write as: Bit [Ch] = 0: No effect. Use the SETCHANNELEN.CHNLS

to enable uDMA channels. Bit [Ch] = 1: Disables channel Ch Writing

to a bit where a uDMA channel is not implemented has no effect

1065

SWCU117A–February 2015–Revised March 2015 Micro Direct Memory Access (µDMA)

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