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µDMA Registers

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12.5.1.11 SETCHANNELEN Register (Offset = 28h) [reset = X]

SETCHANNELEN is shown in Figure 12-17 and described in Table 12-18.

Set Channel Enable

Figure 12-17. SETCHANNELEN Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CHNLS

R/W-X

Table 12-18. SETCHANNELEN Register Field Descriptions

Bit Field Type Reset Description

31-0 CHNLS R/W X

Returns the enable status of the channels, or enables the

corresponding channels. Read as: Bit [Ch] = 0: Channel Ch is

disabled. Bit [Ch] = 1: Channel Ch is enabled. Write as: Bit [Ch] = 0:

No effect. Use the CLEARCHANNELEN.CHNLS to disable a

channel Bit [Ch] = 1: Enables channel Ch Writing to a bit where a

DMA channel is not implemented has no effect

1064

Micro Direct Memory Access (µDMA) SWCU117A–February 2015–Revised March 2015

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