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µDMA Registers

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12.5.1.3 CTRL Register (Offset = 8h) [reset = X]

CTRL is shown in Figure 12-9 and described in Table 12-10.

Channel Control Data Base Pointer

Figure 12-9. CTRL Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BASEPTR RESERVED

R/W-X R/W-X

Table 12-10. CTRL Register Field Descriptions

Bit Field Type Reset Description

31-10 BASEPTR R/W X

This register point to the base address for the primary data

structures of each DMA channel. This is not stored in module, but in

system memory, thus space must be allocated for this usage when

DMA is in usage

9-0 RESERVED R/W X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

1056

Micro Direct Memory Access (µDMA) SWCU117A–February 2015–Revised March 2015

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