User manual

µDMA Registers www.ti.com
12.5.1.1 STATUS Register (Offset = 0h) [reset = X]
STATUS is shown in Figure 12-7 and described in Table 12-8.
Status
Figure 12-7. STATUS Register
31 30 29 28 27 26 25 24
TEST RESERVED
R-X R-X
23 22 21 20 19 18 17 16
RESERVED TOTALCHANNELS
R-X R-1Fh
15 14 13 12 11 10 9 8
RESERVED
R-X
7 6 5 4 3 2 1 0
STATE RESERVED MASTERENAB
LE
R-X R-X R-X
Table 12-8. STATUS Register Field Descriptions
Bit Field Type Reset Description
31-28 TEST R X
0x0: Controller does not include the integration test logic 0x1:
Controller includes the integration test logic 0x2: Undefined ... 0xF:
Undefined
27-21 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
20-16 TOTALCHANNELS R 1Fh
Register value returns number of available uDMA channels minus
one. For example a read out value of: 0x00: Show that the controller
is configured to use 1 uDMA channel 0x01: Shows that the controller
is configured to use 2 uDMA channels ... 0x1F: Shows that the
controller is configured to use 32 uDMA channels (32-1=31=0x1F)
15-8 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
7-4 STATE R X
Current state of the control state machine. State can be one of the
following: 0x0: Idle 0x1: Reading channel controller data 0x2:
Reading source data end pointer 0x3: Reading destination data end
pointer 0x4: Reading source data 0x5: Writing destination data 0x6:
Waiting for uDMA request to clear 0x7: Writing channel controller
data 0x8: Stalled 0x9: Done 0xA: Peripheral scatter-gather transition
0xB: Undefined ... 0xF: Undefined.
3-1 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
0 MASTERENABLE R X
Shows the enable status of the controller as configured by
CFG.MASTERENABLE: 0: Controller is disabled 1: Controller is
enabled
1054
Micro Direct Memory Access (µDMA) SWCU117A–February 2015–Revised March 2015
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated