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µDMA Registers

12.5.1 UDMA Registers

Table 12-7 lists the memory-mapped registers for the UDMA. All register offset addresses not listed in

Table 12-7 should be considered as reserved locations and the register contents should not be modified.

Table 12-7. UDMA Registers

Offset Acronym Register Name Section

0h STATUS Status Section 12.5.1.1

4h CFG Configuration Section 12.5.1.2

8h CTRL Channel Control Data Base Pointer Section 12.5.1.3

Ch ALTCTRL Channel Alternate Control Data Base Pointer Section 12.5.1.4

10h WAITONREQ Channel Wait On Request Status Section 12.5.1.5

14h SOFTREQ Channel Software Request Section 12.5.1.6

18h SETBURST Channel Set UseBurst Section 12.5.1.7

1Ch CLEARBURST Channel Clear UseBurst Section 12.5.1.8

20h SETREQMASK Channel Set Request Mask Section 12.5.1.9

24h CLEARREQMASK Clear Channel Request Mask Section 12.5.1.10

28h SETCHANNELEN Set Channel Enable Section 12.5.1.11

2Ch CLEARCHANNELEN Clear Channel Enable Section 12.5.1.12

30h SETCHNLPRIALT Channel Set Primary-Alternate Section 12.5.1.13

34h CLEARCHNLPRIALT Channel Clear Primary-Alternate Section 12.5.1.14

38h SETCHNLPRIORITY Set Channel Priority Section 12.5.1.15

3Ch CLEARCHNLPRIORITY Clear Channel Priority Section 12.5.1.16

4Ch ERROR Error Status and Clear Section 12.5.1.17

504h REQDONE Channel Request Done Section 12.5.1.18

520h DONEMASK Channel Request Done Mask Section 12.5.1.19

1053

SWCU117A–February 2015–Revised March 2015 Micro Direct Memory Access (µDMA)

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