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12.3.7 Transfer Size and Increments
The μDMA controller supports transfer data sizes of 8, 16, or 32 bits. The source and destination data size
must be the same for any given transfer. The source and destination address can be automatically
incremented by bytes, half-words, words, or set to no increment. The source and destination address
increment values can be set independently; it is not necessary for the address increment to match the
data size, as long as the increment is the same or larger than the data size. For example, it is possible to
perform a transfer using 8-bit data size by using an address increment of full words (4 bytes). The data to
be transferred must be aligned in memory according to the data size (8, 16, or 32 bits).
Table 12-5 provides the configuration to read from a peripheral that supplies 8-bit data.
Table 12-5. μDMA Read Example: 8-Bit Peripheral
Field Configuration
Source data size 8 bits
Destination data size 8 bits
Source address increment No increment
Destination address increment Byte
Source end pointer Peripheral read FIFO register
Destination end pointer End of the data buffer in memory
12.3.8 Peripheral Interface
Each peripheral that supports μDMA has a single request or burst request signal that is asserted when the
peripheral is ready to transfer data (see Table 12-2). The request signal can be disabled or enabled using
the [UDMA_SETREQMASK] and [UDMA_CLEARREQMASK] registers, respectively. The μDMA request
signal is disabled, or masked, when the channel request mask bit is set. When the request is not masked,
the μDMA channel is configured correctly and enabled, the peripheral asserts the request signal, and the
μDMA controller begins the transfer.
NOTE: The peripheral must disable all interrupts to the event fabric when using μDMA to transfer
data to and from a peripheral.
When a μDMA transfer is complete, the μDMA controller generates an interrupt; for more information, see
Section 12.3.10, Interrupts and Errors.
For more information on how a specific peripheral interacts with the μDMA controller, refer to the DMA
Operation section in the chapter that discusses that peripheral.
12.3.9 Software Request
Channels may be set up to perform software transfers through the [UDMA_SOFTREQ] register. If the
channel used for software is also tied to a specific peripheral, the dma_done/interrupt signal is provided
directly to the Cortex-M3 CPU instead of sending it to the peripheral. The interrupt used is a combined
interrupt, number 46 – software µDMA interrupt, for all software transfers.
If software uses a μDMA channel of the peripheral to initiate a request, then the completion interrupt
occurs on the interrupt vector for the peripheral instead of occurring on the software interrupt vector.
NOTE: DMA software requests are specified on channels 0, 18, 19, and 20. For channel 0 and
channel 18, dma_done is available as events DMA_CH0_DONE and DMA_CH18_DONE in
the EV field of the [EVENT_UDMACH14BSEL] or [EVENT_CPUIRQSEL30] registers.
1050
Micro Direct Memory Access (µDMA) SWCU117A–February 2015–Revised March 2015
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