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12.3.2 Priority
The μDMA controller assigns priority to each channel based on the channel number and the priority level
bit for the channel. Channel 0 has the highest priority, and as the channel number increases, the priority of
a channel decreases. Each channel has a priority-level bit to provide two levels of priority: default priority
and high priority. If the priority-level bit is set, then that channel has a higher priority than all other
channels at default priority. If multiple channels are set for high priority, then the channel number is used
to determine relative priority among all the high-priority channels.
The priority bit for a channel can be set using the [UDMA_SETCHNLPRIORITY] register and cleared with
the [UDMA_CLEARCHNLPRIORITY] register.
12.3.3 Arbitration Size
When a μDMA channel requests a transfer, the μDMA controller arbitrates among all the channels making
a request, and services the μDMA channel with the highest priority. Once a transfer begins, it continues
for a selectable number of transfers before rearbitrating among the requesting channels. The arbitration
size can be configured for each channel, ranging from 1 to 1024 item transfers. After the μDMA controller
transfers the number of items specified by the arbitration size, the controller then checks among all the
channels making a request, and services the channel with the highest priority.
If a lower-priority μDMA channel uses a large arbitration size, the latency for higher-priority channels is
increased because the μDMA controller completes the lower-priority burst before checking for higher-
priority requests. Therefore, lower-priority channels must not use a large arbitration size for best response
on high-priority channels.
The arbitration size can also be thought of as burst size. Arbitration size is the maximum number of items
that are transferred at any one time in a burst. Here, the term arbitration refers to the determination of the
μDMA channel priority, not arbitration for the bus. When the μDMA controller arbitrates for the bus, the
processor always takes priority. Furthermore, the μDMA controller is delayed whenever the processor
must perform a bus transaction on the same bus, even in the middle of a burst transfer.
12.3.4 Request Types
The μDMA controller responds to two types of requests from a peripheral: single request or burst request.
Each peripheral may support either or both types of requests. A single request means that the peripheral
is ready to transfer one item, while a burst request means that the peripheral is ready to transfer multiple
items.
The μDMA controller responds differently depending on whether the peripheral is making a single request
or a burst request. If both types of requests are asserted and the μDMA channel has been set up for a
burst transfer, then the burst request takes precedence. Table 12-2 lists how each peripheral supports the
two request types.
Table 12-2. Request Type Support
Peripheral Single Request Signal Burst Request Signal
ADC None. FIFO not empty. Sequencer IE bit. FIFO half full.
General-purpose timer Raw interrupt pulse None
GPIO Raw interrupt pulse None
SSI TX TX FIFO not full TX FIFO level (fixed at 4)
SSI RX RX FIFO not empty RX FIFO level (fixed at 4)
UART TX TX FIFO not full TX FIFO level (configurable)
UART RX RX FIFO not empty RX FIFO level (configurable)
1039
SWCU117A–February 2015–Revised March 2015 Micro Direct Memory Access (µDMA)
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