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Table 12-1. Channel Assignments
map dma dma DMA_CHANNEL DMA DMA_CHANNEL
Channel Peripheral waitonreq stall
_wiatonreq _done _active _WITH_2STAGE_SYNC _ACTIVE_FF _ASYNC
21-31 Reserved 1 YES YES 0 0
20
(1)
Software 3 1 0 0
19
(1)
Software 2 1 0 0
18
(1)
Software 1 1 YES 0 0
17 SSP1_TX 1 YES YES 0 0
16 SSP1_RX 1 YES YES 0 0
15 AON_RTC 0 0 1
14 DMA_PROG 0 0 1
13 AON_PROG2 0 0 1
12 GPT1_B 1 YES 1 0
11 GPT1_A 1 YES 1 0
10 GPT0_B 1 YES 1 0
9 GPT0_A 1 YES 1 0
8 AUX_SW 0 0 1
7 AUX_ADC 1 YES YES 0 1 1
6 SPIS_TX 1 YES YES 0 1 1
5 SPIS_RX 1 YES YES 0 1 1
4 SSP0_TX 1 YES YES 0 0
3 SSP0_RX 1 YES YES 0 0
2 UART0_TX 1 YES YES 0 0
1 UART0_RX 1 YES YES 0 0
0
(1)
Software 0 1 y YES 0 0
(1)
DMA software trigger
1038
Micro Direct Memory Access (µDMA) SWCU117A–February 2015–Revised March 2015
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