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11.11.3.8 DOUT31_28 Register (Offset = 1Ch) [reset = X]
DOUT31_28 is shown in Figure 11-47 and described in Table 11-51.
Data Out 28 to 31 Alias register for byte access to each bit in DOUT31_0
Figure 11-47. DOUT31_28 Register
31 30 29 28 27 26 25 24
RESERVED DIO31
R-X W-X
23 22 21 20 19 18 17 16
RESERVED DIO30
R-X W-X
15 14 13 12 11 10 9 8
RESERVED DIO29
R-X W-X
7 6 5 4 3 2 1 0
RESERVED DIO28
R-X W-X
Table 11-51. DOUT31_28 Register Field Descriptions
Bit Field Type Reset Description
31-25 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
24 DIO31 W X
Sets the state of the pin that is configured as DIO#31, if the
corresponding DOE31_0 bitfield is set.
23-17 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
16 DIO30 W X
Sets the state of the pin that is configured as DIO#30, if the
corresponding DOE31_0 bitfield is set.
15-9 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
8 DIO29 W X
Sets the state of the pin that is configured as DIO#29, if the
corresponding DOE31_0 bitfield is set.
7-1 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
0 DIO28 W X
Sets the state of the pin that is configured as DIO#28, if the
corresponding DOE31_0 bitfield is set.
1020
I/O Control SWCU117A–February 2015–Revised March 2015
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