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11.11.3.1 DOUT3_0 Register (Offset = 0h) [reset = X]
DOUT3_0 is shown in Figure 11-40 and described in Table 11-44.
Data Out 0 to 3 Alias register for byte access to each bit in DOUT31_0
Figure 11-40. DOUT3_0 Register
31 30 29 28 27 26 25 24
RESERVED DIO3
R-X W-X
23 22 21 20 19 18 17 16
RESERVED DIO2
R-X W-X
15 14 13 12 11 10 9 8
RESERVED DIO1
R-X W-X
7 6 5 4 3 2 1 0
RESERVED DIO0
R-X W-X
Table 11-44. DOUT3_0 Register Field Descriptions
Bit Field Type Reset Description
31-25 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
24 DIO3 W X
Sets the state of the pin that is configured as DIO#3, if the
corresponding DOE31_0 bitfield is set.
23-17 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
16 DIO2 W X
Sets the state of the pin that is configured as DIO#2, if the
corresponding DOE31_0 bitfield is set.
15-9 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
8 DIO1 W X
Sets the state of the pin that is configured as DIO#1, if the
corresponding DOE31_0 bitfield is set.
7-1 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
0 DIO0 W X
Sets the state of the pin that is configured as DIO#0, if the
corresponding DOE31_0 bitfield is set.
1013
SWCU117A–February 2015–Revised March 2015 I/O Control
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