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Cortex-M3 Processor Registers

2.7.2.8 PCSR Register (Offset = 1Ch) [reset = 0h]

PCSR is shown in Figure 2-48 and described in Table 2-72.

Program Counter Sample This register is used to enable coarse-grained software profiling using a debug

agent, without changing the currently executing code. If the core is not in debug state, the value returned

is the instruction address of a recently executed instruction. If the core is in debug state, the value

returned is 0xFFFFFFFF.

Figure 2-48. PCSR Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

EIASAMPLE

R-0h

Table 2-72. PCSR Register Field Descriptions

Bit Field Type Reset Description

31-0 EIASAMPLE R 0h

Execution instruction address sample, or 0xFFFFFFFF if the core is

halted.

101

SWCU117A–February 2015–Revised March 2015

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