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CC26xx SimpleLink™ Wireless MCU

Technical Reference Manual

Literature Number: SWCU117A

February 2015–Revised March 2015

Summary of content (1570 pages)

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CC26xx SimpleLink™ Wireless MCU Technical Reference Manual Literature Number: SWCU117A February 2015 – Revised March 2015
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Contents Revision History .......................................................................................................................... 10 Preface....................................................................................................................................... 11 1 Architectural Overview ........................................................................................................ 13 1.1 1.2 1.3 2 2.4 2.5 2.6 2.7 The Cortex-M3 Processor Introduction ........
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www.ti.com 3.2 4 4.2 4.3 4.4 4.5 4.6 Exception Model .......................................................................................................... 4.1.1 Exception States ................................................................................................. 4.1.2 Exception Types ................................................................................................. 4.1.3 Exception Handlers ..............................................................................
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www.ti.com 6.2 7 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 8.2 9.2 531 531 534 534 534 534 534 534 537 538 539 540 540 540 540 540 541 541 541 541 542 543 669 670 Bootloader Functionality ................................................................................................. 8.1.1 Bootloader Disabling ............................................................................................ 8.1.2 Bootloader Backdoor ...............................................................................
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www.ti.com 10.2 11 10.1.3 Hardware Description .......................................................................................... 10.1.4 Module Description ............................................................................................. 10.1.5 Performance ..................................................................................................... 10.1.6 Programming Guidelines ...................................................................................... 10.1.
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www.ti.com 13.4 13.5 14 14.3 14.4 16.6 16.7 WDT Introduction ........................................................................................................ WDT Functional Description ........................................................................................... WDT Initialization and Configuration.................................................................................. Watchdog Timer Registers ............................................................................
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www.ti.com 17.5 17.6 17.7 17.8 18 1200 1203 1203 1204 1204 1204 1205 1205 1208 1208 1208 1208 1208 1209 1210 1210 1210 1211 1211 1211 1211 1211 1211 1211 1212 1221 1235 1257 1273 1282 1292 1299 Battery Monitor and Temperature Sensor........................................................................... 1311 18.1 18.2 18.3 19 17.4.2 GPIO Control .................................................................................................. 17.4.3 AUX Timers ...................................
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www.ti.com 20 Synchronous Serial Interface (SSI) .................................................................................... 1353 20.1 20.2 20.3 20.4 20.5 20.6 20.7 21 Inter-Integrated Circuit (I2C) Interface 21.1 21.2 21.3 21.4 21.5 22 Synchronous Serial Interface .......................................................................................... Block Diagram ...........................................................................................................
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www.ti.com 23.2 23.3 23.4 23.5 23.6 23.7 23.1.1 High-Level Description and Overview ...................................................................... Radio Doorbell ........................................................................................................... 23.2.1 Operational Description ...................................................................................... RF Core HAL ..................................................................................................
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Revision History www.ti.com Revision History Changes from February 21, 2015 to March 5, 2015 ........................................................................................................ Page • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 10 Changed Functional Description section ............................................................................................... 7 Changed Cortex-M3 Processor registers ...............................................................
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Preface SWCU117A – February 2015 – Revised March 2015 Read This First About This Document This technical reference manual provides information on how to use the CC26xx and the CC13xx SimpleLink™ ultra-low power wireless microcontroller devices. The CC26xx and the CC13xx families share the same MCU architecture and most of the peripherals, but the CC13xx radio is designed for use in the sub-1 GHz frequency bands while the CC26xx radio operates in the 2.4-GHz ISM frequency band.
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Related Documents www.ti.com Devices The CC26xx and the CC13xx family of devices includes both 2.4-GHz and Sub-1 GHz radios and a variety of different memory sizes, peripherals and package options. All devices are centered around an ARM Cortex-M series processor that handles the application layer and protocol stack, as well as an autonomous radio core centered around an ARM Cortex-M0 processor that handles all the low-level radio control and processing. Network processor options are available.
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Chapter 1 SWCU117A – February 2015 – Revised March 2015 Architectural Overview The CC26xx SimpleLink ultra-low power wireless MCU platforms provide solutions for a wide range of applications. To help the user develop these applications, this user's guide focuses on the use of the different building blocks of the devices. For detailed device descriptions, complete feature lists, and performance numbers, see the data sheet.
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Target Applications 1.1 www.ti.com Target Applications The CC26xx SimpleLink ultra-low power wireless MCU platforms are positioned for low-power wireless applications such as: • • • • • • • • • • • • 1.
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Overview www.ti.com Figure 1-1.
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Overview www.ti.
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Functional Overview www.ti.com In addition, the CC26xx microcontroller offers the advantages of ARM's widely available development tools, SoC infrastructure IP applications, and a large user community. Additionally, the microcontroller uses ARMThumb®-compatible Thumb®-2 instruction set to reduce memory requirements and, thereby, cost.
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Functional Overview 1.3.1.2 www.ti.com System Timer (SysTick) ARM Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit, clear-onwrite, decrementing, wrap-on-zero counter with a flexible control mechanism.
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Functional Overview www.ti.com 1.3.2.2 Flash Memory The flash block provides an in-circuit, programmable, nonvolatile program memory for the device. The flash memory is organized as a set of 4-KB pages that can be individually erased. Erasing a block causes the entire contents of the block to be reset to all 1s. These pages can be individually protected. Read-only blocks cannot be erased or programmed, protecting the contents of those blocks from being modified.
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Functional Overview www.ti.com 1.3.5 General-Purpose Timers General-purpose timers can be used to count or time external events that drive the timer-input pins. Each 16- or 32-bit GPTM block provides two 16-bit timers or counters that can be configured to operate independently as timers or event counters, or configured to operate as one 32-bit timer.
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Functional Overview www.ti.com 1.3.7 System Control and Clock System control determines the overall operation of the CC26xx device. System control provides information about the CC26xx device, controls power-saving features, controls the clocking of the CC26xx device and individual peripherals, and handles reset detection and reporting.
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Functional Overview 1.3.8.1 www.ti.com UART A UART is an integrated circuit used for RS-232C serial communications. A UART contains a transmitter (parallel-to-serial converter) and a receiver (serial-to-parallel converter); each is clocked separately. The CC26xx microcontroller includes one fully programmable UART. The UART can generate individually masked interrupts from the receive (RX), transmit (TX), modem flow control, and error conditions.
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Functional Overview www.ti.com • • • 1.3.8.
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Functional Overview www.ti.com 1.3.9 Programmable IOs IO pins offer flexibility for a variety of connections. The CC26xx supports highly configurable IO pins which can be muxed to any digital peripheral through the IO Controller. Note that analog functionality, Sensor Controller connections and high drive strength is limited to certain pins. Refer to the I/O Control chapter for details.
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Functional Overview www.ti.com • • ADC The ADC is a 12-bit, 200 ksamples/s ADC with eight inputs and a built-in voltage reference. The ADC can be triggered by many different sources, including timers, I/O pins, software, the analog comparator, and the RTC. An ADC is a peripheral that converts a continuous analog voltage to a discrete digital number.
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Functional Overview www.ti.com Figure 1-2. CC26xx Supply System VDDS POR / BOD / Misc Global LDO IOs Digital LDO VDD VDDS2 IOs Micro LDO VDDS3 IOs VDDS_DCDC AON_VD DCDC_SW DC/DC Converter MCU_VD VDDR VDDR_RF Oscillators RF LDOs DCOUPL 1.3.13.1.1 VDDS The battery voltage on the CC26xx family is called VDDS (supply). This supply has the highest potential in the system and typically is the only one provided by the user.
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Functional Overview www.ti.com 1.3.13.1.3 Digital Core Supply The digital core of the CC26xx is supplied by a 1.28-V regulator connected to VDDR. The output of this regulator requires an external decoupling capacitor for proper operation; this capacitor must be connected to the DCOUPL pin. NOTE: The DCOUPL pin cannot be used to supply external circuitry.
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Chapter 2 SWCU117A – February 2015 – Revised March 2015 The Cortex-M3 Processor The CC26xx family of microcontrollers builds on Cortex-M3 core to bring high-performance 32-bit computing to cost-sensitive embedded microcontroller applications, such as factory automation and control, industrial control power devices, building and home automation, and stepper motor control. This chapter provides information on the CC26xx implementation of the Cortex-M3 processor.
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The Cortex-M3 Processor Introduction www.ti.com 2.1 The Cortex-M3 Processor Introduction The ARM® Cortex™-M3 processor provides a high-performance, low-cost platform that meets the system requirements of minimal memory implementation, reduced pin count, and low power consumption. The following features included: • • • • • • • • • • • • • • • • 2.
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Overview www.ti.com The Cortex-M3 processor closely integrates a nested vector interrupt controller (NVIC) to deliver fast execution of interrupt service routines (ISRs) thereby dramatically reducing interrupt latency. The hardware stacking of registers and the ability to suspend load-multiple and store-multiple operations further reduces interrupt latency. Interrupt handlers do not require any assembler stubs, thus removing code overhead from the ISRs.
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Overview www.ti.com The flash patch and breakpoint unit (FPB) provides up to eight hardware breakpoint comparators that debuggers can use. The comparators in the FPB also provide remap functions of up to eight words in the program code in the CODE memory region. Remap functions enable patching of applications stored in a read-only area of flash memory into another area of on-chip SRAM or flash memory. If a patch is required, the application programs the FPB to remap a number of addresses.
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Programming Model www.ti.com 2.4.1 Processor Mode and Privilege Levels for Software Execution The Cortex-M3 has two modes of operation: 1. Thread mode: Used to execute application software. The processor enters thread mode when it comes out of reset. 2. Handler mode: Used to handle exceptions. When the processor completes exception processing, it returns to thread mode. In addition, the Cortex-M3 has two privilege levels, unprivileged and privileged. 1.
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Coretex-M3 Core Registers www.ti.com 2.5 Coretex-M3 Core Registers Figure 2-3 shows the Cortex-M3 register set. Table 2-2 lists the core registers. The core registers are not memory mapped and are accessed by register name, so the base address is N/A (not applicable) and there is no offset. Figure 2-3.
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Coretex-M3 Core Registers www.ti.com 2.5.1 Core Register Map Table 2-2. Processor Register Map Name Type Reset Description Link R0 R/W – Cortex general-purpose register 0 See Section 2.5.2.1. R1 R/W – Cortex general-purpose register 1 See Section 2.5.2.2. R2 R/W – Cortex general-purpose register 2 See Section 2.5.2.3. R3 R/W – Cortex general-purpose register 3 See Section 2.5.2.4. R4 R/W – Cortex general-purpose register 4 See Section 2.5.2.5.
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Coretex-M3 Core Registers www.ti.com 2.5.2.2 Cortex General-Purpose Register 1 (R1) Table 2-4. Cortex General-Purpose Register 1 (R1) Address Offset Reset Physical Address – Instance Description The R1 registers are 32-bit general-purpose registers for data operations and can be accessed from either privileged or unprivileged mode.
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Coretex-M3 Core Registers 2.5.2.5 www.ti.com Cortex General-Purpose Register 4 (R4) Table 2-7. Cortex General-Purpose Register 4 (R4) Address Offset Reset Physical Address – Instance Description The R4 registers are 32-bit general-purpose registers for data operations and can be accessed from either privileged or unprivileged mode.
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Coretex-M3 Core Registers www.ti.com 2.5.2.8 Cortex General-Purpose Register 7 (R7) Table 2-10. Cortex General-Purpose Register 7 (R7) Address Offset Reset Physical Address – Instance Description The R7 registers are 32-bit general-purpose registers for data operations and can be accessed from either privileged or unprivileged mode.
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Coretex-M3 Core Registers www.ti.com 2.5.2.11 Cortex General-Purpose Register 10 (R10) Table 2-13. Cortex General-Purpose Register 10 (R10) Address Offset Reset Physical Address – Instance Description The R10 registers are 32-bit general-purpose registers for data operations and can be accessed from either privileged or unprivileged mode.
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Coretex-M3 Core Registers www.ti.com 2.5.2.14 Stack Pointer (SP) Table 2-16. Stack Pointer (SP) Address Offset Reset Physical Address Instance – Description The Stack Pointer (SP) is register R13. In thread mode, the function of this register changes depending on the ASP bit in the Control Register (CONTROL) register. When the ASP bit is clear, this register is the Main Stack Pointer (MSP). When the ASP bit is set, this register is the Process Stack Pointer (PSP).
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Coretex-M3 Core Registers www.ti.com 2.5.2.16 Program Counter (PC) Table 2-18. Program Counter (PC) Address Offset Reset Physical Address Instance – Description The Program Counter (PC) is register R15, and it contains the current program address. On reset, the processor loads the PC with the value of the reset vector, which is at address 0x0000 0004. Bit 0 of the reset vector is loaded into the THUMB bit of the EPSR register at reset and must be 1.
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Coretex-M3 Core Registers www.ti.com Table 2-20. Program Status Register (PSR) Address Offset Reset Physical Address Instance 0x0100 0000 Description Note: This register is also referred to as xPSR.
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Coretex-M3 Core Registers Bits Field Name www.ti.com Description 1 The previous operation resulted in an overflow. 0 The previous operation did not result in an overflow. Type Reset R/W 0 The value of this bit is meaningful only when accessing PSR or APSR. 27 Q APSR Sticky Overflow and Saturation Flag Value Description 1 Overflow or Saturation has occurred. (set by SSAT or USAT instructions). 0 Overflow or saturation has not occurred since reset or since the bit was last cleared.
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Coretex-M3 Core Registers www.ti.com Bits Field Name Description 0x03 Hard fault 0x04 Memory management fault 0x05 Bus fault 0x06 Usage fault 0x070x0A Reserved 0x0B SVCall 0x0C Reserved for debug 0x0D Reserved 0x0E PendSV 0x0F SysTick 0x10 Interrupt vector 0 0x11 Interrupt vector 1 ... ... 0x31 Interrupt vector 33 0x320x7F Reserved Type Reset For more information, see Section 4.1.2, Exception Types. The value of this field is meaningful only when accessing PSR or IPSR.
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Coretex-M3 Core Registers www.ti.com 2.5.2.18 Priority Mask Register (PRIMASK) Table 2-21. Priority Mask Register (PRIMASK) Address Offset Reset Physical Address Instance 0x0000 0000 Description The Priority Mask (PRIMASK) register prevents activation of all exceptions with programmable priority. Reset, nonmaskable interrupt (NMI), and hard fault are the only exceptions with fixed priority. Exceptions must be disabled when they might impact the timing of critical tasks.
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Coretex-M3 Core Registers www.ti.com 2.5.2.19 Fault Mask Register (FAULTMASK) Table 2-22. Fault Mask Register (FAULTMASK) Address Offset Reset Physical Address Instance 0x0000 0000 Description The Fault Mask FAULTMASK register prevents activation of all exceptions except for the NMI. Exceptions must be disabled when they might impact the timing of critical tasks. This register is accessible only in privileged mode.
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Coretex-M3 Core Registers www.ti.com 2.5.2.20 Base Priority Mask Register (BASEPRI) Table 2-23. Base Priority Mask Register (BASEPRI) Address Offset Reset Physical Address Instance 0x0000 0000 Description The Base Priority Mask BASEPRI register defines the minimum priority for exception processing. When BASEPRI is set to a nonzero value, it prevents the activation of all exceptions with the same or lower priority level as the BASEPRI value.
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Instruction Set Summary www.ti.com 2.5.2.21 Control Register (CONTROL) Table 2-24. Control Register (CONTROL) Address Offset Reset Physical Address Instance 0x0000 0000 Description The CONTROL register controls the stack used and the privilege level for software execution when the processor is in thread mode. This register is accessible only in privileged mode. Handler mode always uses MSP, so the processor ignores explicit writes to the ASP bit of the CONTROL register when in handler mode.
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Instruction Set Summary www.ti.com Table 2-25.
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Instruction Set Summary www.ti.com Table 2-25.
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Cortex-M3 Processor Registers www.ti.com Table 2-25. Cortex-M3 Instruction Summary (continued) Mnemonic 2.
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Cortex-M3 Processor Registers www.ti.com 2.7.1 CPU_ITM Registers Table 2-26 lists the memory-mapped registers for the CPU_ITM. All register offset addresses not listed in Table 2-26 should be considered as reserved locations and the register contents should not be modified. Table 2-26. CPU_ITM Registers Offset Acronym Register Name Section 0h STIM0 Stimulus Port 0 Section 2.7.1.1 4h STIM1 Stimulus Port 1 Section 2.7.1.2 8h STIM2 Stimulus Port 2 Section 2.7.1.
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Cortex-M3 Processor Registers 2.7.1.1 www.ti.com STIM0 Register (Offset = 0h) [reset = 0h] STIM0 is shown in Figure 2-4 and described in Table 2-27. Stimulus Port 0 Figure 2-4. STIM0 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 STIM0 R/W-0h 9 8 7 6 5 4 3 2 1 0 Table 2-27. STIM0 Register Field Descriptions Bit 31-0 52 Field Type Reset Description STIM0 R/W 0h A write to this location causes data to be written into the FIFO if TER.STIMENA0 is set.
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Cortex-M3 Processor Registers www.ti.com 2.7.1.2 STIM1 Register (Offset = 4h) [reset = 0h] STIM1 is shown in Figure 2-5 and described in Table 2-28. Stimulus Port 1 Figure 2-5. STIM1 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 STIM1 R/W-0h 9 8 7 6 5 4 3 2 1 0 Table 2-28. STIM1 Register Field Descriptions Bit 31-0 Field Type Reset Description STIM1 R/W 0h A write to this location causes data to be written into the FIFO if TER.STIMENA1 is set.
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Cortex-M3 Processor Registers 2.7.1.3 www.ti.com STIM2 Register (Offset = 8h) [reset = 0h] STIM2 is shown in Figure 2-6 and described in Table 2-29. Stimulus Port 2 Figure 2-6. STIM2 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 STIM2 R/W-0h 9 8 7 6 5 4 3 2 1 0 Table 2-29. STIM2 Register Field Descriptions Bit 31-0 54 Field Type Reset Description STIM2 R/W 0h A write to this location causes data to be written into the FIFO if TER.STIMENA2 is set.
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Cortex-M3 Processor Registers www.ti.com 2.7.1.4 STIM3 Register (Offset = Ch) [reset = 0h] STIM3 is shown in Figure 2-7 and described in Table 2-30. Stimulus Port 3 Figure 2-7. STIM3 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 STIM3 R/W-0h 9 8 7 6 5 4 3 2 1 0 Table 2-30. STIM3 Register Field Descriptions Bit 31-0 Field Type Reset Description STIM3 R/W 0h A write to this location causes data to be written into the FIFO if TER.STIMENA3 is set.
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Cortex-M3 Processor Registers 2.7.1.5 www.ti.com STIM4 Register (Offset = 10h) [reset = 0h] STIM4 is shown in Figure 2-8 and described in Table 2-31. Stimulus Port 4 Figure 2-8. STIM4 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 STIM4 R/W-0h 9 8 7 6 5 4 3 2 1 0 Table 2-31. STIM4 Register Field Descriptions Bit 31-0 56 Field Type Reset Description STIM4 R/W 0h A write to this location causes data to be written into the FIFO if TER.STIMENA4 is set.
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Cortex-M3 Processor Registers www.ti.com 2.7.1.6 STIM5 Register (Offset = 14h) [reset = 0h] STIM5 is shown in Figure 2-9 and described in Table 2-32. Stimulus Port 5 Figure 2-9. STIM5 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 STIM5 R/W-0h 9 8 7 6 5 4 3 2 1 0 Table 2-32. STIM5 Register Field Descriptions Bit 31-0 Field Type Reset Description STIM5 R/W 0h A write to this location causes data to be written into the FIFO if TER.STIMENA5 is set.
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Cortex-M3 Processor Registers 2.7.1.7 www.ti.com STIM6 Register (Offset = 18h) [reset = 0h] STIM6 is shown in Figure 2-10 and described in Table 2-33. Stimulus Port 6 Figure 2-10. STIM6 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 STIM6 R/W-0h 9 8 7 6 5 4 3 2 1 0 Table 2-33. STIM6 Register Field Descriptions Bit 31-0 58 Field Type Reset Description STIM6 R/W 0h A write to this location causes data to be written into the FIFO if TER.STIMENA6 is set.
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Cortex-M3 Processor Registers www.ti.com 2.7.1.8 STIM7 Register (Offset = 1Ch) [reset = 0h] STIM7 is shown in Figure 2-11 and described in Table 2-34. Stimulus Port 7 Figure 2-11. STIM7 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 STIM7 R/W-0h 9 8 7 6 5 4 3 2 1 0 Table 2-34. STIM7 Register Field Descriptions Bit 31-0 Field Type Reset Description STIM7 R/W 0h A write to this location causes data to be written into the FIFO if TER.STIMENA7 is set.
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Cortex-M3 Processor Registers 2.7.1.9 www.ti.com STIM8 Register (Offset = 20h) [reset = 0h] STIM8 is shown in Figure 2-12 and described in Table 2-35. Stimulus Port 8 Figure 2-12. STIM8 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 STIM8 R/W-0h 9 8 7 6 5 4 3 2 1 0 Table 2-35. STIM8 Register Field Descriptions Bit 31-0 60 Field Type Reset Description STIM8 R/W 0h A write to this location causes data to be written into the FIFO if TER.STIMENA8 is set.
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Cortex-M3 Processor Registers www.ti.com 2.7.1.10 STIM9 Register (Offset = 24h) [reset = 0h] STIM9 is shown in Figure 2-13 and described in Table 2-36. Stimulus Port 9 Figure 2-13. STIM9 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 STIM9 R/W-0h 9 8 7 6 5 4 3 2 1 0 Table 2-36. STIM9 Register Field Descriptions Bit 31-0 Field Type Reset Description STIM9 R/W 0h A write to this location causes data to be written into the FIFO if TER.STIMENA9 is set.
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Cortex-M3 Processor Registers www.ti.com 2.7.1.11 STIM10 Register (Offset = 28h) [reset = 0h] STIM10 is shown in Figure 2-14 and described in Table 2-37. Stimulus Port 10 Figure 2-14. STIM10 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 STIM10 R/W-0h 9 8 7 6 5 4 3 2 1 0 Table 2-37. STIM10 Register Field Descriptions Bit 31-0 62 Field Type Reset Description STIM10 R/W 0h A write to this location causes data to be written into the FIFO if TER.
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Cortex-M3 Processor Registers www.ti.com 2.7.1.12 STIM11 Register (Offset = 2Ch) [reset = 0h] STIM11 is shown in Figure 2-15 and described in Table 2-38. Stimulus Port 11 Figure 2-15. STIM11 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 STIM11 R/W-0h 9 8 7 6 5 4 3 2 1 0 Table 2-38. STIM11 Register Field Descriptions Bit 31-0 Field Type Reset Description STIM11 R/W 0h A write to this location causes data to be written into the FIFO if TER.STIMENA11 is set.
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Cortex-M3 Processor Registers www.ti.com 2.7.1.13 STIM12 Register (Offset = 30h) [reset = 0h] STIM12 is shown in Figure 2-16 and described in Table 2-39. Stimulus Port 12 Figure 2-16. STIM12 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 STIM12 R/W-0h 9 8 7 6 5 4 3 2 1 0 Table 2-39. STIM12 Register Field Descriptions Bit 31-0 64 Field Type Reset Description STIM12 R/W 0h A write to this location causes data to be written into the FIFO if TER.
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Cortex-M3 Processor Registers www.ti.com 2.7.1.14 STIM13 Register (Offset = 34h) [reset = 0h] STIM13 is shown in Figure 2-17 and described in Table 2-40. Stimulus Port 13 Figure 2-17. STIM13 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 STIM13 R/W-0h 9 8 7 6 5 4 3 2 1 0 Table 2-40. STIM13 Register Field Descriptions Bit 31-0 Field Type Reset Description STIM13 R/W 0h A write to this location causes data to be written into the FIFO if TER.STIMENA13 is set.
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Cortex-M3 Processor Registers www.ti.com 2.7.1.15 STIM14 Register (Offset = 38h) [reset = 0h] STIM14 is shown in Figure 2-18 and described in Table 2-41. Stimulus Port 14 Figure 2-18. STIM14 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 STIM14 R/W-0h 9 8 7 6 5 4 3 2 1 0 Table 2-41. STIM14 Register Field Descriptions Bit 31-0 66 Field Type Reset Description STIM14 R/W 0h A write to this location causes data to be written into the FIFO if TER.
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Cortex-M3 Processor Registers www.ti.com 2.7.1.16 STIM15 Register (Offset = 3Ch) [reset = 0h] STIM15 is shown in Figure 2-19 and described in Table 2-42. Stimulus Port 15 Figure 2-19. STIM15 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 STIM15 R/W-0h 9 8 7 6 5 4 3 2 1 0 Table 2-42. STIM15 Register Field Descriptions Bit 31-0 Field Type Reset Description STIM15 R/W 0h A write to this location causes data to be written into the FIFO if TER.STIMENA15 is set.
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Cortex-M3 Processor Registers www.ti.com 2.7.1.17 STIM16 Register (Offset = 40h) [reset = 0h] STIM16 is shown in Figure 2-20 and described in Table 2-43. Stimulus Port 16 Figure 2-20. STIM16 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 STIM16 R/W-0h 9 8 7 6 5 4 3 2 1 0 Table 2-43. STIM16 Register Field Descriptions Bit 31-0 68 Field Type Reset Description STIM16 R/W 0h A write to this location causes data to be written into the FIFO if TER.
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Cortex-M3 Processor Registers www.ti.com 2.7.1.18 STIM17 Register (Offset = 44h) [reset = 0h] STIM17 is shown in Figure 2-21 and described in Table 2-44. Stimulus Port 17 Figure 2-21. STIM17 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 STIM17 R/W-0h 9 8 7 6 5 4 3 2 1 0 Table 2-44. STIM17 Register Field Descriptions Bit 31-0 Field Type Reset Description STIM17 R/W 0h A write to this location causes data to be written into the FIFO if TER.STIMENA17 is set.
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Cortex-M3 Processor Registers www.ti.com 2.7.1.19 STIM18 Register (Offset = 48h) [reset = 0h] STIM18 is shown in Figure 2-22 and described in Table 2-45. Stimulus Port 18 Figure 2-22. STIM18 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 STIM18 R/W-0h 9 8 7 6 5 4 3 2 1 0 Table 2-45. STIM18 Register Field Descriptions Bit 31-0 70 Field Type Reset Description STIM18 R/W 0h A write to this location causes data to be written into the FIFO if TER.
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Cortex-M3 Processor Registers www.ti.com 2.7.1.20 STIM19 Register (Offset = 4Ch) [reset = 0h] STIM19 is shown in Figure 2-23 and described in Table 2-46. Stimulus Port 19 Figure 2-23. STIM19 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 STIM19 R/W-0h 9 8 7 6 5 4 3 2 1 0 Table 2-46. STIM19 Register Field Descriptions Bit 31-0 Field Type Reset Description STIM19 R/W 0h A write to this location causes data to be written into the FIFO if TER.STIMENA19 is set.
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Cortex-M3 Processor Registers www.ti.com 2.7.1.21 STIM20 Register (Offset = 50h) [reset = 0h] STIM20 is shown in Figure 2-24 and described in Table 2-47. Stimulus Port 20 Figure 2-24. STIM20 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 STIM20 R/W-0h 9 8 7 6 5 4 3 2 1 0 Table 2-47. STIM20 Register Field Descriptions Bit 31-0 72 Field Type Reset Description STIM20 R/W 0h A write to this location causes data to be written into the FIFO if TER.
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Cortex-M3 Processor Registers www.ti.com 2.7.1.22 STIM21 Register (Offset = 54h) [reset = 0h] STIM21 is shown in Figure 2-25 and described in Table 2-48. Stimulus Port 21 Figure 2-25. STIM21 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 STIM21 R/W-0h 9 8 7 6 5 4 3 2 1 0 Table 2-48. STIM21 Register Field Descriptions Bit 31-0 Field Type Reset Description STIM21 R/W 0h A write to this location causes data to be written into the FIFO if TER.STIMENA21 is set.
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Cortex-M3 Processor Registers www.ti.com 2.7.1.23 STIM22 Register (Offset = 58h) [reset = 0h] STIM22 is shown in Figure 2-26 and described in Table 2-49. Stimulus Port 22 Figure 2-26. STIM22 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 STIM22 R/W-0h 9 8 7 6 5 4 3 2 1 0 Table 2-49. STIM22 Register Field Descriptions Bit 31-0 74 Field Type Reset Description STIM22 R/W 0h A write to this location causes data to be written into the FIFO if TER.
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Cortex-M3 Processor Registers www.ti.com 2.7.1.24 STIM23 Register (Offset = 5Ch) [reset = 0h] STIM23 is shown in Figure 2-27 and described in Table 2-50. Stimulus Port 23 Figure 2-27. STIM23 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 STIM23 R/W-0h 9 8 7 6 5 4 3 2 1 0 Table 2-50. STIM23 Register Field Descriptions Bit 31-0 Field Type Reset Description STIM23 R/W 0h A write to this location causes data to be written into the FIFO if TER.STIMENA23 is set.
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Cortex-M3 Processor Registers www.ti.com 2.7.1.25 STIM24 Register (Offset = 60h) [reset = 0h] STIM24 is shown in Figure 2-28 and described in Table 2-51. Stimulus Port 24 Figure 2-28. STIM24 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 STIM24 R/W-0h 9 8 7 6 5 4 3 2 1 0 Table 2-51. STIM24 Register Field Descriptions Bit 31-0 76 Field Type Reset Description STIM24 R/W 0h A write to this location causes data to be written into the FIFO if TER.
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Cortex-M3 Processor Registers www.ti.com 2.7.1.26 STIM25 Register (Offset = 64h) [reset = 0h] STIM25 is shown in Figure 2-29 and described in Table 2-52. Stimulus Port 25 Figure 2-29. STIM25 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 STIM25 R/W-0h 9 8 7 6 5 4 3 2 1 0 Table 2-52. STIM25 Register Field Descriptions Bit 31-0 Field Type Reset Description STIM25 R/W 0h A write to this location causes data to be written into the FIFO if TER.STIMENA25 is set.
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Cortex-M3 Processor Registers www.ti.com 2.7.1.27 STIM26 Register (Offset = 68h) [reset = 0h] STIM26 is shown in Figure 2-30 and described in Table 2-53. Stimulus Port 26 Figure 2-30. STIM26 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 STIM26 R/W-0h 9 8 7 6 5 4 3 2 1 0 Table 2-53. STIM26 Register Field Descriptions Bit 31-0 78 Field Type Reset Description STIM26 R/W 0h A write to this location causes data to be written into the FIFO if TER.
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Cortex-M3 Processor Registers www.ti.com 2.7.1.28 STIM27 Register (Offset = 6Ch) [reset = 0h] STIM27 is shown in Figure 2-31 and described in Table 2-54. Stimulus Port 27 Figure 2-31. STIM27 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 STIM27 R/W-0h 9 8 7 6 5 4 3 2 1 0 Table 2-54. STIM27 Register Field Descriptions Bit 31-0 Field Type Reset Description STIM27 R/W 0h A write to this location causes data to be written into the FIFO if TER.STIMENA27 is set.
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Cortex-M3 Processor Registers www.ti.com 2.7.1.29 STIM28 Register (Offset = 70h) [reset = 0h] STIM28 is shown in Figure 2-32 and described in Table 2-55. Stimulus Port 28 Figure 2-32. STIM28 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 STIM28 R/W-0h 9 8 7 6 5 4 3 2 1 0 Table 2-55. STIM28 Register Field Descriptions Bit 31-0 80 Field Type Reset Description STIM28 R/W 0h A write to this location causes data to be written into the FIFO if TER.
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Cortex-M3 Processor Registers www.ti.com 2.7.1.30 STIM29 Register (Offset = 74h) [reset = 0h] STIM29 is shown in Figure 2-33 and described in Table 2-56. Stimulus Port 29 Figure 2-33. STIM29 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 STIM29 R/W-0h 9 8 7 6 5 4 3 2 1 0 Table 2-56. STIM29 Register Field Descriptions Bit 31-0 Field Type Reset Description STIM29 R/W 0h A write to this location causes data to be written into the FIFO if TER.STIMENA29 is set.
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Cortex-M3 Processor Registers www.ti.com 2.7.1.31 STIM30 Register (Offset = 78h) [reset = 0h] STIM30 is shown in Figure 2-34 and described in Table 2-57. Stimulus Port 30 Figure 2-34. STIM30 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 STIM30 R/W-0h 9 8 7 6 5 4 3 2 1 0 Table 2-57. STIM30 Register Field Descriptions Bit 31-0 82 Field Type Reset Description STIM30 R/W 0h A write to this location causes data to be written into the FIFO if TER.
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Cortex-M3 Processor Registers www.ti.com 2.7.1.32 STIM31 Register (Offset = 7Ch) [reset = 0h] STIM31 is shown in Figure 2-35 and described in Table 2-58. Stimulus Port 31 Figure 2-35. STIM31 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 STIM31 R/W-0h 9 8 7 6 5 4 3 2 1 0 Table 2-58. STIM31 Register Field Descriptions Bit 31-0 Field Type Reset Description STIM31 R/W 0h A write to this location causes data to be written into the FIFO if TER.STIMENA31 is set.
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Cortex-M3 Processor Registers www.ti.com 2.7.1.33 TER Register (Offset = E00h) [reset = X] TER is shown in Figure 2-36 and described in Table 2-59. Trace Enable Use the Trace Enable Register to generate trace data by writing to the corresponding stimulus port. Note: Privileged writes are accepted to this register if TCR.ITMENA is set. User writes are accepted to this register if TCR.ITMENA is set and the appropriate privilege mask is cleared.
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Cortex-M3 Processor Registers www.ti.com Table 2-59. TER Register Field Descriptions (continued) Bit Field Type Reset Description 9 STIMENA9 R/W X Bit mask to enable tracing on ITM stimulus port 9. 8 STIMENA8 R/W X Bit mask to enable tracing on ITM stimulus port 8. 7 STIMENA7 R/W X Bit mask to enable tracing on ITM stimulus port 7. 6 STIMENA6 R/W X Bit mask to enable tracing on ITM stimulus port 6. 5 STIMENA5 R/W X Bit mask to enable tracing on ITM stimulus port 5.
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Cortex-M3 Processor Registers www.ti.com 2.7.1.34 TPR Register (Offset = E40h) [reset = X] TPR is shown in Figure 2-37 and described in Table 2-60. Trace Privilege This register is used to enable an operating system to control which stimulus ports are accessible by user code. This register can only be used in privileged mode. Figure 2-37.
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Cortex-M3 Processor Registers www.ti.com 2.7.1.35 TCR Register (Offset = E80h) [reset = X] TCR is shown in Figure 2-38 and described in Table 2-61. Trace Control Use this register to configure and control ITM transfers. This register can only be written in privilege mode. DWT is not enabled in the ITM block. However, DWT stimulus entry into the FIFO is controlled by DWTENA. If DWT requires timestamping, the TSENA bit must be set. Figure 2-38.
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Cortex-M3 Processor Registers www.ti.com Table 2-61. TCR Register Field Descriptions (continued) Bit 88 Field Type Reset Description 1 TSENA R/W X Enables differential timestamps. Differential timestamps are emitted when a packet is written to the FIFO with a non-zero timestamp counter, and when the timestamp counter overflows. Timestamps are emitted during idle times after a fixed number of two million cycles. This provides a time reference for packets and inter-packet gaps.
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Cortex-M3 Processor Registers www.ti.com 2.7.1.36 LAR Register (Offset = FB0h) [reset = X] LAR is shown in Figure 2-39 and described in Table 2-62. Lock Access This register is used to prevent write accesses to the Control Registers: TER, TPR and TCR. Figure 2-39. LAR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 LOCK_ACCESS W-X 9 8 7 6 5 4 3 2 1 0 Table 2-62.
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Cortex-M3 Processor Registers www.ti.com 2.7.1.37 LSR Register (Offset = FB4h) [reset = X] LSR is shown in Figure 2-40 and described in Table 2-63. Lock Status Use this register to enable write accesses to the Control Register. Figure 2-40. LSR Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 BYTEACC R-X 1 ACCESS R-1h 0 PRESENT R-1h RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 RESERVED R-X 4 Table 2-63.
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Cortex-M3 Processor Registers www.ti.
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Cortex-M3 Processor Registers www.ti.com 2.7.2 CPU_DWT Registers Table 2-64 lists the memory-mapped registers for the CPU_DWT. All register offset addresses not listed in Table 2-64 should be considered as reserved locations and the register contents should not be modified. Table 2-64. CPU_DWT Registers Offset 92 Acronym Register Name 0h CTRL Control Section 2.7.2.1 Section 4h CYCCNT Current PC Sampler Cycle Count Section 2.7.2.2 8h CPICNT CPI Count Section 2.7.2.
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Cortex-M3 Processor Registers www.ti.com 2.7.2.1 CTRL Register (Offset = 0h) [reset = X] CTRL is shown in Figure 2-41 and described in Table 2-65. Control Use the DWT Control Register to enable the DWT unit. Figure 2-41.
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Cortex-M3 Processor Registers www.ti.com Table 2-65. CTRL Register Field Descriptions (continued) Bit Field Type Reset Description RESERVED R/W X Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. PCSAMPLEENA R/W X Enables PC Sampling event. A PC sample event is emitted when the POSTCNT counter triggers it. See CYCTAP and POSTPRESET for details. Enabling this bit overrides CYCEVTENA. 0: PC Sampling event disabled.
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Cortex-M3 Processor Registers www.ti.com 2.7.2.2 CYCCNT Register (Offset = 4h) [reset = X] CYCCNT is shown in Figure 2-42 and described in Table 2-66. Current PC Sampler Cycle Count This register is used to count the number of core cycles. This counter can measure elapsed execution time. This is a free-running counter (this counter will not advance in power modes where free-running clock to CPU stops). The counter has three functions: 1: When CTRL.
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Cortex-M3 Processor Registers 2.7.2.3 www.ti.com CPICNT Register (Offset = 8h) [reset = X] CPICNT is shown in Figure 2-43 and described in Table 2-67. CPI Count This register is used to count the total number of instruction cycles beyond the first cycle. Figure 2-43. CPICNT Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R/W-X 9 8 7 6 5 4 3 2 CPICNT R/W-0h 1 0 Table 2-67.
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Cortex-M3 Processor Registers www.ti.com 2.7.2.4 EXCCNT Register (Offset = Ch) [reset = X] EXCCNT is shown in Figure 2-44 and described in Table 2-68. Exception Overhead Count This register is used to count the total cycles spent in interrupt processing. Figure 2-44. EXCCNT Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R/W-X 9 8 7 6 5 4 3 2 EXCCNT R/W-0h 1 0 Table 2-68.
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Cortex-M3 Processor Registers 2.7.2.5 www.ti.com SLEEPCNT Register (Offset = 10h) [reset = X] SLEEPCNT is shown in Figure 2-45 and described in Table 2-69. Sleep Count This register is used to count the total number of cycles during which the processor is sleeping. Figure 2-45. SLEEPCNT Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R/W-X 9 8 7 6 5 4 3 2 SLEEPCNT R/W-0h 1 0 Table 2-69.
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Cortex-M3 Processor Registers www.ti.com 2.7.2.6 LSUCNT Register (Offset = 14h) [reset = X] LSUCNT is shown in Figure 2-46 and described in Table 2-70. LSU Count This register is used to count the total number of cycles during which the processor is processing an LSU operation beyond the first cycle. Figure 2-46. LSUCNT Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R/W-X 9 8 7 6 5 4 3 2 LSUCNT R/W-0h 1 0 Table 2-70.
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Cortex-M3 Processor Registers 2.7.2.7 www.ti.com FOLDCNT Register (Offset = 18h) [reset = X] FOLDCNT is shown in Figure 2-47 and described in Table 2-71. Fold Count This register is used to count the total number of folded instructions. The counter increments on each instruction which takes 0 cycles. Figure 2-47. FOLDCNT Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R/W-X 9 8 7 6 5 4 3 2 FOLDCNT R/W-0h 1 0 Table 2-71.
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Cortex-M3 Processor Registers www.ti.com 2.7.2.8 PCSR Register (Offset = 1Ch) [reset = 0h] PCSR is shown in Figure 2-48 and described in Table 2-72. Program Counter Sample This register is used to enable coarse-grained software profiling using a debug agent, without changing the currently executing code. If the core is not in debug state, the value returned is the instruction address of a recently executed instruction. If the core is in debug state, the value returned is 0xFFFFFFFF. Figure 2-48.
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Cortex-M3 Processor Registers 2.7.2.9 www.ti.com COMP0 Register (Offset = 20h) [reset = 0h] COMP0 is shown in Figure 2-49 and described in Table 2-73. Comparator 0 This register is used to write the reference value for comparator 0. Figure 2-49. COMP0 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 COMP R/W-0h 9 8 7 6 5 4 3 2 1 0 Table 2-73.
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Cortex-M3 Processor Registers www.ti.com 2.7.2.10 MASK0 Register (Offset = 24h) [reset = X] MASK0 is shown in Figure 2-50 and described in Table 2-74. Mask 0 Use the DWT Mask Registers 0 to apply a mask to data addresses when matching against COMP0. Figure 2-50. MASK0 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R/W-X 9 8 7 6 5 4 3 2 1 0 MASK R/W-0h Table 2-74.
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Cortex-M3 Processor Registers www.ti.com 2.7.2.11 FUNCTION0 Register (Offset = 28h) [reset = X] FUNCTION0 is shown in Figure 2-51 and described in Table 2-75. Function 0 Use the DWT Function Registers 0 to control the operation of the comparator 0. This comparator can: 1. Match against either the PC or the data address. This is controlled by CYCMATCH. This function is only available for comparator 0 (COMP0). 2.
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Cortex-M3 Processor Registers www.ti.com Table 2-75. FUNCTION0 Register Field Descriptions (continued) Bit Field Type Reset Description 3-0 FUNCTION R/W X Function settings. 0x0: Disabled 0x1: EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit address offset through ITM 0x2: EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, emit data and address offset through ITM on read or write. 0x3: EMITRANGE = 0, sample PC and data value through ITM on read or write.
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Cortex-M3 Processor Registers www.ti.com 2.7.2.12 COMP1 Register (Offset = 30h) [reset = 0h] COMP1 is shown in Figure 2-52 and described in Table 2-76. Comparator 1 This register is used to write the reference value for comparator 1. Figure 2-52. COMP1 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 COMP R/W-0h 9 8 7 6 5 4 3 2 1 0 Table 2-76.
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Cortex-M3 Processor Registers www.ti.com 2.7.2.13 MASK1 Register (Offset = 34h) [reset = X] MASK1 is shown in Figure 2-53 and described in Table 2-77. Mask 1 Use the DWT Mask Registers 1 to apply a mask to data addresses when matching against COMP1. Figure 2-53. MASK1 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R/W-X 9 8 7 6 5 4 3 2 1 0 MASK R/W-0h Table 2-77.
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Cortex-M3 Processor Registers www.ti.com 2.7.2.14 FUNCTION1 Register (Offset = 38h) [reset = X] FUNCTION1 is shown in Figure 2-54 and described in Table 2-78. Function 1 Use the DWT Function Registers 1 to control the operation of the comparator 1. This comparator can: 1. Perform data value comparisons if associated address comparators have performed an address match. This function is only available for comparator 1 (COMP1). 2.
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Cortex-M3 Processor Registers www.ti.com Table 2-78. FUNCTION1 Register Field Descriptions (continued) Bit Field Type Reset Description 3-0 FUNCTION R/W X Function settings: 0x0: Disabled 0x1: EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit address offset through ITM 0x2: EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, emit data and address offset through ITM on read or write. 0x3: EMITRANGE = 0, sample PC and data value through ITM on read or write.
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Cortex-M3 Processor Registers www.ti.com 2.7.2.15 COMP2 Register (Offset = 40h) [reset = 0h] COMP2 is shown in Figure 2-55 and described in Table 2-79. Comparator 2 This register is used to write the reference value for comparator 2. Figure 2-55. COMP2 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 COMP R/W-0h 9 8 7 6 5 4 3 2 1 0 Table 2-79.
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Cortex-M3 Processor Registers www.ti.com 2.7.2.16 MASK2 Register (Offset = 44h) [reset = X] MASK2 is shown in Figure 2-56 and described in Table 2-80. Mask 2 Use the DWT Mask Registers 2 to apply a mask to data addresses when matching against COMP2. Figure 2-56. MASK2 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R/W-X 9 8 7 6 5 4 3 2 1 0 MASK R/W-0h Table 2-80.
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Cortex-M3 Processor Registers www.ti.com 2.7.2.17 FUNCTION2 Register (Offset = 48h) [reset = X] FUNCTION2 is shown in Figure 2-57 and described in Table 2-81. Function 2 Use the DWT Function Registers 2 to control the operation of the comparator 2. This comparator can emit data or PC couples, trigger the ETM, or generate a watchpoint depending on the operation defined by FUNCTION. Figure 2-57.
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Cortex-M3 Processor Registers www.ti.com 2.7.2.18 COMP3 Register (Offset = 50h) [reset = 0h] COMP3 is shown in Figure 2-58 and described in Table 2-82. Comparator 3 This register is used to write the reference value for comparator 3. Figure 2-58. COMP3 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 COMP R/W-0h 9 8 7 6 5 4 3 2 1 0 Table 2-82.
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Cortex-M3 Processor Registers www.ti.com 2.7.2.19 MASK3 Register (Offset = 54h) [reset = X] MASK3 is shown in Figure 2-59 and described in Table 2-83. Mask 3 Use the DWT Mask Registers 3 to apply a mask to data addresses when matching against COMP3. Figure 2-59. MASK3 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R/W-X 9 8 7 6 5 4 3 2 1 0 MASK R/W-0h Table 2-83.
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Cortex-M3 Processor Registers www.ti.com 2.7.2.20 FUNCTION3 Register (Offset = 58h) [reset = X] FUNCTION3 is shown in Figure 2-60 and described in Table 2-84. Function 3 Use the DWT Function Registers 3 to control the operation of the comparator 3. This comparator can emit data or PC couples, trigger the ETM, or generate a watchpoint depending on the operation defined by FUNCTION. Figure 2-60.
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Cortex-M3 Processor Registers 116 www.ti.
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Cortex-M3 Processor Registers www.ti.com 2.7.3 CPU_FPB Registers Table 2-85 lists the memory-mapped registers for the CPU_FPB. All register offset addresses not listed in Table 2-85 should be considered as reserved locations and the register contents should not be modified. Table 2-85. CPU_FPB Registers Offset Acronym Register Name 0h CTRL Control Section 2.7.3.1 Section 4h REMAP Remap Section 2.7.3.2 8h COMP0 Comparator 0 Section 2.7.3.3 Ch COMP1 Comparator 1 Section 2.7.3.
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Cortex-M3 Processor Registers 2.7.3.1 www.ti.com CTRL Register (Offset = 0h) [reset = X] CTRL is shown in Figure 2-61 and described in Table 2-86. Control This register is used to enable the flash patch block. Figure 2-61. CTRL Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 1 KEY W-X 0 ENABLE R/W-X RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 RESERVED R-X 7 12 NUM_CODE2 R-X 6 5 NUM_LIT R-2h 4 NUM_CODE1 R-6h 3 2 RESERVED R-X Table 2-86.
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Cortex-M3 Processor Registers www.ti.com 2.7.3.2 REMAP Register (Offset = 4h) [reset = X] REMAP is shown in Figure 2-62 and described in Table 2-87. Remap This register provides the remap base address location where a matched addresses are remapped. The three most significant bits and the five least significant bits of the remap base address are hard-coded to 3'b001 and 5'b00000 respectively.
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Cortex-M3 Processor Registers 2.7.3.3 www.ti.com COMP0 Register (Offset = 8h) [reset = X] COMP0 is shown in Figure 2-63 and described in Table 2-88. Comparator 0 Figure 2-63. COMP0 Register 31 30 29 RESERVED R/W-X 28 22 21 20 REPLACE R/W-X 23 27 26 COMP R/W-X 25 24 19 18 17 16 11 10 9 8 3 2 1 RESERVED R/W-X 0 ENABLE R/W-X COMP R/W-X 15 14 13 12 COMP R/W-X 7 6 5 4 COMP R/W-X Table 2-88.
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Cortex-M3 Processor Registers www.ti.com 2.7.3.4 COMP1 Register (Offset = Ch) [reset = X] COMP1 is shown in Figure 2-64 and described in Table 2-89. Comparator 1 Figure 2-64. COMP1 Register 31 30 29 RESERVED R/W-X 28 22 21 20 REPLACE R/W-X 23 27 26 COMP R/W-X 25 24 19 18 17 16 11 10 9 8 3 2 1 RESERVED R/W-X 0 ENABLE R/W-X COMP R/W-X 15 14 13 12 COMP R/W-X 7 6 5 4 COMP R/W-X Table 2-89.
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Cortex-M3 Processor Registers 2.7.3.5 www.ti.com COMP2 Register (Offset = 10h) [reset = X] COMP2 is shown in Figure 2-65 and described in Table 2-90. Comparator 2 Figure 2-65. COMP2 Register 31 30 29 RESERVED R/W-X 28 22 21 20 REPLACE R/W-X 23 27 26 COMP R/W-X 25 24 19 18 17 16 11 10 9 8 3 2 1 RESERVED R/W-X 0 ENABLE R/W-X COMP R/W-X 15 14 13 12 COMP R/W-X 7 6 5 4 COMP R/W-X Table 2-90.
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Cortex-M3 Processor Registers www.ti.com 2.7.3.6 COMP3 Register (Offset = 14h) [reset = X] COMP3 is shown in Figure 2-66 and described in Table 2-91. Comparator 3 Figure 2-66. COMP3 Register 31 30 29 RESERVED R/W-X 28 22 21 20 REPLACE R/W-X 23 27 26 COMP R/W-X 25 24 19 18 17 16 11 10 9 8 3 2 1 RESERVED R/W-X 0 ENABLE R/W-X COMP R/W-X 15 14 13 12 COMP R/W-X 7 6 5 4 COMP R/W-X Table 2-91.
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Cortex-M3 Processor Registers 2.7.3.7 www.ti.com COMP4 Register (Offset = 18h) [reset = X] COMP4 is shown in Figure 2-67 and described in Table 2-92. Comparator 4 Figure 2-67. COMP4 Register 31 30 29 RESERVED R/W-X 28 22 21 20 REPLACE R/W-X 23 27 26 COMP R/W-X 25 24 19 18 17 16 11 10 9 8 3 2 1 RESERVED R/W-X 0 ENABLE R/W-X COMP R/W-X 15 14 13 12 COMP R/W-X 7 6 5 4 COMP R/W-X Table 2-92.
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Cortex-M3 Processor Registers www.ti.com 2.7.3.8 COMP5 Register (Offset = 1Ch) [reset = X] COMP5 is shown in Figure 2-68 and described in Table 2-93. Comparator 5 Figure 2-68. COMP5 Register 31 30 29 RESERVED R/W-X 28 22 21 20 REPLACE R/W-X 23 27 26 COMP R/W-X 25 24 19 18 17 16 11 10 9 8 3 2 1 RESERVED R/W-X 0 ENABLE R/W-X COMP R/W-X 15 14 13 12 COMP R/W-X 7 6 5 4 COMP R/W-X Table 2-93.
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Cortex-M3 Processor Registers 2.7.3.9 www.ti.com COMP6 Register (Offset = 20h) [reset = X] COMP6 is shown in Figure 2-69 and described in Table 2-94. Comparator 6 Figure 2-69. COMP6 Register 31 30 29 RESERVED R/W-X 28 22 21 20 REPLACE R/W-X 23 27 26 COMP R/W-X 25 24 19 18 17 16 11 10 9 8 3 2 1 RESERVED R/W-X 0 ENABLE R/W-X COMP R/W-X 15 14 13 12 COMP R/W-X 7 6 5 4 COMP R/W-X Table 2-94.
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Cortex-M3 Processor Registers www.ti.com 2.7.3.10 COMP7 Register (Offset = 24h) [reset = X] COMP7 is shown in Figure 2-70 and described in Table 2-95. Comparator 7 Figure 2-70. COMP7 Register 31 30 29 RESERVED R/W-X 28 22 21 20 REPLACE R/W-X 23 27 26 COMP R/W-X 25 24 19 18 17 16 11 10 9 8 3 2 1 RESERVED R/W-X 0 ENABLE R/W-X COMP R/W-X 15 14 13 12 COMP R/W-X 7 6 5 4 COMP R/W-X Table 2-95.
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Cortex-M3 Processor Registers 128 www.ti.
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Cortex-M3 Processor Registers www.ti.com 2.7.4 CPU_SCS Registers Table 2-96 lists the memory-mapped registers for the CPU_SCS. All register offset addresses not listed in Table 2-96 should be considered as reserved locations and the register contents should not be modified. Table 2-96. CPU_SCS Registers Offset Acronym Register Name 4h ICTR Interrupt Control Type Section 2.7.4.1 Section 8h ACTLR Auxiliary Control Section 2.7.4.2 10h STCSR SysTick Control and Status Section 2.7.4.
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Cortex-M3 Processor Registers www.ti.com Table 2-96. CPU_SCS Registers (continued) 130 Offset Acronym Register Name D4Ch ID_AFR0 Auxiliary Feature 0 Section 2.7.4.45 Section D50h ID_MMFR0 Memory Model Feature 0 Section 2.7.4.46 D54h ID_MMFR1 Memory Model Feature 1 Section 2.7.4.47 D58h ID_MMFR2 Memory Model Feature 2 Section 2.7.4.48 D5Ch ID_MMFR3 Memory Model Feature 3 Section 2.7.4.49 D60h ID_ISAR0 ISA Feature 0 Section 2.7.4.50 D64h ID_ISAR1 ISA Feature 1 Section 2.7.4.
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Cortex-M3 Processor Registers www.ti.com 2.7.4.1 ICTR Register (Offset = 4h) [reset = X] ICTR is shown in Figure 2-71 and described in Table 2-97. Interrupt Control Type Read this register to see the number of interrupt lines that the NVIC supports. Figure 2-71. ICTR Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 INTLINESNUM R-1h 0 RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 RESERVED R-X 4 Table 2-97.
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Cortex-M3 Processor Registers 2.7.4.2 www.ti.com ACTLR Register (Offset = 8h) [reset = X] ACTLR is shown in Figure 2-72 and described in Table 2-98. Auxiliary Control This register is used to disable certain aspects of functionality within the processor Figure 2-72.
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Cortex-M3 Processor Registers www.ti.com 2.7.4.3 STCSR Register (Offset = 10h) [reset = X] STCSR is shown in Figure 2-73 and described in Table 2-99. SysTick Control and Status This register enables the SysTick features and returns status flags related to SysTick. Figure 2-73.
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Cortex-M3 Processor Registers 2.7.4.4 www.ti.com STRVR Register (Offset = 14h) [reset = X] STRVR is shown in Figure 2-74 and described in Table 2-100. SysTick Reload Value This register is used to specify the start value to load into the current value register STCVR.CURRENT when the counter reaches 0. It can be any value between 1 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and STCSR.COUNTFLAG are activated when counting from 1 to 0. Figure 2-74.
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Cortex-M3 Processor Registers www.ti.com 2.7.4.5 STCVR Register (Offset = 18h) [reset = X] STCVR is shown in Figure 2-75 and described in Table 2-101. SysTick Current Value Read from this register returns the current value of SysTick counter. Writing to this register resets the SysTick counter (as well as STCSR.COUNTFLAG). Figure 2-75. STCVR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED CURRENT R/W-X R/W-0h 9 8 7 6 5 4 3 2 1 0 Table 2-101.
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Cortex-M3 Processor Registers 2.7.4.6 www.ti.com STCR Register (Offset = 1Ch) [reset = X] STCR is shown in Figure 2-76 and described in Table 2-102. SysTick Calibration Value Used to enable software to scale to any required speed using divide and multiply. Figure 2-76. STCR Register 31 NOREF R-1h 30 SKEW R-1h 29 23 22 21 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RESERVED R-X 20 TENMS R-75300h 15 14 13 12 TENMS R-75300h 7 6 5 4 TENMS R-75300h Table 2-102.
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Cortex-M3 Processor Registers www.ti.com 2.7.4.7 NVIC_ISER0 Register (Offset = 100h) [reset = X] NVIC_ISER0 is shown in Figure 2-77 and described in Table 2-103. Irq 0 to 31 Set Enable This register is used to enable interrupts and determine which interrupts are currently enabled. Figure 2-77.
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Cortex-M3 Processor Registers www.ti.com Table 2-103. NVIC_ISER0 Register Field Descriptions (continued) 138 Bit Field Type Reset Description 20 SETENA20 R/W X Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit returns its current enable state. 19 SETENA19 R/W X Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details).
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Cortex-M3 Processor Registers www.ti.com Table 2-103. NVIC_ISER0 Register Field Descriptions (continued) Bit Field Type Reset Description 2 SETENA2 R/W X Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit returns its current enable state. 1 SETENA1 R/W X Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details).
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Cortex-M3 Processor Registers 2.7.4.8 www.ti.com NVIC_ISER1 Register (Offset = 104h) [reset = X] NVIC_ISER1 is shown in Figure 2-78 and described in Table 2-104. Irq 32 to 63 Set Enable This register is used to enable interrupts and determine which interrupts are currently enabled. Figure 2-78.
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Cortex-M3 Processor Registers www.ti.com 2.7.4.9 NVIC_ICER0 Register (Offset = 180h) [reset = X] NVIC_ICER0 is shown in Figure 2-79 and described in Table 2-105. Irq 0 to 31 Clear Enable This register is used to disable interrupts and determine which interrupts are currently enabled. Figure 2-79.
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Cortex-M3 Processor Registers www.ti.com Table 2-105. NVIC_ICER0 Register Field Descriptions (continued) 142 Bit Field Type Reset Description 20 CLRENA20 R/W X Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit returns its current enable state. 19 CLRENA19 R/W X Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details).
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Cortex-M3 Processor Registers www.ti.com Table 2-105. NVIC_ICER0 Register Field Descriptions (continued) Bit Field Type Reset Description 2 CLRENA2 R/W X Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit returns its current enable state. 1 CLRENA1 R/W X Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details).
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Cortex-M3 Processor Registers www.ti.com 2.7.4.10 NVIC_ICER1 Register (Offset = 184h) [reset = X] NVIC_ICER1 is shown in Figure 2-80 and described in Table 2-106. Irq 32 to 63 Clear Enable This register is used to disable interrupts and determine which interrupts are currently enabled. Figure 2-80.
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Cortex-M3 Processor Registers www.ti.com 2.7.4.11 NVIC_ISPR0 Register (Offset = 200h) [reset = X] NVIC_ISPR0 is shown in Figure 2-81 and described in Table 2-107. Irq 0 to 31 Set Pending This register is used to force interrupts into the pending state and determine which interrupts are currently pending. Figure 2-81.
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Cortex-M3 Processor Registers www.ti.com Table 2-107. NVIC_ISPR0 Register Field Descriptions (continued) 146 Bit Field Type Reset Description 20 SETPEND20 R/W X Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit returns its current state. 19 SETPEND19 R/W X Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details).
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Cortex-M3 Processor Registers www.ti.com Table 2-107. NVIC_ISPR0 Register Field Descriptions (continued) Bit Field Type Reset Description 2 SETPEND2 R/W X Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit returns its current state. 1 SETPEND1 R/W X Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details).
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Cortex-M3 Processor Registers www.ti.com 2.7.4.12 NVIC_ISPR1 Register (Offset = 204h) [reset = X] NVIC_ISPR1 is shown in Figure 2-82 and described in Table 2-108. Irq 32 to 63 Set Pending This register is used to force interrupts into the pending state and determine which interrupts are currently pending. Figure 2-82.
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Cortex-M3 Processor Registers www.ti.com 2.7.4.13 NVIC_ICPR0 Register (Offset = 280h) [reset = X] NVIC_ICPR0 is shown in Figure 2-83 and described in Table 2-109. Irq 0 to 31 Clear Pending This register is used to clear pending interrupts and determine which interrupts are currently pending. Figure 2-83.
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Cortex-M3 Processor Registers www.ti.com Table 2-109. NVIC_ICPR0 Register Field Descriptions (continued) 150 Bit Field Type Reset Description 20 CLRPEND20 R/W X Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit returns its current state.
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Cortex-M3 Processor Registers www.ti.com Table 2-109. NVIC_ICPR0 Register Field Descriptions (continued) Bit Field Type Reset Description 2 CLRPEND2 R/W X Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit returns its current state. 1 CLRPEND1 R/W X Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 1 (See EVENT:CPUIRQSEL1.
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Cortex-M3 Processor Registers www.ti.com 2.7.4.14 NVIC_ICPR1 Register (Offset = 284h) [reset = X] NVIC_ICPR1 is shown in Figure 2-84 and described in Table 2-110. Irq 32 to 63 Clear Pending This register is used to clear pending interrupts and determine which interrupts are currently pending. Figure 2-84.
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Cortex-M3 Processor Registers www.ti.com 2.7.4.15 NVIC_IABR0 Register (Offset = 300h) [reset = X] NVIC_IABR0 is shown in Figure 2-85 and described in Table 2-111. Irq 0 to 31 Active Bit This register is used to determine which interrupts are active. Each flag in the register corresponds to one interrupt. Figure 2-85.
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Cortex-M3 Processor Registers www.ti.com Table 2-111. NVIC_IABR0 Register Field Descriptions (continued) 154 Bit Field Type Reset Description 20 ACTIVE20 R X Reading 0 from this bit implies that interrupt line 20 is not active. Reading 1 from this bit implies that the interrupt line 20 is active (See EVENT:CPUIRQSEL20.EV for details). 19 ACTIVE19 R X Reading 0 from this bit implies that interrupt line 19 is not active.
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Cortex-M3 Processor Registers www.ti.com Table 2-111. NVIC_IABR0 Register Field Descriptions (continued) Bit Field Type Reset Description 2 ACTIVE2 R X Reading 0 from this bit implies that interrupt line 2 is not active. Reading 1 from this bit implies that the interrupt line 2 is active (See EVENT:CPUIRQSEL2.EV for details). 1 ACTIVE1 R X Reading 0 from this bit implies that interrupt line 1 is not active.
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Cortex-M3 Processor Registers www.ti.com 2.7.4.16 NVIC_IABR1 Register (Offset = 304h) [reset = X] NVIC_IABR1 is shown in Figure 2-86 and described in Table 2-112. Irq 32 to 63 Active Bit This register is used to determine which interrupts are active. Each flag in the register corresponds to one interrupt. Figure 2-86.
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Cortex-M3 Processor Registers www.ti.com 2.7.4.17 NVIC_IPR0 Register (Offset = 400h) [reset = X] NVIC_IPR0 is shown in Figure 2-87 and described in Table 2-113. Irq 0 to 3 Priority This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the setting in AIRCR.PRIGROUP. Figure 2-87.
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Cortex-M3 Processor Registers www.ti.com 2.7.4.18 NVIC_IPR1 Register (Offset = 404h) [reset = X] NVIC_IPR1 is shown in Figure 2-88 and described in Table 2-114. Irq 4 to 7 Priority This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the setting in AIRCR.PRIGROUP. Figure 2-88.
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Cortex-M3 Processor Registers www.ti.com 2.7.4.19 NVIC_IPR2 Register (Offset = 408h) [reset = X] NVIC_IPR2 is shown in Figure 2-89 and described in Table 2-115. Irq 8 to 11 Priority This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the setting in AIRCR.PRIGROUP. Figure 2-89.
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Cortex-M3 Processor Registers www.ti.com 2.7.4.20 NVIC_IPR3 Register (Offset = 40Ch) [reset = X] NVIC_IPR3 is shown in Figure 2-90 and described in Table 2-116. Irq 12 to 15 Priority This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the setting in AIRCR.PRIGROUP. Figure 2-90.
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Cortex-M3 Processor Registers www.ti.com 2.7.4.21 NVIC_IPR4 Register (Offset = 410h) [reset = X] NVIC_IPR4 is shown in Figure 2-91 and described in Table 2-117. Irq 16 to 19 Priority This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the setting in AIRCR.PRIGROUP. Figure 2-91.
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Cortex-M3 Processor Registers www.ti.com 2.7.4.22 NVIC_IPR5 Register (Offset = 414h) [reset = X] NVIC_IPR5 is shown in Figure 2-92 and described in Table 2-118. Irq 20 to 23 Priority This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the setting in AIRCR.PRIGROUP. Figure 2-92.
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Cortex-M3 Processor Registers www.ti.com 2.7.4.23 NVIC_IPR6 Register (Offset = 418h) [reset = X] NVIC_IPR6 is shown in Figure 2-93 and described in Table 2-119. Irq 24 to 27 Priority This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the setting in AIRCR.PRIGROUP. Figure 2-93.
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Cortex-M3 Processor Registers www.ti.com 2.7.4.24 NVIC_IPR7 Register (Offset = 41Ch) [reset = X] NVIC_IPR7 is shown in Figure 2-94 and described in Table 2-120. Irq 28 to 31 Priority This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the setting in AIRCR.PRIGROUP. Figure 2-94.
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Cortex-M3 Processor Registers www.ti.com 2.7.4.25 NVIC_IPR8 Register (Offset = 420h) [reset = X] NVIC_IPR8 is shown in Figure 2-95 and described in Table 2-121. Irq 32 to 35 Priority This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the setting in AIRCR.PRIGROUP. Figure 2-95.
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Cortex-M3 Processor Registers www.ti.com 2.7.4.26 CPUID Register (Offset = D00h) [reset = 412FC231h] CPUID is shown in Figure 2-96 and described in Table 2-122. CPUID Base This register determines the ID number of the processor core, the version number of the processor core and the implementation details of the processor core. Figure 2-96.
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Cortex-M3 Processor Registers www.ti.com 2.7.4.27 ICSR Register (Offset = D04h) [reset = X] ICSR is shown in Figure 2-97 and described in Table 2-123. Interrupt Control State This register is used to set a pending Non-Maskable Interrupt (NMI), set or clear a pending SVC, set or clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority pended exception, and check the vector number of the active exception. Figure 2-97.
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Cortex-M3 Processor Registers www.ti.com 2.7.4.28 VTOR Register (Offset = D08h) [reset = X] VTOR is shown in Figure 2-98 and described in Table 2-124. Vector Table Offset This register is used to relocated the vector table base address. The vector table base offset determines the offset from the bottom of the memory map. The two most significant bits and the seven least significant bits of the vector table base offset must be 0. The portion of vector table base offset that is allowed to change is TBLOFF.
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Cortex-M3 Processor Registers www.ti.com 2.7.4.29 AIRCR Register (Offset = D0Ch) [reset = X] AIRCR is shown in Figure 2-99 and described in Table 2-125. Application Interrupt/Reset Control This register is used to determine data endianness, clear all active state information for debug or to recover from a hard failure, execute a system reset, alter the priority grouping position (binary point). Figure 2-99.
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Cortex-M3 Processor Registers www.ti.com 2.7.4.30 SCR Register (Offset = D10h) [reset = X] SCR is shown in Figure 2-100 and described in Table 2-126. System Control This register is used for power-management functions, i.e., signaling to the system when the processor can enter a low power state, controlling how the processor enters and exits low power states. Figure 2-100.
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Cortex-M3 Processor Registers www.ti.com 2.7.4.31 CCR Register (Offset = D14h) [reset = X] CCR is shown in Figure 2-101 and described in Table 2-127. Configuration Control This register is used to enable NMI, HardFault and FAULTMASK to ignore bus fault, trap divide by zero and unaligned accesses, enable user access to the Software Trigger Interrupt Register (STIR), control entry to Thread Mode. Figure 2-101.
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Cortex-M3 Processor Registers www.ti.com Table 2-127. CCR Register Field Descriptions (continued) Bit 0 172 Field Type Reset Description NONBASETHREDENA R/W X Indicates how the processor enters Thread mode: 0: Processor can enter Thread mode only when no exception is active. 1: Processor can enter Thread mode from any level using the appropriate return value (EXC_RETURN).
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Cortex-M3 Processor Registers www.ti.com 2.7.4.32 SHPR1 Register (Offset = D18h) [reset = X] SHPR1 is shown in Figure 2-102 and described in Table 2-128. System Handlers 4-7 Priority This register is used to prioritize the following system handlers: Memory manage, Bus fault, and Usage fault. System Handlers are a special class of exception handler that can have their priority set to any of the priority levels. Most can be masked on (enabled) or off (disabled).
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Cortex-M3 Processor Registers www.ti.com 2.7.4.33 SHPR2 Register (Offset = D1Ch) [reset = X] SHPR2 is shown in Figure 2-103 and described in Table 2-129. System Handlers 8-11 Priority This register is used to prioritize the SVC handler. System Handlers are a special class of exception handler that can have their priority set to any of the priority levels. Most can be masked on (enabled) or off (disabled). When disabled, the fault is always treated as a Hard Fault. Figure 2-103.
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Cortex-M3 Processor Registers www.ti.com 2.7.4.34 SHPR3 Register (Offset = D20h) [reset = X] SHPR3 is shown in Figure 2-104 and described in Table 2-130. System Handlers 12-15 Priority This register is used to prioritize the following system handlers: SysTick, PendSV and Debug Monitor. System Handlers are a special class of exception handler that can have their priority set to any of the priority levels. Most can be masked on (enabled) or off (disabled).
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Cortex-M3 Processor Registers www.ti.com 2.7.4.35 SHCSR Register (Offset = D24h) [reset = X] SHCSR is shown in Figure 2-105 and described in Table 2-131. System Handler Control and State This register is used to enable or disable the system handlers, determine the pending status of bus fault, mem manage fault, and SVC, determine the active status of the system handlers. If a fault condition occurs while its fault handler is disabled, the fault escalates to a Hard Fault. Figure 2-105.
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Cortex-M3 Processor Registers www.ti.com Table 2-131. SHCSR Register Field Descriptions (continued) Bit Field Type Reset Description 10 PENDSVACT R X PendSV active 0x0: Not active 0x1: Active 9 RESERVED R X Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
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Cortex-M3 Processor Registers www.ti.com 2.7.4.36 CFSR Register (Offset = D28h) [reset = X] CFSR is shown in Figure 2-106 and described in Table 2-132. Configurable Fault Status This register is used to obtain information about local faults. These registers include three subsections: The first byte is Memory Manage Fault Status Register (MMFSR). The second byte is Bus Fault Status Register (BFSR). The higher half-word is Usage Fault Status Register (UFSR).
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Cortex-M3 Processor Registers www.ti.com Table 2-132. CFSR Register Field Descriptions (continued) Bit Field Type Reset Description 15 BFARVALID R/W X This bit is set if the Bus Fault Address Register (BFAR) contains a valid address. This is true after a bus fault where the address is known. Other faults can clear this bit, such as a Mem Manage fault occurring later. If a Bus fault occurs that is escalated to a Hard Fault because of priority, the Hard Fault handler must clear this bit.
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Cortex-M3 Processor Registers www.ti.com 2.7.4.37 HFSR Register (Offset = D2Ch) [reset = X] HFSR is shown in Figure 2-107 and described in Table 2-133. Hard Fault Status This register is used to obtain information about events that activate the Hard Fault handler. This register is a write-clear register. This means that writing a 1 to a bit clears that bit. Figure 2-107.
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Cortex-M3 Processor Registers www.ti.com 2.7.4.38 DFSR Register (Offset = D30h) [reset = X] DFSR is shown in Figure 2-108 and described in Table 2-134. Debug Fault Status This register is used to monitor external debug requests, vector catches, data watchpoint match, BKPT instruction execution, halt requests. Multiple flags in the Debug Fault Status Register can be set when multiple fault conditions occur. The register is read/write clear. This means that it can be read normally.
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Cortex-M3 Processor Registers www.ti.com 2.7.4.39 MMFAR Register (Offset = D34h) [reset = 0h] MMFAR is shown in Figure 2-109 and described in Table 2-135. Mem Manage Fault Address This register is used to read the address of the location that caused a Memory Manage Fault. Figure 2-109. MMFAR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ADDRESS R/W-0h 9 8 7 6 5 4 3 2 1 0 Table 2-135.
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Cortex-M3 Processor Registers www.ti.com 2.7.4.40 BFAR Register (Offset = D38h) [reset = 0h] BFAR is shown in Figure 2-110 and described in Table 2-136. Bus Fault Address This register is used to read the address of the location that generated a Bus Fault. Figure 2-110. BFAR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ADDRESS R/W-0h 9 8 7 6 5 4 3 2 1 0 Table 2-136.
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Cortex-M3 Processor Registers www.ti.com 2.7.4.41 AFSR Register (Offset = D3Ch) [reset = X] AFSR is shown in Figure 2-111 and described in Table 2-137. Auxiliary Fault Status This register is used to determine additional system fault information to software. Single-cycle high level on an auxiliary faults is latched as one. The bit can only be cleared by writing a one to the corresponding bit. Auxiliary fault inputs to the CPU are tied to 0. Figure 2-111.
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Cortex-M3 Processor Registers www.ti.com 2.7.4.42 ID_PFR0 Register (Offset = D40h) [reset = X] ID_PFR0 is shown in Figure 2-112 and described in Table 2-138. Processor Feature 0 Figure 2-112. ID_PFR0 Register 31 30 29 28 27 26 25 15 14 13 12 11 RESERVED R-X 10 9 24 23 RESERVED R-X 8 7 22 21 20 19 18 17 16 6 5 STATE1 R-3h 4 3 2 1 STATE0 R-X 0 Table 2-138.
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Cortex-M3 Processor Registers www.ti.com 2.7.4.43 ID_PFR1 Register (Offset = D44h) [reset = X] ID_PFR1 is shown in Figure 2-113 and described in Table 2-139. Processor Feature 1 Figure 2-113. ID_PFR1 Register 31 30 29 28 27 26 25 24 19 18 17 16 RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 5 4 11 10 9 8 MICROCONTROLLER_PROGRAMMERS_MODEL R-2h RESERVED R-X 7 6 3 2 1 0 RESERVED R-X Table 2-139.
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Cortex-M3 Processor Registers www.ti.com 2.7.4.44 ID_DFR0 Register (Offset = D48h) [reset = X] ID_DFR0 is shown in Figure 2-114 and described in Table 2-140. Debug Feature 0 This register provides a high level view of the debug system. Further details are provided in the debug infrastructure itself. Figure 2-114.
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Cortex-M3 Processor Registers www.ti.com 2.7.4.45 ID_AFR0 Register (Offset = D4Ch) [reset = X] ID_AFR0 is shown in Figure 2-115 and described in Table 2-141. Auxiliary Feature 0 This register provides some freedom for implementation defined features to be registered. Not used in Cortex-M. Figure 2-115. ID_AFR0 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 1 0 Table 2-141.
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Cortex-M3 Processor Registers www.ti.com 2.7.4.46 ID_MMFR0 Register (Offset = D50h) [reset = 100030h] ID_MMFR0 is shown in Figure 2-116 and described in Table 2-142. Memory Model Feature 0 General information on the memory model and memory management support. Figure 2-116. ID_MMFR0 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-100030h 9 8 7 6 5 4 3 2 1 0 Table 2-142.
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Cortex-M3 Processor Registers www.ti.com 2.7.4.47 ID_MMFR1 Register (Offset = D54h) [reset = X] ID_MMFR1 is shown in Figure 2-117 and described in Table 2-143. Memory Model Feature 1 General information on the memory model and memory management support. Figure 2-117. ID_MMFR1 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 1 0 Table 2-143.
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Cortex-M3 Processor Registers www.ti.com 2.7.4.48 ID_MMFR2 Register (Offset = D58h) [reset = X] ID_MMFR2 is shown in Figure 2-118 and described in Table 2-144. Memory Model Feature 2 General information on the memory model and memory management support. Figure 2-118. ID_MMFR2 Register 31 30 29 28 RESERVED 27 26 25 24 WAIT_FOR_IN TERRUPT_ST ALLING R-1h 19 18 17 16 11 10 9 8 3 2 1 0 R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 4 RESERVED R-X Table 2-144.
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Cortex-M3 Processor Registers www.ti.com 2.7.4.49 ID_MMFR3 Register (Offset = D5Ch) [reset = X] ID_MMFR3 is shown in Figure 2-119 and described in Table 2-145. Memory Model Feature 3 General information on the memory model and memory management support. Figure 2-119. ID_MMFR3 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 1 0 Table 2-145.
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Cortex-M3 Processor Registers www.ti.com 2.7.4.50 ID_ISAR0 Register (Offset = D60h) [reset = 1101110h] ID_ISAR0 is shown in Figure 2-120 and described in Table 2-146. ISA Feature 0 Information on the instruction set attributes register Figure 2-120. ID_ISAR0 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-1101110h 9 8 7 6 5 4 3 2 1 0 Table 2-146.
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Cortex-M3 Processor Registers www.ti.com 2.7.4.51 ID_ISAR1 Register (Offset = D64h) [reset = 2111000h] ID_ISAR1 is shown in Figure 2-121 and described in Table 2-147. ISA Feature 1 Information on the instruction set attributes register Figure 2-121. ID_ISAR1 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-2111000h 9 8 7 6 5 4 3 2 1 0 Table 2-147.
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Cortex-M3 Processor Registers www.ti.com 2.7.4.52 ID_ISAR2 Register (Offset = D68h) [reset = 21112231h] ID_ISAR2 is shown in Figure 2-122 and described in Table 2-148. ISA Feature 2 Information on the instruction set attributes register Figure 2-122. ID_ISAR2 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-21112231h 9 8 7 6 5 4 3 2 1 0 Table 2-148.
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Cortex-M3 Processor Registers www.ti.com 2.7.4.53 ID_ISAR3 Register (Offset = D6Ch) [reset = 1111110h] ID_ISAR3 is shown in Figure 2-123 and described in Table 2-149. ISA Feature 3 Information on the instruction set attributes register Figure 2-123. ID_ISAR3 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-1111110h 9 8 7 6 5 4 3 2 1 0 Table 2-149.
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Cortex-M3 Processor Registers www.ti.com 2.7.4.54 ID_ISAR4 Register (Offset = D70h) [reset = 1310132h] ID_ISAR4 is shown in Figure 2-124 and described in Table 2-150. ISA Feature 4 Information on the instruction set attributes register Figure 2-124. ID_ISAR4 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-1310132h 9 8 7 6 5 4 3 2 1 0 Table 2-150.
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Cortex-M3 Processor Registers www.ti.com 2.7.4.55 CPACR Register (Offset = D88h) [reset = X] CPACR is shown in Figure 2-125 and described in Table 2-151. Coprocessor Access Control This register specifies the access privileges for coprocessors. Figure 2-125. CPACR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R/W-X 9 8 7 6 5 4 3 2 1 0 Table 2-151.
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Cortex-M3 Processor Registers www.ti.com 2.7.4.56 DHCSR Register (Offset = DF0h) [reset = X] DHCSR is shown in Figure 2-126 and described in Table 2-152. Debug Halting Control and Status The purpose of this register is to provide status information about the state of the processor, enable core debug, halt and step the processor. For writes, 0xA05F must be written to higher half-word of this register, otherwise the write operation is ignored and no bits are written into the register.
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Cortex-M3 Processor Registers www.ti.com Table 2-152. DHCSR Register Field Descriptions (continued) 200 Bit Field Type Reset Description 19 S_LOCKUP R/W X Reads as one if the core is running (not halted) and a lockup condition is present. When writing to this register, 1 must be written this bit-field, otherwise the write operation is ignored and no bits are written into the register. 18 S_SLEEP R/W X Indicates that the core is sleeping (WFI, WFE, or **SLEEP-ONEXIT**).
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Cortex-M3 Processor Registers www.ti.com 2.7.4.57 DCRSR Register (Offset = DF4h) [reset = 0h] DCRSR is shown in Figure 2-127 and described in Table 2-153. Deubg Core Register Selector The purpose of this register is to select the processor register to transfer data to or from. This write-only register generates a handshake to the core to transfer data to or from Debug Core Register Data Register and the selected register. Until this core transaction is complete, DHCSR.S_REGRDY is 0.
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Cortex-M3 Processor Registers www.ti.com 2.7.4.58 DCRDR Register (Offset = DF8h) [reset = 0h] DCRDR is shown in Figure 2-128 and described in Table 2-154. Debug Core Register Data Figure 2-128. DCRDR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DCRDR R/W-0h 9 8 7 6 5 4 3 2 1 0 Table 2-154.
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Cortex-M3 Processor Registers www.ti.com 2.7.4.59 DEMCR Register (Offset = DFCh) [reset = X] DEMCR is shown in Figure 2-129 and described in Table 2-155. Debug Exception and Monitor Control The purpose of this register is vector catching and debug monitor control. This register manages exception behavior under debug. Vector catching is only available to halting debug. The upper halfword is for monitor controls and the lower halfword is for halting exception support.
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Cortex-M3 Processor Registers www.ti.com Table 2-155. DEMCR Register Field Descriptions (continued) Bit Field Type Reset Description 16 MON_EN R/W X Enable the debug monitor. When enabled, the System handler priority register controls its priority level. If disabled, then all debug events go to Hard fault. DHCSR.C_DEBUGEN overrides this bit. Vector catching is semi-synchronous. When a matching event is seen, a Halt is requested.
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Cortex-M3 Processor Registers www.ti.com 2.7.4.60 STIR Register (Offset = F00h) [reset = X] STIR is shown in Figure 2-130 and described in Table 2-156. Software Trigger Interrupt Figure 2-130. STIR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED W-X 9 8 7 6 5 4 3 INTID W-0h 2 1 0 Table 2-156. STIR Register Field Descriptions Field Type Reset Description 31-9 Bit RESERVED W X Software should not rely on the value of a reserved. Write 0.
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Cortex-M3 Processor Registers 206 www.ti.
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Cortex-M3 Processor Registers www.ti.com 2.7.5 CPU_TPIU Registers Table 2-157 lists the memory-mapped registers for the CPU_TPIU. All register offset addresses not listed in Table 2-157 should be considered as reserved locations and the register contents should not be modified. Table 2-157. CPU_TPIU Registers Offset Acronym Register Name Section 0h SSPSR Supported Sync Port Sizes Section 2.7.5.1 4h CSPSR Current Sync Port Size Section 2.7.5.2 10h ACPR Async Clock Prescaler Section 2.7.5.
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Cortex-M3 Processor Registers 2.7.5.1 www.ti.com SSPSR Register (Offset = 0h) [reset = X] SSPSR is shown in Figure 2-131 and described in Table 2-158. Supported Sync Port Sizes This register represents a single port size that is supported on the device, that is, 4, 2 or 1. This is to ensure that tools do not attempt to select a port width that an attached TPA cannot capture. Figure 2-131.
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Cortex-M3 Processor Registers www.ti.com 2.7.5.2 CSPSR Register (Offset = 4h) [reset = X] CSPSR is shown in Figure 2-132 and described in Table 2-159. Current Sync Port Size This register has the same format as SSPSR but only one bit can be set, and all others must be zero. Writing values with more than one bit set, or setting a bit that is not indicated as supported can cause Unpredictable behavior. On reset this defaults to the smallest possible port size, 1 bit. Figure 2-132.
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Cortex-M3 Processor Registers 2.7.5.3 www.ti.com ACPR Register (Offset = 10h) [reset = X] ACPR is shown in Figure 2-133 and described in Table 2-160. Async Clock Prescaler This register scales the baud rate of the asynchronous output. Figure 2-133. ACPR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R/W-X 9 8 7 6 5 4 PRESCALER R/W-X 3 2 1 0 Table 2-160.
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Cortex-M3 Processor Registers www.ti.com 2.7.5.4 SPPR Register (Offset = F0h) [reset = X] SPPR is shown in Figure 2-134 and described in Table 2-161. Selected Pin Protocol This register selects the protocol to be used for trace output. Note: If this register is changed while trace data is being output, data corruption occurs. Figure 2-134.
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Cortex-M3 Processor Registers 2.7.5.5 www.ti.com FFSR Register (Offset = 300h) [reset = X] FFSR is shown in Figure 2-135 and described in Table 2-162. Formatter and Flush Status Figure 2-135. FFSR Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 FTNONSTOP R-1h 2 1 RESERVED R-X 0 RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 4 RESERVED R-X Table 2-162.
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Cortex-M3 Processor Registers www.ti.com 2.7.5.6 FFCR Register (Offset = 304h) [reset = X] FFCR is shown in Figure 2-136 and described in Table 2-163. Formatter and Flush Control When one of the two single wire output (SWO) modes is selected, ENFCONT enables the formatter to be bypassed. If the formatter is bypassed, only the ITM/DWT trace source (ATDATA2) passes through. The TPIU accepts and discards data that is presented on the ETM port (ATDATA1).
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Cortex-M3 Processor Registers 2.7.5.7 www.ti.com FSCR Register (Offset = 308h) [reset = X] FSCR is shown in Figure 2-137 and described in Table 2-164. Formatter Synchronization Counter Figure 2-137. FSCR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 FSCR R-X 9 8 7 6 5 4 3 2 1 0 Table 2-164.
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Cortex-M3 Processor Registers www.ti.com 2.7.5.8 CLAIMMASK Register (Offset = FA0h) [reset = Fh] CLAIMMASK is shown in Figure 2-138 and described in Table 2-165. Claim Tag Mask Figure 2-138. CLAIMMASK Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 CLAIMMASK R-Fh 9 8 7 6 5 4 3 2 1 0 Table 2-165. CLAIMMASK Register Field Descriptions Bit 31-0 Field Type Reset Description CLAIMMASK R Fh This register forms one half of the Claim Tag value.
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Cortex-M3 Processor Registers 2.7.5.9 www.ti.com CLAIMSET Register (Offset = FA0h) [reset = Fh] CLAIMSET is shown in Figure 2-139 and described in Table 2-166. Claim Tag Set Figure 2-139. CLAIMSET Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 CLAIMSET W-Fh 9 8 7 6 5 4 3 2 1 0 Table 2-166. CLAIMSET Register Field Descriptions Bit 31-0 216 Field Type Reset Description CLAIMSET W Fh This register forms one half of the Claim Tag value.
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Cortex-M3 Processor Registers www.ti.com 2.7.5.10 CLAIMTAG Register (Offset = FA4h) [reset = X] CLAIMTAG is shown in Figure 2-140 and described in Table 2-167. Current Claim Tag Figure 2-140. CLAIMTAG Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 CLAIMTAG R-X 9 8 7 6 5 4 3 2 1 0 Table 2-167. CLAIMTAG Register Field Descriptions Bit 31-0 Field Type Reset Description CLAIMTAG R X This register forms one half of the Claim Tag value.
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Cortex-M3 Processor Registers www.ti.com 2.7.5.11 CLAIMCLR Register (Offset = FA4h) [reset = X] CLAIMCLR is shown in Figure 2-141 and described in Table 2-168. Claim Tag Clear Figure 2-141. CLAIMCLR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 CLAIMCLR W-X 9 8 7 6 5 4 3 2 1 0 Table 2-168. CLAIMCLR Register Field Descriptions Bit 31-0 218 Field Type Reset Description CLAIMCLR W X This register forms one half of the Claim Tag value.
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Cortex-M3 Processor Registers www.ti.com 2.7.5.12 DEVID Register (Offset = FC8h) [reset = CA0h] DEVID is shown in Figure 2-142 and described in Table 2-169. Device ID Figure 2-142. DEVID Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DEVID R-CA0h 9 8 7 6 5 4 3 2 1 0 Table 2-169. DEVID Register Field Descriptions Bit 31-0 Field Type Reset Description DEVID R CA0h This field returns: 0xCA1 if there is an ETM present. 0xCA0 if there is no ETM present.
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Chapter 3 SWCU117A – February 2015 – Revised March 2015 Cortex™-M3 Peripherals This chapter describes the Cortex™-M3 peripherals. Topic 3.1 3.2 220 ........................................................................................................................... Page Cortex™-M3 Peripherals Introduction ................................................................. 221 Functional Description ......................................................................................
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Cortex™-M3 Peripherals Introduction www.ti.com 3.1 Cortex™-M3 Peripherals Introduction This chapter provides information on the CC26xx implementation of the Cortex-M3 processor peripherals, including: • System timer (SysTick) (see SysTick): Provides a simple, 24-bit clear-on-write, decrementing, wrap-onzero counter with a flexible control mechanism.
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Functional Description • • www.ti.com the dynamic range of the counter A simple counter used to measure time to completion and time used An internal clock source control based on missing and/or meeting durations. The COUNTFLAG bit in the STCSR control and status register can be used to determine if an action completed within a set duration, as part of a dynamic clock management control loop.
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Functional Description www.ti.com 3.2.2.2 Hardware and Software Control of Interrupts The Cortex-M3 processor latches all interrupts. A peripheral interrupt becomes pending for one of the following reasons: • The NVIC detects that the interrupt signal is asserted and the interrupt is not active. • The NVIC detects a rising edge on the interrupt signal.
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Functional Description • • www.ti.com Two literal comparators for matching against literal loads from Code space, and remapping to a corresponding area in System space Six instruction comparators for matching against instruction fetches from Code space, and remapping to a corresponding area in System space.
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Functional Description www.ti.com Table 3-1.
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Functional Description www.ti.com Table 3-1.
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Chapter 4 SWCU117A – February 2015 – Revised March 2015 Interrupts and Events This chapter describes CC26xx interrupts and events. Topic ........................................................................................................................... 4.1 4.2 4.3 4.4 4.5 4.6 Exception Model ............................................................................................... Fault Handling ................................................................................................
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Exception Model 4.1 www.ti.com Exception Model The ARM® Cortex®-M3 processor and the nested vectored interrupt controller (NVIC) prioritize and handle all exceptions in handler mode. The state of the processor is automatically stored to the stack on an exception and automatically restored from the stack at the end of the interrupt service routine (ISR). The vector is fetched in parallel to state saving, thus enabling efficient interrupt entry.
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Exception Model www.ti.com • • • • • • • Bus Fault: A bus fault is an exception that occurs because of a memory-related fault for an instruction or data memory transaction such as a prefetch fault or a memory access fault. This fault can be enabled or disabled.
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Exception Model www.ti.com Table 4-2. Exception Types (continued) Vector Address or Offset (2) Vector Number Priority (1) PendSV 14 Programmable 0x0000 0038 Asynchronous SysTick 15 Programmable 0x0000 003C Asynchronous 16 and above Programmable (4) Exception Type Interrupts (4) Activation 0x0000 0040 and above Asynchronous See PRIn registers. Table 4-3.
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Exception Model www.ti.com 4.1.3 Exception Handlers The processor handles exceptions using: • Interrupt Service Routines (ISRs): Interrupts (IRQx) are the exceptions handled by ISRs. • Fault Handlers: Hard fault, usage fault, and bus fault are fault exceptions handled by the fault handlers. • System Handlers: PendSV, SVCall, SysTick, and the fault exceptions are all system exceptions that are handled by system handlers. 4.1.
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Exception Model www.ti.com 4.1.5 Exception Priorities As Table 4-2 shows, all exceptions have an associated priority, with a lower priority value indicating a higher priority and configurable priorities for all exceptions except reset, and hard fault. If software does not configure any priorities, then all exceptions with a configurable priority have a priority of 0.
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Exception Model www.ti.com 4.1.7 Exception Entry and Return Descriptions of exception handling use the following terms: • Preemption: When the processor is executing an exception handler, an exception can preempt the exception handler if its priority is higher than the priority of the exception being handled. For more information about preemption by an interrupt, see Section 4.1.6, Interrupt Priority Grouping. When one exception preempts another, the exceptions are called nested exceptions.
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Exception Model 4.1.7.1 www.ti.com Exception Entry Exception entry occurs when there is a pending exception with sufficient priority and either the processor is in thread mode or the new exception is of a higher priority than the exception being handled, in which case the new exception preempts the original exception. When one exception preempts another, the exceptions are nested.
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Fault Handling www.ti.com Table 4-4. Exception Return Behavior EXC_RETURN[31:0] 4.2 Description 0xFFFF FFF0 Reserved 0xFFFF FFF1 Return to handler mode Exception return uses state from MSP. Execution uses MSP after return. 0xFFFF FFF2 to 0xFFFF FFF8 Reserved 0xFFFF FFF9 Return to thread mode Exception return uses state from MSP. Execution uses MSP after return. 0xFFFF FFFA to 0xFFFF FFFC Reserved 0xFFFF FFFD Return to thread mode Exception return uses state from PSP.
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Fault Handling www.ti.com 4.2.2 Fault Escalation and Hard Faults All fault exceptions except for hard fault have configurable exception priority. Software can disable execution of the handlers for these faults. Usually, the exception priority, together with the values of the exception mask registers, determines whether the processor enters the fault handler, and whether a fault handler can preempt another fault handler as described in Section 4.1, Exception Model.
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Event Fabric www.ti.com 4.3 Event Fabric 4.3.1 Introduction The event fabric is a combinational router between event sources and event subscribers. The event inputs are routed to a central event-bus where a subscriber can select the appropriate events and output those as inputs to peripherals. Figure 4-3 shows the general concept of the event fabric. The event fabric is strictly combinational logic.
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Event Fabric www.ti.com 4.3.2 Event Fabric Overview There are two main event fabric blocks in the CC26xx family. One in the MCU power domain (MCU event fabric) and the other in the AON power domain (AON event fabric). Figure 4-4 shows a simplified overview of the two modules together. The MCU event fabric is one of the subscribers to the AON event fabric. Figure 4-4.
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AON Event Fabric www.ti.com 4.4.1 Common Input Event List Table 4-7 lists the input events for the AON event fabric. The sources for these events are considered level-triggered active high. Table 4-7. AON Event Fabric Input Events Event No.
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MCU Event Fabric www.ti.com Figure 4-5. WUC Subscriber in AON Event Fabric WUC JTAG AUX MCU Event bus Event Producers (Peripherals) 4.4.2.2 Real-Time Clock The RTC has a programmable event, which can be configured in the [CTRL_EVENT_RTC] register, and a fixed event with ID 46 (Channel 2 clear – from AUX). 4.4.2.3 MCU Event Fabric Seven output event from the AON event fabric are routed as input to the MCU event fabric. These events are: 1. AON programmable 0 2. AON programmable 1 3.
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MCU Event Fabric www.ti.com 4.5.1 Common Input Event List Table 4-8 lists the input events for the MCU event fabric. The sources for these events are considered level-triggered active-high. Table 4-8. MCU Event Fabric Input Events Event No. Event Enum. Description 0x0 NONE Always inactive 0x1 AON_PROG0 Event selected by AON_EVENT MCU event selector, [AON_EVENT:EVTOMCUSEL.AON_PROG0_EV] 0x2 AON_PROG1 Event selected by AON_EVENT MCU event selector, [AON_EVENT:EVTOMCUSEL.
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MCU Event Fabric www.ti.com Table 4-8. MCU Event Fabric Input Events (continued) Event No. Event Enum. Description MCU domain wake-up control [AON_EVENT:MCUWUSEL.*] AUX domain wake-up control [AON_EVENT:AUXWUSEL.*] Combined interrupt for CPE-generated events. Corresponding flags are here [RFC_DBELL:RFCPEIFG.*]. Only interrupts selected with CPE1 in [RFC_DBELL:RFCPEIFG.*] can trigger a RFC_CPE_1 event.
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MCU Event Fabric www.ti.com Table 4-8. MCU Event Fabric Input Events (continued) Event No. Event Enum. Description 0x43 GPT3A_CMP GPT3A compare event. Configured by [GPT3:TAMR.TCACT]. 0x44 GPT3B_CMP GPT3B compare event. Configured by [GPT3:TBMR.TCACT].
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MCU Event Fabric www.ti.com Table 4-8. MCU Event Fabric Input Events (continued) Event No. Event Enum. Description 0x68 TRNG_IRQ TRNG Interrupt event, controlled by [TRNG:IRQEN.EN] 0x69 AUX_AON_WU_EV AON wake-up event, corresponds flags are here [AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV]. 0x6A AUX_COMPA AUX COMP A event, corresponds to [AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA]. 0x6B AUX_COMPB AUX COMP B event, corresponds to [AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB].
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Interrupts and Events Registers www.ti.com 4.5.2.1 System CPU Table 4-3 shows that the interrupts with vector number from 16 to 49 are sourced by the events routed in the MCU event fabric to the system CPU. The event fabric routes all level interrupt events to the system CPU. The event/interrupt called "AON programmable 0" can be configured in the AON event fabric.
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Interrupts and Events Registers www.ti.com 4.6.1 AON_EVENT Registers Table 4-10 lists the memory-mapped registers for the AON_EVENT. All register offset addresses not listed in Table 4-10 should be considered as reserved locations and the register contents should not be modified. Table 4-10. AON_EVENT Registers Offset 246 Acronym Register Name 0h MCUWUSEL Wake-up Selector For MCU Section 4.6.1.1 4h AUXWUSEL Wake-up Selector For AUX Section 4.6.1.
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Interrupts and Events Registers www.ti.com 4.6.1.1 MCUWUSEL Register (Offset = 0h) [reset = X] MCUWUSEL is shown in Figure 4-6 and described in Table 4-11. Wake-up Selector For MCU This register contains pointers to 4 events which are routed to AON_WUC as wakeup sources for MCU. AON_WUC will start a wakeup sequence for the MCU domain when either of the 4 selected events are asserted.
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Interrupts and Events Registers www.ti.com Table 4-11. MCUWUSEL Register Field Descriptions (continued) Bit 29-24 248 Field Type Reset Description WU3_EV R/W 3Fh MCU Wakeup Source #3 AON Event Source selecting 1 of 4 events routed to AON_WUC for waking up the MCU domain from Power Off or Power Down.
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Interrupts and Events Registers www.ti.com Table 4-11. MCUWUSEL Register Field Descriptions (continued) Bit Field Type Reset Description 32h = TDC completed or timed out 33h = Timer 0 event 34h = Timer 1 event 35h = BATMON temperature update event 36h = BATMON voltage update event 37h = Comparator B triggered. Asynchronous signal directly from the AUX Comparator B as opposed to AUX_COMPB which is synchronized in AUX 38h = Comparator B not triggered.
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Interrupts and Events Registers www.ti.com Table 4-11. MCUWUSEL Register Field Descriptions (continued) Bit Field Type Reset Description 28h = RTC channel 2 - delayed event 29h = RTC combined delayed event 2Ah = RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) 2Bh = JTAG generated event 2Ch = AUX Software triggered event #0. Triggered by AUX_EVCTL:SWEVSET.SWEV0 2Dh = AUX Software triggered event #1. Triggered by AUX_EVCTL:SWEVSET.
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Interrupts and Events Registers www.ti.com Table 4-11. MCUWUSEL Register Field Descriptions (continued) Bit 13-8 Field Type Reset Description WU1_EV R/W 3Fh MCU Wakeup Source #1 AON Event Source selecting 1 of 4 events routed to AON_WUC for waking up the MCU domain from Power Off or Power Down.
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Interrupts and Events Registers www.ti.com Table 4-11. MCUWUSEL Register Field Descriptions (continued) Bit Field Type Reset Description 32h = TDC completed or timed out 33h = Timer 0 event 34h = Timer 1 event 35h = BATMON temperature update event 36h = BATMON voltage update event 37h = Comparator B triggered. Asynchronous signal directly from the AUX Comparator B as opposed to AUX_COMPB which is synchronized in AUX 38h = Comparator B not triggered.
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Interrupts and Events Registers www.ti.com Table 4-11. MCUWUSEL Register Field Descriptions (continued) Bit Field Type Reset Description 28h = RTC channel 2 - delayed event 29h = RTC combined delayed event 2Ah = RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) 2Bh = JTAG generated event 2Ch = AUX Software triggered event #0. Triggered by AUX_EVCTL:SWEVSET.SWEV0 2Dh = AUX Software triggered event #1. Triggered by AUX_EVCTL:SWEVSET.
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Interrupts and Events Registers 4.6.1.2 www.ti.com AUXWUSEL Register (Offset = 4h) [reset = X] AUXWUSEL is shown in Figure 4-7 and described in Table 4-12. Wake-up Selector For AUX This register contains pointers to 3 events which are routed to AON_WUC as wakeup sources for AUX. AON_WUC will start a wakeup sequence for the AUX domain when either of the 3 selected events are asserted.
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Interrupts and Events Registers www.ti.com Table 4-12. AUXWUSEL Register Field Descriptions (continued) Bit 21-16 Field Type Reset Description WU2_EV R/W 3Fh AUX Wakeup Source #2 AON Event Source selecting 1 of 3 events routed to AON_WUC for waking up the AUX domain from Power Off or Power Down.
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Interrupts and Events Registers www.ti.com Table 4-12. AUXWUSEL Register Field Descriptions (continued) Bit Field Type Reset Description 32h = TDC completed or timed out 33h = Timer 0 event 34h = Timer 1 event 35h = BATMON temperature update event 36h = BATMON voltage update event 37h = Comparator B triggered. Asynchronous signal directly from the AUX Comparator B as opposed to AUX_COMPB which is synchronized in AUX 38h = Comparator B not triggered.
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Interrupts and Events Registers www.ti.com Table 4-12. AUXWUSEL Register Field Descriptions (continued) Bit Field Type Reset Description 28h = RTC channel 2 - delayed event 29h = RTC combined delayed event 2Ah = RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) 2Bh = JTAG generated event 2Ch = AUX Software triggered event #0. Triggered by AUX_EVCTL:SWEVSET.SWEV0 2Dh = AUX Software triggered event #1. Triggered by AUX_EVCTL:SWEVSET.
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Interrupts and Events Registers www.ti.com Table 4-12. AUXWUSEL Register Field Descriptions (continued) 258 Bit Field Type Reset Description 5-0 WU0_EV R/W 3Fh AUX Wakeup Source #0 AON Event Source selecting 1 of 3 events routed to AON_WUC for waking up the AUX domain from Power Off or Power Down.
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Interrupts and Events Registers www.ti.com Table 4-12. AUXWUSEL Register Field Descriptions (continued) Bit Field Type Reset Description 32h = TDC completed or timed out 33h = Timer 0 event 34h = Timer 1 event 35h = BATMON temperature update event 36h = BATMON voltage update event 37h = Comparator B triggered. Asynchronous signal directly from the AUX Comparator B as opposed to AUX_COMPB which is synchronized in AUX 38h = Comparator B not triggered.
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Interrupts and Events Registers 4.6.1.3 www.ti.com EVTOMCUSEL Register (Offset = 8h) [reset = X] EVTOMCUSEL is shown in Figure 4-8 and described in Table 4-13. Event Selector For MCU Event Fabric This register contains pointers for 3 AON events that are routed to the MCU Event Fabric EVENT Figure 4-8.
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Interrupts and Events Registers www.ti.com Table 4-13. EVTOMCUSEL Register Field Descriptions (continued) Bit 21-16 Field Type Reset Description AON_PROG2_EV R/W 2Bh Event selector for AON_PROG2 event. AON Event Source id# selecting event routed to EVENT as AON_PROG2 event.
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Interrupts and Events Registers www.ti.com Table 4-13. EVTOMCUSEL Register Field Descriptions (continued) Bit Field Type Reset Description 33h = Timer 0 event 34h = Timer 1 event 35h = BATMON temperature update event 36h = BATMON voltage update event 37h = Comparator B triggered. Asynchronous signal directly from the AUX Comparator B as opposed to AUX_COMPB which is synchronized in AUX 38h = Comparator B not triggered.
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Interrupts and Events Registers www.ti.com Table 4-13. EVTOMCUSEL Register Field Descriptions (continued) Bit Field Type Reset Description 29h = RTC combined delayed event 2Ah = RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) 2Bh = JTAG generated event 2Ch = AUX Software triggered event #0. Triggered by AUX_EVCTL:SWEVSET.SWEV0 2Dh = AUX Software triggered event #1. Triggered by AUX_EVCTL:SWEVSET.SWEV1 2Eh = AUX Software triggered event #2.
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Interrupts and Events Registers www.ti.com Table 4-13. EVTOMCUSEL Register Field Descriptions (continued) 264 Bit Field Type Reset Description 5-0 AON_PROG0_EV R/W 2Bh Event selector for AON_PROG0 event. AON Event Source id# selecting event routed to EVENT as AON_PROG0 event.
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Interrupts and Events Registers www.ti.com Table 4-13. EVTOMCUSEL Register Field Descriptions (continued) Bit Field Type Reset Description 33h = Timer 0 event 34h = Timer 1 event 35h = BATMON temperature update event 36h = BATMON voltage update event 37h = Comparator B triggered. Asynchronous signal directly from the AUX Comparator B as opposed to AUX_COMPB which is synchronized in AUX 38h = Comparator B not triggered.
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Interrupts and Events Registers 4.6.1.4 www.ti.com RTCSEL Register (Offset = Ch) [reset = X] RTCSEL is shown in Figure 4-9 and described in Table 4-14. RTC Capture Event Selector For AON_RTC This register contains a pointer to select an AON event for RTC capture. Please refer to AON_RTC:CH1CAPT Figure 4-9. RTCSEL Register 31 30 29 28 27 26 25 15 14 13 12 11 10 RESERVED R-X 9 24 23 RESERVED R-X 8 7 22 21 20 6 5 4 19 18 17 16 3 2 1 RTC_CH1_CAPT_EV R/W-3Fh 0 Table 4-14.
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Interrupts and Events Registers www.ti.com Table 4-14. RTCSEL Register Field Descriptions (continued) Bit Field Type Reset Description 5-0 RTC_CH1_CAPT_EV R/W 3Fh AON Event Source id# for RTCSEL event which is fed to AON_RTC.
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Interrupts and Events Registers www.ti.com Table 4-14. RTCSEL Register Field Descriptions (continued) Bit Field Type Reset Description 33h = AUX Timer 0 event 34h = AUX Timer 1 event 35h = BATMON temperature update event 36h = BATMON voltage update event 37h = Comparator B triggered. Asynchronous signal directly from the AUX Comparator B as opposed to AUX_COMPB which is synchronized in AUX 38h = Comparator B not triggered.
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Interrupts and Events Registers www.ti.
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Interrupts and Events Registers www.ti.com 4.6.2 EVENT Registers Table 4-15 lists the memory-mapped registers for the EVENT. All register offset addresses not listed in Table 4-15 should be considered as reserved locations and the register contents should not be modified. Table 4-15. EVENT Registers Offset Acronym Register Name 0h CPUIRQSEL0 Output Selection for CPU Interrupt 0 Section 4.6.2.1 Section 4h CPUIRQSEL1 Output Selection for CPU Interrupt 1 Section 4.6.2.
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Interrupts and Events Registers www.ti.com Table 4-15. EVENT Registers (continued) Offset Acronym Register Name 200h GPT0ACAPTSEL Output Selection for GPT0 0 Section 4.6.2.45 Section 204h GPT0BCAPTSEL Output Selection for GPT0 1 Section 4.6.2.46 300h GPT1ACAPTSEL Output Selection for GPT1 0 Section 4.6.2.47 304h GPT1BCAPTSEL Output Selection for GPT1 1 Section 4.6.2.48 400h GPT2ACAPTSEL Output Selection for GPT2 0 Section 4.6.2.
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Interrupts and Events Registers www.ti.com Table 4-15. EVENT Registers (continued) 272 Offset Acronym Register Name 700h AUXSEL0 Output Selection for AUX Subscriber 0 Section 4.6.2.92 800h CM3NMISEL0 Output Selection for NMI Subscriber 0 Section 4.6.2.93 900h I2SSTMPSEL0 Output Selection for I2S Subscriber 0 Section 4.6.2.94 A00h FRZSEL0 Output Selection for FRZ Subscriber 0 Section 4.6.2.95 F00h SWEV Set or Clear Software Events Section 4.6.2.
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Interrupts and Events Registers www.ti.com 4.6.2.1 CPUIRQSEL0 Register (Offset = 0h) [reset = X] CPUIRQSEL0 is shown in Figure 4-10 and described in Table 4-16. Output Selection for CPU Interrupt 0 Figure 4-10. CPUIRQSEL0 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-4h 1 0 Table 4-16.
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Interrupts and Events Registers 4.6.2.2 www.ti.com CPUIRQSEL1 Register (Offset = 4h) [reset = X] CPUIRQSEL1 is shown in Figure 4-11 and described in Table 4-17. Output Selection for CPU Interrupt 1 Figure 4-11. CPUIRQSEL1 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-9h 1 0 Table 4-17.
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Interrupts and Events Registers www.ti.com 4.6.2.3 CPUIRQSEL2 Register (Offset = 8h) [reset = X] CPUIRQSEL2 is shown in Figure 4-12 and described in Table 4-18. Output Selection for CPU Interrupt 2 Figure 4-12. CPUIRQSEL2 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-1Eh 1 0 Table 4-18.
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Interrupts and Events Registers 4.6.2.4 www.ti.com CPUIRQSEL3 Register (Offset = Ch) [reset = X] CPUIRQSEL3 is shown in Figure 4-13 and described in Table 4-19. Output Selection for CPU Interrupt 3 Figure 4-13. CPUIRQSEL3 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-38h 1 0 Table 4-19.
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Interrupts and Events Registers www.ti.com 4.6.2.5 CPUIRQSEL4 Register (Offset = 10h) [reset = X] CPUIRQSEL4 is shown in Figure 4-14 and described in Table 4-20. Output Selection for CPU Interrupt 4 Figure 4-14. CPUIRQSEL4 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-7h 1 0 Table 4-20.
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Interrupts and Events Registers 4.6.2.6 www.ti.com CPUIRQSEL5 Register (Offset = 14h) [reset = X] CPUIRQSEL5 is shown in Figure 4-15 and described in Table 4-21. Output Selection for CPU Interrupt 5 Figure 4-15. CPUIRQSEL5 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-24h 1 0 Table 4-21.
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Interrupts and Events Registers www.ti.com 4.6.2.7 CPUIRQSEL6 Register (Offset = 18h) [reset = X] CPUIRQSEL6 is shown in Figure 4-16 and described in Table 4-22. Output Selection for CPU Interrupt 6 Figure 4-16. CPUIRQSEL6 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-1Ch 1 0 Table 4-22.
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Interrupts and Events Registers 4.6.2.8 www.ti.com CPUIRQSEL7 Register (Offset = 1Ch) [reset = X] CPUIRQSEL7 is shown in Figure 4-17 and described in Table 4-23. Output Selection for CPU Interrupt 7 Figure 4-17. CPUIRQSEL7 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-22h 1 0 Table 4-23.
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Interrupts and Events Registers www.ti.com 4.6.2.9 CPUIRQSEL8 Register (Offset = 20h) [reset = X] CPUIRQSEL8 is shown in Figure 4-18 and described in Table 4-24. Output Selection for CPU Interrupt 8 Figure 4-18. CPUIRQSEL8 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-23h 1 0 Table 4-24.
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Interrupts and Events Registers www.ti.com 4.6.2.10 CPUIRQSEL9 Register (Offset = 24h) [reset = X] CPUIRQSEL9 is shown in Figure 4-19 and described in Table 4-25. Output Selection for CPU Interrupt 9 Figure 4-19. CPUIRQSEL9 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-1Bh 1 0 Table 4-25.
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Interrupts and Events Registers www.ti.com 4.6.2.11 CPUIRQSEL10 Register (Offset = 28h) [reset = X] CPUIRQSEL10 is shown in Figure 4-20 and described in Table 4-26. Output Selection for CPU Interrupt 10 Figure 4-20. CPUIRQSEL10 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-1Ah 1 0 Table 4-26.
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Interrupts and Events Registers www.ti.com 4.6.2.12 CPUIRQSEL11 Register (Offset = 2Ch) [reset = X] CPUIRQSEL11 is shown in Figure 4-21 and described in Table 4-27. Output Selection for CPU Interrupt 11 Figure 4-21. CPUIRQSEL11 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-19h 1 0 Table 4-27.
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Interrupts and Events Registers www.ti.com 4.6.2.13 CPUIRQSEL12 Register (Offset = 30h) [reset = X] CPUIRQSEL12 is shown in Figure 4-22 and described in Table 4-28. Output Selection for CPU Interrupt 12 Figure 4-22. CPUIRQSEL12 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-8h 1 0 Table 4-28.
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Interrupts and Events Registers www.ti.com 4.6.2.14 CPUIRQSEL13 Register (Offset = 34h) [reset = X] CPUIRQSEL13 is shown in Figure 4-23 and described in Table 4-29. Output Selection for CPU Interrupt 13 Figure 4-23. CPUIRQSEL13 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-1Dh 1 0 Table 4-29.
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Interrupts and Events Registers www.ti.com 4.6.2.15 CPUIRQSEL14 Register (Offset = 38h) [reset = X] CPUIRQSEL14 is shown in Figure 4-24 and described in Table 4-30. Output Selection for CPU Interrupt 14 Figure 4-24. CPUIRQSEL14 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-18h 1 0 Table 4-30.
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Interrupts and Events Registers www.ti.com 4.6.2.16 CPUIRQSEL15 Register (Offset = 3Ch) [reset = X] CPUIRQSEL15 is shown in Figure 4-25 and described in Table 4-31. Output Selection for CPU Interrupt 15 Figure 4-25. CPUIRQSEL15 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-10h 1 0 Table 4-31.
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Interrupts and Events Registers www.ti.com 4.6.2.17 CPUIRQSEL16 Register (Offset = 40h) [reset = X] CPUIRQSEL16 is shown in Figure 4-26 and described in Table 4-32. Output Selection for CPU Interrupt 16 Figure 4-26. CPUIRQSEL16 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-11h 1 0 Table 4-32.
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Interrupts and Events Registers www.ti.com 4.6.2.18 CPUIRQSEL17 Register (Offset = 44h) [reset = X] CPUIRQSEL17 is shown in Figure 4-27 and described in Table 4-33. Output Selection for CPU Interrupt 17 Figure 4-27. CPUIRQSEL17 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-12h 1 0 Table 4-33.
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Interrupts and Events Registers www.ti.com 4.6.2.19 CPUIRQSEL18 Register (Offset = 48h) [reset = X] CPUIRQSEL18 is shown in Figure 4-28 and described in Table 4-34. Output Selection for CPU Interrupt 18 Figure 4-28. CPUIRQSEL18 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-13h 1 0 Table 4-34.
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Interrupts and Events Registers www.ti.com 4.6.2.20 CPUIRQSEL19 Register (Offset = 4Ch) [reset = X] CPUIRQSEL19 is shown in Figure 4-29 and described in Table 4-35. Output Selection for CPU Interrupt 19 Figure 4-29. CPUIRQSEL19 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-Ch 1 0 Table 4-35.
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Interrupts and Events Registers www.ti.com 4.6.2.21 CPUIRQSEL20 Register (Offset = 50h) [reset = X] CPUIRQSEL20 is shown in Figure 4-30 and described in Table 4-36. Output Selection for CPU Interrupt 20 Figure 4-30. CPUIRQSEL20 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-Dh 1 0 Table 4-36.
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Interrupts and Events Registers www.ti.com 4.6.2.22 CPUIRQSEL21 Register (Offset = 54h) [reset = X] CPUIRQSEL21 is shown in Figure 4-31 and described in Table 4-37. Output Selection for CPU Interrupt 21 Figure 4-31. CPUIRQSEL21 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-Eh 1 0 Table 4-37.
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Interrupts and Events Registers www.ti.com 4.6.2.23 CPUIRQSEL22 Register (Offset = 58h) [reset = X] CPUIRQSEL22 is shown in Figure 4-32 and described in Table 4-38. Output Selection for CPU Interrupt 22 Figure 4-32. CPUIRQSEL22 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-Fh 1 0 Table 4-38.
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Interrupts and Events Registers www.ti.com 4.6.2.24 CPUIRQSEL23 Register (Offset = 5Ch) [reset = X] CPUIRQSEL23 is shown in Figure 4-33 and described in Table 4-39. Output Selection for CPU Interrupt 23 Figure 4-33. CPUIRQSEL23 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-5Dh 1 0 Table 4-39.
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Interrupts and Events Registers www.ti.com 4.6.2.25 CPUIRQSEL24 Register (Offset = 60h) [reset = X] CPUIRQSEL24 is shown in Figure 4-34 and described in Table 4-40. Output Selection for CPU Interrupt 24 Figure 4-34. CPUIRQSEL24 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-27h 1 0 Table 4-40.
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Interrupts and Events Registers www.ti.com 4.6.2.26 CPUIRQSEL25 Register (Offset = 64h) [reset = X] CPUIRQSEL25 is shown in Figure 4-35 and described in Table 4-41. Output Selection for CPU Interrupt 25 Figure 4-35. CPUIRQSEL25 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-26h 1 0 Table 4-41.
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Interrupts and Events Registers www.ti.com 4.6.2.27 CPUIRQSEL26 Register (Offset = 68h) [reset = X] CPUIRQSEL26 is shown in Figure 4-36 and described in Table 4-42. Output Selection for CPU Interrupt 26 Figure 4-36. CPUIRQSEL26 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-15h 1 0 Table 4-42.
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Interrupts and Events Registers www.ti.com 4.6.2.28 CPUIRQSEL27 Register (Offset = 6Ch) [reset = X] CPUIRQSEL27 is shown in Figure 4-37 and described in Table 4-43. Output Selection for CPU Interrupt 27 Figure 4-37. CPUIRQSEL27 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-64h 1 0 Table 4-43.
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Interrupts and Events Registers www.ti.com 4.6.2.29 CPUIRQSEL28 Register (Offset = 70h) [reset = X] CPUIRQSEL28 is shown in Figure 4-38 and described in Table 4-44. Output Selection for CPU Interrupt 28 Figure 4-38. CPUIRQSEL28 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-Bh 1 0 Table 4-44.
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Interrupts and Events Registers www.ti.com 4.6.2.30 CPUIRQSEL29 Register (Offset = 74h) [reset = X] CPUIRQSEL29 is shown in Figure 4-39 and described in Table 4-45. Output Selection for CPU Interrupt 29 Figure 4-39. CPUIRQSEL29 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-1h 1 0 Table 4-45.
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Interrupts and Events Registers www.ti.com 4.6.2.31 CPUIRQSEL30 Register (Offset = 78h) [reset = X] CPUIRQSEL30 is shown in Figure 4-40 and described in Table 4-46. Output Selection for CPU Interrupt 30 Figure 4-40. CPUIRQSEL30 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R/W-X 1 0 Table 4-46.
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Interrupts and Events Registers www.ti.com 4.6.2.32 CPUIRQSEL31 Register (Offset = 7Ch) [reset = X] CPUIRQSEL31 is shown in Figure 4-41 and described in Table 4-47. Output Selection for CPU Interrupt 31 Figure 4-41. CPUIRQSEL31 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-6Ah 1 0 Table 4-47.
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Interrupts and Events Registers www.ti.com 4.6.2.33 CPUIRQSEL32 Register (Offset = 80h) [reset = X] CPUIRQSEL32 is shown in Figure 4-42 and described in Table 4-48. Output Selection for CPU Interrupt 32 Figure 4-42. CPUIRQSEL32 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-73h 1 0 Table 4-48.
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Interrupts and Events Registers www.ti.com 4.6.2.34 CPUIRQSEL33 Register (Offset = 84h) [reset = X] CPUIRQSEL33 is shown in Figure 4-43 and described in Table 4-49. Output Selection for CPU Interrupt 33 Figure 4-43. CPUIRQSEL33 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-68h 1 0 Table 4-49.
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Interrupts and Events Registers www.ti.com 4.6.2.35 RFCSEL0 Register (Offset = 100h) [reset = X] RFCSEL0 is shown in Figure 4-44 and described in Table 4-50. Output Selection for RFC Event 0 Figure 4-44. RFCSEL0 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-3Dh 1 0 Table 4-50. RFCSEL0 Register Field Descriptions Field Type Reset Description 31-7 Bit RESERVED R X Software should not rely on the value of a reserved.
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Interrupts and Events Registers www.ti.com 4.6.2.36 RFCSEL1 Register (Offset = 104h) [reset = X] RFCSEL1 is shown in Figure 4-45 and described in Table 4-51. Output Selection for RFC Event 1 Figure 4-45. RFCSEL1 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-3Eh 1 0 Table 4-51. RFCSEL1 Register Field Descriptions Bit 308 Field Type Reset Description 31-7 RESERVED R X Software should not rely on the value of a reserved.
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Interrupts and Events Registers www.ti.com 4.6.2.37 RFCSEL2 Register (Offset = 108h) [reset = X] RFCSEL2 is shown in Figure 4-46 and described in Table 4-52. Output Selection for RFC Event 2 Figure 4-46. RFCSEL2 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-3Fh 1 0 Table 4-52. RFCSEL2 Register Field Descriptions Field Type Reset Description 31-7 Bit RESERVED R X Software should not rely on the value of a reserved.
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Interrupts and Events Registers www.ti.com 4.6.2.38 RFCSEL3 Register (Offset = 10Ch) [reset = X] RFCSEL3 is shown in Figure 4-47 and described in Table 4-53. Output Selection for RFC Event 3 Figure 4-47. RFCSEL3 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-40h 1 0 Table 4-53. RFCSEL3 Register Field Descriptions Bit 310 Field Type Reset Description 31-7 RESERVED R X Software should not rely on the value of a reserved.
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Interrupts and Events Registers www.ti.com 4.6.2.39 RFCSEL4 Register (Offset = 110h) [reset = X] RFCSEL4 is shown in Figure 4-48 and described in Table 4-54. Output Selection for RFC Event 4 Figure 4-48. RFCSEL4 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-41h 1 0 Table 4-54. RFCSEL4 Register Field Descriptions Field Type Reset Description 31-7 Bit RESERVED R X Software should not rely on the value of a reserved.
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Interrupts and Events Registers www.ti.com 4.6.2.40 RFCSEL5 Register (Offset = 114h) [reset = X] RFCSEL5 is shown in Figure 4-49 and described in Table 4-55. Output Selection for RFC Event 5 Figure 4-49. RFCSEL5 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-42h 1 0 Table 4-55. RFCSEL5 Register Field Descriptions Bit 312 Field Type Reset Description 31-7 RESERVED R X Software should not rely on the value of a reserved.
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Interrupts and Events Registers www.ti.com 4.6.2.41 RFCSEL6 Register (Offset = 118h) [reset = X] RFCSEL6 is shown in Figure 4-50 and described in Table 4-56. Output Selection for RFC Event 6 Figure 4-50. RFCSEL6 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-43h 1 0 Table 4-56. RFCSEL6 Register Field Descriptions Field Type Reset Description 31-7 Bit RESERVED R X Software should not rely on the value of a reserved.
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Interrupts and Events Registers www.ti.com 4.6.2.42 RFCSEL7 Register (Offset = 11Ch) [reset = X] RFCSEL7 is shown in Figure 4-51 and described in Table 4-57. Output Selection for RFC Event 7 Figure 4-51. RFCSEL7 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-44h 1 0 Table 4-57. RFCSEL7 Register Field Descriptions Bit 314 Field Type Reset Description 31-7 RESERVED R X Software should not rely on the value of a reserved.
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Interrupts and Events Registers www.ti.com 4.6.2.43 RFCSEL8 Register (Offset = 120h) [reset = X] RFCSEL8 is shown in Figure 4-52 and described in Table 4-58. Output Selection for RFC Event 8 Figure 4-52. RFCSEL8 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-77h 1 0 Table 4-58. RFCSEL8 Register Field Descriptions Field Type Reset Description 31-7 Bit RESERVED R X Software should not rely on the value of a reserved.
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Interrupts and Events Registers www.ti.com 4.6.2.44 RFCSEL9 Register (Offset = 124h) [reset = X] RFCSEL9 is shown in Figure 4-53 and described in Table 4-59. Output Selection for RFC Event 9 Figure 4-53. RFCSEL9 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R/W-2h 1 0 Table 4-59. RFCSEL9 Register Field Descriptions Bit 316 Field Type Reset Description 31-7 RESERVED R X Software should not rely on the value of a reserved.
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Interrupts and Events Registers www.ti.com 4.6.2.45 GPT0ACAPTSEL Register (Offset = 200h) [reset = X] GPT0ACAPTSEL is shown in Figure 4-54 and described in Table 4-60. Output Selection for GPT0 0 Figure 4-54. GPT0ACAPTSEL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R/W-55h 1 0 Table 4-60.
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Interrupts and Events Registers www.ti.com Table 4-60. GPT0ACAPTSEL Register Field Descriptions (continued) 318 Bit Field Type Reset Description 6-0 EV R/W 55h Read/write selection value 0h = Always inactive 4h = Edge detect event from IOC. Configureded by the IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings 5h = A complete byte transfer event from the SPIS. Equivalent to the SPIS:GPFLAGS.BYTE_DONE flag 6h = SPIS chip select event. Equivalent to the SPIS:GPFLAGS.
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Interrupts and Events Registers www.ti.com Table 4-60. GPT0ACAPTSEL Register Field Descriptions (continued) Bit Field Type Reset Description 6Eh = AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV 6Fh = Autotake event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE 70h = AUX ADC done, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE 71h = AUX ADC FIFO watermark event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.
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Interrupts and Events Registers www.ti.com 4.6.2.46 GPT0BCAPTSEL Register (Offset = 204h) [reset = X] GPT0BCAPTSEL is shown in Figure 4-55 and described in Table 4-61. Output Selection for GPT0 1 Figure 4-55. GPT0BCAPTSEL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R/W-56h 1 0 Table 4-61.
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Interrupts and Events Registers www.ti.com Table 4-61. GPT0BCAPTSEL Register Field Descriptions (continued) Bit Field Type Reset Description 6-0 EV R/W 56h Read/write selection value 0h = Always inactive 4h = Edge detect event from IOC. Configureded by the IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings 5h = A complete byte transfer event from the SPIS. Equivalent to the SPIS:GPFLAGS.BYTE_DONE flag 6h = SPIS chip select event. Equivalent to the SPIS:GPFLAGS.
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Interrupts and Events Registers www.ti.com Table 4-61. GPT0BCAPTSEL Register Field Descriptions (continued) Bit Field Type Reset Description 6Eh = AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV 6Fh = Autotake event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE 70h = AUX ADC done, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE 71h = AUX ADC FIFO watermark event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.
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Interrupts and Events Registers www.ti.com 4.6.2.47 GPT1ACAPTSEL Register (Offset = 300h) [reset = X] GPT1ACAPTSEL is shown in Figure 4-56 and described in Table 4-62. Output Selection for GPT1 0 Figure 4-56. GPT1ACAPTSEL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R/W-57h 1 0 Table 4-62.
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Interrupts and Events Registers www.ti.com Table 4-62. GPT1ACAPTSEL Register Field Descriptions (continued) 324 Bit Field Type Reset Description 6-0 EV R/W 57h Read/write selection value 0h = Always inactive 4h = Edge detect event from IOC. Configureded by the IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings 5h = A complete byte transfer event from the SPIS. Equivalent to the SPIS:GPFLAGS.BYTE_DONE flag 6h = SPIS chip select event. Equivalent to the SPIS:GPFLAGS.
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Interrupts and Events Registers www.ti.com Table 4-62. GPT1ACAPTSEL Register Field Descriptions (continued) Bit Field Type Reset Description 6Eh = AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV 6Fh = Autotake event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE 70h = AUX ADC done, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE 71h = AUX ADC FIFO watermark event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.
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Interrupts and Events Registers www.ti.com 4.6.2.48 GPT1BCAPTSEL Register (Offset = 304h) [reset = X] GPT1BCAPTSEL is shown in Figure 4-57 and described in Table 4-63. Output Selection for GPT1 1 Figure 4-57. GPT1BCAPTSEL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R/W-58h 1 0 Table 4-63.
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Interrupts and Events Registers www.ti.com Table 4-63. GPT1BCAPTSEL Register Field Descriptions (continued) Bit Field Type Reset Description 6-0 EV R/W 58h Read/write selection value 0h = Always inactive 4h = Edge detect event from IOC. Configureded by the IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings 5h = A complete byte transfer event from the SPIS. Equivalent to the SPIS:GPFLAGS.BYTE_DONE flag 6h = SPIS chip select event. Equivalent to the SPIS:GPFLAGS.
PAGE 328
Interrupts and Events Registers www.ti.com Table 4-63. GPT1BCAPTSEL Register Field Descriptions (continued) Bit Field Type Reset Description 6Eh = AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV 6Fh = Autotake event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE 70h = AUX ADC done, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE 71h = AUX ADC FIFO watermark event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.
PAGE 329
Interrupts and Events Registers www.ti.com 4.6.2.49 GPT2ACAPTSEL Register (Offset = 400h) [reset = X] GPT2ACAPTSEL is shown in Figure 4-58 and described in Table 4-64. Output Selection for GPT2 0 Figure 4-58. GPT2ACAPTSEL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R/W-59h 1 0 Table 4-64.
PAGE 330
Interrupts and Events Registers www.ti.com Table 4-64. GPT2ACAPTSEL Register Field Descriptions (continued) 330 Bit Field Type Reset Description 6-0 EV R/W 59h Read/write selection value 0h = Always inactive 4h = Edge detect event from IOC. Configureded by the IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings 5h = A complete byte transfer event from the SPIS. Equivalent to the SPIS:GPFLAGS.BYTE_DONE flag 6h = SPIS chip select event. Equivalent to the SPIS:GPFLAGS.
PAGE 331
Interrupts and Events Registers www.ti.com Table 4-64. GPT2ACAPTSEL Register Field Descriptions (continued) Bit Field Type Reset Description 6Eh = AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV 6Fh = Autotake event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE 70h = AUX ADC done, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE 71h = AUX ADC FIFO watermark event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.
PAGE 332
Interrupts and Events Registers www.ti.com 4.6.2.50 GPT2BCAPTSEL Register (Offset = 404h) [reset = X] GPT2BCAPTSEL is shown in Figure 4-59 and described in Table 4-65. Output Selection for GPT2 1 Figure 4-59. GPT2BCAPTSEL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R/W-5Ah 1 0 Table 4-65.
PAGE 333
Interrupts and Events Registers www.ti.com Table 4-65. GPT2BCAPTSEL Register Field Descriptions (continued) Bit Field Type Reset Description 6-0 EV R/W 5Ah Read/write selection value 0h = Always inactive 4h = Edge detect event from IOC. Configureded by the IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings 5h = A complete byte transfer event from the SPIS. Equivalent to the SPIS:GPFLAGS.BYTE_DONE flag 6h = SPIS chip select event. Equivalent to the SPIS:GPFLAGS.
PAGE 334
Interrupts and Events Registers www.ti.com Table 4-65. GPT2BCAPTSEL Register Field Descriptions (continued) Bit Field Type Reset Description 6Eh = AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV 6Fh = Autotake event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE 70h = AUX ADC done, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE 71h = AUX ADC FIFO watermark event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.
PAGE 335
Interrupts and Events Registers www.ti.com 4.6.2.51 UDMACH1SSEL Register (Offset = 508h) [reset = X] UDMACH1SSEL is shown in Figure 4-60 and described in Table 4-66. Output Selection for DMA Channel 1 SREQ Figure 4-60. UDMACH1SSEL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-31h 1 0 Table 4-66.
PAGE 336
Interrupts and Events Registers www.ti.com 4.6.2.52 UDMACH1BSEL Register (Offset = 50Ch) [reset = X] UDMACH1BSEL is shown in Figure 4-61 and described in Table 4-67. Output Selection for DMA Channel 1 REQ Figure 4-61. UDMACH1BSEL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-30h 1 0 Table 4-67.
PAGE 337
Interrupts and Events Registers www.ti.com 4.6.2.53 UDMACH2SSEL Register (Offset = 510h) [reset = X] UDMACH2SSEL is shown in Figure 4-62 and described in Table 4-68. Output Selection for DMA Channel 2 SREQ Figure 4-62. UDMACH2SSEL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-33h 1 0 Table 4-68.
PAGE 338
Interrupts and Events Registers www.ti.com 4.6.2.54 UDMACH2BSEL Register (Offset = 514h) [reset = X] UDMACH2BSEL is shown in Figure 4-63 and described in Table 4-69. Output Selection for DMA Channel 2 REQ Figure 4-63. UDMACH2BSEL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-32h 1 0 Table 4-69.
PAGE 339
Interrupts and Events Registers www.ti.com 4.6.2.55 UDMACH3SSEL Register (Offset = 518h) [reset = X] UDMACH3SSEL is shown in Figure 4-64 and described in Table 4-70. Output Selection for DMA Channel 3 SREQ Figure 4-64. UDMACH3SSEL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-29h 1 0 Table 4-70.
PAGE 340
Interrupts and Events Registers www.ti.com 4.6.2.56 UDMACH3BSEL Register (Offset = 51Ch) [reset = X] UDMACH3BSEL is shown in Figure 4-65 and described in Table 4-71. Output Selection for DMA Channel 3 REQ Figure 4-65. UDMACH3BSEL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-28h 1 0 Table 4-71.
PAGE 341
Interrupts and Events Registers www.ti.com 4.6.2.57 UDMACH4SSEL Register (Offset = 520h) [reset = X] UDMACH4SSEL is shown in Figure 4-66 and described in Table 4-72. Output Selection for DMA Channel 4 SREQ Figure 4-66. UDMACH4SSEL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-2Bh 1 0 Table 4-72.
PAGE 342
Interrupts and Events Registers www.ti.com 4.6.2.58 UDMACH4BSEL Register (Offset = 524h) [reset = X] UDMACH4BSEL is shown in Figure 4-67 and described in Table 4-73. Output Selection for DMA Channel 4 REQ Figure 4-67. UDMACH4BSEL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-2Ah 1 0 Table 4-73.
PAGE 343
Interrupts and Events Registers www.ti.com 4.6.2.59 UDMACH5SSEL Register (Offset = 528h) [reset = X] UDMACH5SSEL is shown in Figure 4-68 and described in Table 4-74. Output Selection for DMA Channel 5 SREQ Figure 4-68. UDMACH5SSEL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-3Ah 1 0 Table 4-74.
PAGE 344
Interrupts and Events Registers www.ti.com 4.6.2.60 UDMACH5BSEL Register (Offset = 52Ch) [reset = X] UDMACH5BSEL is shown in Figure 4-69 and described in Table 4-75. Output Selection for DMA Channel 5 REQ Figure 4-69. UDMACH5BSEL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-39h 1 0 Table 4-75.
PAGE 345
Interrupts and Events Registers www.ti.com 4.6.2.61 UDMACH6SSEL Register (Offset = 530h) [reset = X] UDMACH6SSEL is shown in Figure 4-70 and described in Table 4-76. Output Selection for DMA Channel 6 SREQ Figure 4-70. UDMACH6SSEL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-3Ch 1 0 Table 4-76.
PAGE 346
Interrupts and Events Registers www.ti.com 4.6.2.62 UDMACH6BSEL Register (Offset = 534h) [reset = X] UDMACH6BSEL is shown in Figure 4-71 and described in Table 4-77. Output Selection for DMA Channel 6 REQ Figure 4-71. UDMACH6BSEL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-3Bh 1 0 Table 4-77.
PAGE 347
Interrupts and Events Registers www.ti.com 4.6.2.63 UDMACH7SSEL Register (Offset = 538h) [reset = X] UDMACH7SSEL is shown in Figure 4-72 and described in Table 4-78. Output Selection for DMA Channel 7 SREQ Figure 4-72. UDMACH7SSEL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-75h 1 0 Table 4-78.
PAGE 348
Interrupts and Events Registers www.ti.com 4.6.2.64 UDMACH7BSEL Register (Offset = 53Ch) [reset = X] UDMACH7BSEL is shown in Figure 4-73 and described in Table 4-79. Output Selection for DMA Channel 7 REQ Figure 4-73. UDMACH7BSEL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-76h 1 0 Table 4-79.
PAGE 349
Interrupts and Events Registers www.ti.com 4.6.2.65 UDMACH8SSEL Register (Offset = 540h) [reset = X] UDMACH8SSEL is shown in Figure 4-74 and described in Table 4-80. Output Selection for DMA Channel 8 SREQ Single request is ignored for this channel Figure 4-74. UDMACH8SSEL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-74h 1 0 Table 4-80.
PAGE 350
Interrupts and Events Registers www.ti.com 4.6.2.66 UDMACH8BSEL Register (Offset = 544h) [reset = X] UDMACH8BSEL is shown in Figure 4-75 and described in Table 4-81. Output Selection for DMA Channel 8 REQ Figure 4-75. UDMACH8BSEL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-74h 1 0 Table 4-81.
PAGE 351
Interrupts and Events Registers www.ti.com 4.6.2.67 UDMACH9SSEL Register (Offset = 548h) [reset = X] UDMACH9SSEL is shown in Figure 4-76 and described in Table 4-82. Output Selection for DMA Channel 9 SREQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMAARIS Figure 4-76. UDMACH9SSEL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R/W-45h 1 0 Table 4-82.
PAGE 352
Interrupts and Events Registers www.ti.com 4.6.2.68 UDMACH9BSEL Register (Offset = 54Ch) [reset = X] UDMACH9BSEL is shown in Figure 4-77 and described in Table 4-83. Output Selection for DMA Channel 9 REQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMAARIS Figure 4-77. UDMACH9BSEL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R/W-4Dh 1 0 Table 4-83.
PAGE 353
Interrupts and Events Registers www.ti.com 4.6.2.69 UDMACH10SSEL Register (Offset = 550h) [reset = X] UDMACH10SSEL is shown in Figure 4-78 and described in Table 4-84. Output Selection for DMA Channel 10 SREQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMABRIS Figure 4-78. UDMACH10SSEL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R/W-46h 1 0 Table 4-84.
PAGE 354
Interrupts and Events Registers www.ti.com 4.6.2.70 UDMACH10BSEL Register (Offset = 554h) [reset = X] UDMACH10BSEL is shown in Figure 4-79 and described in Table 4-85. Output Selection for DMA Channel 10 REQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMABRIS Figure 4-79. UDMACH10BSEL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R/W-4Eh 1 0 Table 4-85.
PAGE 355
Interrupts and Events Registers www.ti.com 4.6.2.71 UDMACH11SSEL Register (Offset = 558h) [reset = X] UDMACH11SSEL is shown in Figure 4-80 and described in Table 4-86. Output Selection for DMA Channel 11 SREQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMAARIS Figure 4-80. UDMACH11SSEL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R/W-47h 1 0 Table 4-86.
PAGE 356
Interrupts and Events Registers www.ti.com 4.6.2.72 UDMACH11BSEL Register (Offset = 55Ch) [reset = X] UDMACH11BSEL is shown in Figure 4-81 and described in Table 4-87. Output Selection for DMA Channel 11 REQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMAARIS Figure 4-81. UDMACH11BSEL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R/W-4Fh 1 0 Table 4-87.
PAGE 357
Interrupts and Events Registers www.ti.com 4.6.2.73 UDMACH12SSEL Register (Offset = 560h) [reset = X] UDMACH12SSEL is shown in Figure 4-82 and described in Table 4-88. Output Selection for DMA Channel 12 SREQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMABRIS Figure 4-82. UDMACH12SSEL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R/W-48h 1 0 Table 4-88.
PAGE 358
Interrupts and Events Registers www.ti.com 4.6.2.74 UDMACH12BSEL Register (Offset = 564h) [reset = X] UDMACH12BSEL is shown in Figure 4-83 and described in Table 4-89. Output Selection for DMA Channel 12 REQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMABRIS Figure 4-83. UDMACH12BSEL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R/W-50h 1 0 Table 4-89.
PAGE 359
Interrupts and Events Registers www.ti.com 4.6.2.75 UDMACH13BSEL Register (Offset = 56Ch) [reset = X] UDMACH13BSEL is shown in Figure 4-84 and described in Table 4-90. Output Selection for DMA Channel 13 REQ Figure 4-84. UDMACH13BSEL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-3h 1 0 Table 4-90.
PAGE 360
Interrupts and Events Registers www.ti.com 4.6.2.76 UDMACH14BSEL Register (Offset = 574h) [reset = X] UDMACH14BSEL is shown in Figure 4-85 and described in Table 4-91. Output Selection for DMA Channel 14 REQ Figure 4-85. UDMACH14BSEL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R/W-1h 1 0 Table 4-91.
PAGE 361
Interrupts and Events Registers www.ti.com Table 4-91. UDMACH14BSEL Register Field Descriptions (continued) Bit Field Type Reset Description 6-0 EV R/W 1h Read/write selection value 0h = Always inactive 1h = Event selected by AON_EVENT MCU event selector, AON_EVENT:EVTOMCUSEL.AON_PROG0_EV 2h = Event selected by AON_EVENT MCU event selector, AON_EVENT:EVTOMCUSEL.AON_PROG1_EV 3h = Event selected by AON_EVENT MCU event selector, AON_EVENT:EVTOMCUSEL.AON_PROG2_EV 4h = Edge detect event from IOC.
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Interrupts and Events Registers www.ti.com Table 4-91. UDMACH14BSEL Register Field Descriptions (continued) Bit Field Type Reset Description 27h = Combined DMA done corresponding flags are here UDMA0:REQDONE 28h = SSI0 RX DMA burst request , controlled by SSI0:DMACR.RXDMAE 29h = SSI0 RX DMA single request, controlled by SSI0:DMACR.RXDMAE 2Ah = SSI0 TX DMA burst request , controlled by SSI0:DMACR.TXDMAE 2Bh = SSI0 TX DMA single request, controlled by SSI0:DMACR.
PAGE 363
Interrupts and Events Registers www.ti.com Table 4-91. UDMACH14BSEL Register Field Descriptions (continued) Bit Field Type Reset Description 58h = Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT3 wil be routed here. 59h = Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT4 wil be routed here. 5Ah = Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID.
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Interrupts and Events Registers www.ti.com Table 4-91. UDMACH14BSEL Register Field Descriptions (continued) Bit Field Type Reset Description AON_RTC:CTL.
PAGE 365
Interrupts and Events Registers www.ti.com 4.6.2.77 UDMACH15BSEL Register (Offset = 57Ch) [reset = X] UDMACH15BSEL is shown in Figure 4-86 and described in Table 4-92. Output Selection for DMA Channel 15 REQ Figure 4-86. UDMACH15BSEL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-7h 1 0 Table 4-92.
PAGE 366
Interrupts and Events Registers www.ti.com 4.6.2.78 UDMACH16SSEL Register (Offset = 580h) [reset = X] UDMACH16SSEL is shown in Figure 4-87 and described in Table 4-93. Output Selection for DMA Channel 16 SREQ Figure 4-87. UDMACH16SSEL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-2Dh 1 0 Table 4-93.
PAGE 367
Interrupts and Events Registers www.ti.com 4.6.2.79 UDMACH16BSEL Register (Offset = 584h) [reset = X] UDMACH16BSEL is shown in Figure 4-88 and described in Table 4-94. Output Selection for DMA Channel 16 REQ Figure 4-88. UDMACH16BSEL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-2Ch 1 0 Table 4-94.
PAGE 368
Interrupts and Events Registers www.ti.com 4.6.2.80 UDMACH17SSEL Register (Offset = 588h) [reset = X] UDMACH17SSEL is shown in Figure 4-89 and described in Table 4-95. Output Selection for DMA Channel 17 SREQ Figure 4-89. UDMACH17SSEL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-2Fh 1 0 Table 4-95.
PAGE 369
Interrupts and Events Registers www.ti.com 4.6.2.81 UDMACH17BSEL Register (Offset = 58Ch) [reset = X] UDMACH17BSEL is shown in Figure 4-90 and described in Table 4-96. Output Selection for DMA Channel 17 REQ Figure 4-90. UDMACH17BSEL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-2Eh 1 0 Table 4-96.
PAGE 370
Interrupts and Events Registers www.ti.com 4.6.2.82 UDMACH21SSEL Register (Offset = 5A8h) [reset = X] UDMACH21SSEL is shown in Figure 4-91 and described in Table 4-97. Output Selection for DMA Channel 21 SREQ Figure 4-91. UDMACH21SSEL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-64h 1 0 Table 4-97.
PAGE 371
Interrupts and Events Registers www.ti.com 4.6.2.83 UDMACH21BSEL Register (Offset = 5ACh) [reset = X] UDMACH21BSEL is shown in Figure 4-92 and described in Table 4-98. Output Selection for DMA Channel 21 REQ Figure 4-92. UDMACH21BSEL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-64h 1 0 Table 4-98.
PAGE 372
Interrupts and Events Registers www.ti.com 4.6.2.84 UDMACH22SSEL Register (Offset = 5B0h) [reset = X] UDMACH22SSEL is shown in Figure 4-93 and described in Table 4-99. Output Selection for DMA Channel 22 SREQ Figure 4-93. UDMACH22SSEL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-65h 1 0 Table 4-99.
PAGE 373
Interrupts and Events Registers www.ti.com 4.6.2.85 UDMACH22BSEL Register (Offset = 5B4h) [reset = X] UDMACH22BSEL is shown in Figure 4-94 and described in Table 4-100. Output Selection for DMA Channel 22 REQ Figure 4-94. UDMACH22BSEL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-65h 1 0 Table 4-100.
PAGE 374
Interrupts and Events Registers www.ti.com 4.6.2.86 UDMACH23SSEL Register (Offset = 5B8h) [reset = X] UDMACH23SSEL is shown in Figure 4-95 and described in Table 4-101. Output Selection for DMA Channel 23 SREQ Figure 4-95. UDMACH23SSEL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-66h 1 0 Table 4-101.
PAGE 375
Interrupts and Events Registers www.ti.com 4.6.2.87 UDMACH23BSEL Register (Offset = 5BCh) [reset = X] UDMACH23BSEL is shown in Figure 4-96 and described in Table 4-102. Output Selection for DMA Channel 23 REQ Figure 4-96. UDMACH23BSEL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-66h 1 0 Table 4-102.
PAGE 376
Interrupts and Events Registers www.ti.com 4.6.2.88 UDMACH24SSEL Register (Offset = 5C0h) [reset = X] UDMACH24SSEL is shown in Figure 4-97 and described in Table 4-103. Output Selection for DMA Channel 24 SREQ Figure 4-97. UDMACH24SSEL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-67h 1 0 Table 4-103.
PAGE 377
Interrupts and Events Registers www.ti.com 4.6.2.89 UDMACH24BSEL Register (Offset = 5C4h) [reset = X] UDMACH24BSEL is shown in Figure 4-98 and described in Table 4-104. Output Selection for DMA Channel 24 REQ Figure 4-98. UDMACH24BSEL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-67h 1 0 Table 4-104.
PAGE 378
Interrupts and Events Registers www.ti.com 4.6.2.90 GPT3ACAPTSEL Register (Offset = 600h) [reset = X] GPT3ACAPTSEL is shown in Figure 4-99 and described in Table 4-105. Output Selection for GPT3 0 Figure 4-99. GPT3ACAPTSEL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R/W-5Bh 1 0 Table 4-105.
PAGE 379
Interrupts and Events Registers www.ti.com Table 4-105. GPT3ACAPTSEL Register Field Descriptions (continued) Bit Field Type Reset Description 6-0 EV R/W 5Bh Read/write selection value 0h = Always inactive 4h = Edge detect event from IOC. Configureded by the IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings 5h = A complete byte transfer event from the SPIS. Equivalent to the SPIS:GPFLAGS.BYTE_DONE flag 6h = SPIS chip select event. Equivalent to the SPIS:GPFLAGS.
PAGE 380
Interrupts and Events Registers www.ti.com Table 4-105. GPT3ACAPTSEL Register Field Descriptions (continued) Bit Field Type Reset Description AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV 6Fh = Autotake event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE 70h = AUX ADC done, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE 71h = AUX ADC FIFO watermark event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL 72h = Loopback of OBSMUX0 through AUX, corresponds to AUX_EVCTL:EVTOMCUFLAGS.
PAGE 381
Interrupts and Events Registers www.ti.com 4.6.2.91 GPT3BCAPTSEL Register (Offset = 604h) [reset = X] GPT3BCAPTSEL is shown in Figure 4-100 and described in Table 4-106. Output Selection for GPT3 1 Figure 4-100. GPT3BCAPTSEL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R/W-5Ch 1 0 Table 4-106.
PAGE 382
Interrupts and Events Registers www.ti.com Table 4-106. GPT3BCAPTSEL Register Field Descriptions (continued) 382 Bit Field Type Reset Description 6-0 EV R/W 5Ch Read/write selection value 0h = Always inactive 4h = Edge detect event from IOC. Configureded by the IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings 5h = A complete byte transfer event from the SPIS. Equivalent to the SPIS:GPFLAGS.BYTE_DONE flag 6h = SPIS chip select event. Equivalent to the SPIS:GPFLAGS.
PAGE 383
Interrupts and Events Registers www.ti.com Table 4-106. GPT3BCAPTSEL Register Field Descriptions (continued) Bit Field Type Reset Description AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV 6Fh = Autotake event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE 70h = AUX ADC done, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE 71h = AUX ADC FIFO watermark event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL 72h = Loopback of OBSMUX0 through AUX, corresponds to AUX_EVCTL:EVTOMCUFLAGS.
PAGE 384
Interrupts and Events Registers www.ti.com 4.6.2.92 AUXSEL0 Register (Offset = 700h) [reset = X] AUXSEL0 is shown in Figure 4-101 and described in Table 4-107. Output Selection for AUX Subscriber 0 Figure 4-101. AUXSEL0 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R/W-10h 1 0 Table 4-107.
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Interrupts and Events Registers www.ti.com 4.6.2.93 CM3NMISEL0 Register (Offset = 800h) [reset = X] CM3NMISEL0 is shown in Figure 4-102 and described in Table 4-108. Output Selection for NMI Subscriber 0 Figure 4-102. CM3NMISEL0 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R-63h 1 0 Table 4-108.
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Interrupts and Events Registers www.ti.com 4.6.2.94 I2SSTMPSEL0 Register (Offset = 900h) [reset = X] I2SSTMPSEL0 is shown in Figure 4-103 and described in Table 4-109. Output Selection for I2S Subscriber 0 Figure 4-103. I2SSTMPSEL0 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R/W-5Fh 1 0 Table 4-109.
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Interrupts and Events Registers www.ti.com 4.6.2.95 FRZSEL0 Register (Offset = A00h) [reset = X] FRZSEL0 is shown in Figure 4-104 and described in Table 4-110. Output Selection for FRZ Subscriber 0 Figure 4-104. FRZSEL0 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 EV R/W-78h 1 0 Table 4-110. FRZSEL0 Register Field Descriptions Field Type Reset Description 31-7 Bit RESERVED R X Software should not rely on the value of a reserved.
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Interrupts and Events Registers www.ti.com 4.6.2.96 SWEV Register (Offset = F00h) [reset = X] SWEV is shown in Figure 4-105 and described in Table 4-111. Set or Clear Software Events Figure 4-105. SWEV Register 31 30 29 28 RESERVED R-X 27 26 25 24 SWEV3 R/W-X 23 22 21 20 RESERVED R-X 19 18 17 16 SWEV2 R/W-X 15 14 13 12 RESERVED R-X 11 10 9 8 SWEV1 R/W-X 7 6 5 4 RESERVED R-X 3 2 1 0 SWEV0 R/W-X Table 4-111.
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Chapter 5 SWCU117A – February 2015 – Revised March 2015 JTAG Interface This chapter describes the cJTAG and JTAG interface for on-chip debug support. Table 5-1. References ID Description [1] IEEE Standard Test Access Port and Boundary Scan Architecture, IEEE Std 1149.1a 1993 and Supplement Std. 1149.1b 1994, The Institute of Electrical and Electronics Engineers, Inc. [2] IEEE 1149.7 Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture Topic ............
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Top Level Debug System 5.1 www.ti.com Top Level Debug System The debug subsystem in CC26xx family implements two IEEE standards for debug and test purposes: • IEEE standard 1149.1: Standard Test Access Port and Boundary Scan Architecture Test Access Port (TAP) [1]. This standard is known by the acronym JTAG. • Class 4 IEEE 1149.7: Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture [2]. This is known by acronym cJTAG (compact JTAG).
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Top Level Debug System www.ti.com The IEEE 1149.1 TAP uses the following signals to support the operation: • TCK (Test Clock) – this signal synchronizes the internal state machine operations. • TMS (Test Mode Select) – this signal is sampled at the rising edge of TCK to determine the next state. • TDI (Test Data In) – this signal represents the data shifted into the test or programming logic of the device. TDI is sampled at the rising edge of TCK when the internal state machine is in the correct state.
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cJTAG 5.2 www.ti.com cJTAG This module implements IEEE 1149.7 compliant compact JTAG (cJTAG) adapter, which runs a 2-pin communication protocol on top of a IEEE 1149.1 JTAG test access port (TAP). The 2-pin JTAG mode using only TCK and TMS I/O pads is the default configuration after power up. The cJTAG configuration in CC26xx implements a subset of class 4 feature scan modes. Class 4 inherits features from classes 0, 1, 2, and 3 (except the features mentioned in Table 5-3.
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cJTAG www.ti.com Table 5-2. IEEE 1149.7 Feature Subset (continued) Scan formats IEEE 1149.
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cJTAG www.ti.com 5.2.1 JTAG Commands cJTAG commands are conveyed via benign JTAG scan activity. There are three basic steps: 1. Loading an inert opcode 2. Setting control level 2 3. Issue commands Before cJTAG commands are issued, the controller must ensure the scan activity will not initiate any unexpected actions in the device. To accomplish this, an inert opcode such as BYPASS or IDCODE must be loaded into the instruction register.
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cJTAG www.ti.com Table 5-4.
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cJTAG www.ti.com Table 5-4. cJTAG Commands (continued) OPCODE CCE Conditional Command Enable Operand: miiii m 00111 0 CGM bit of the targeted controller is set CGM bit of a non-targeted controller is cleared 1 CGM bit of the targeted controller is set CGM bit of a non-targeted controller is not affected SCNB Scan Bit Operand: yyyyy + CR Scan yyyyy 01000 01001–11111 5.2.1.1 00 SGC, Scan Group Candidate, write 01 CGM, Conditional Group Member, write 02-05 CNFG0-3, TAP.
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ICEPick™ www.ti.com 5.2.2.3 Close Command Window The command window can be closed by doing an IR scan, going to test logic reset, or by an ECL command. The ECL command is a subcommand of the STMC (opcode 0) command. The ECL command assumes the TAP state is starting from Pause DR. 1. Goto Scan (Through Update DR to Pause DR)—Does a Zero Bit scan to load CP0 with 0. 2. Scan DR (1 bit, end in Pause DR)—Load CP1 with 1. 3. Goto Scan (Through Update DR to Pause DR)—Complete CP1 by going through update.
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ICEPick™ www.ti.com Table 5-5. Slave TAP Order No Test TAP Name Description Availability for End User Test Banks (1) 0 TEST DFT functionalities and profiler See 1 PBIST1.0 RAM BIST controller interface Locked 2 PBIST2.
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ICEPick™ www.ti.com 5.3.2 ICEPick™ Registers Table 5-6 lists the control and status registers in ICEPick. Table 5-6.
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ICEPick™ 5.3.2.2 www.ti.com Data Shift Register Figure 5-4 is the register used to shift bits between the ICEPick TDI and TDO. This register is 32 bits wide. The data shift register has multiple shift in points to facilitate shifts on the instruction path and several of the data paths. Figure 5-4.
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ICEPick™ www.ti.com Table 5-8. Device Identification Register Description Field Width Description Version 4 Revision of the device Part Number 16 Part number of the device Manufacturer 11 TI’s JEDEC bank and company code: 00000010111b 0 1 This bit is always 1 5.3.2.6 User Code Register The User Code register helps to distinguish between the devices built from the same chip. The User Code register value is set through eFuse.
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ICEPick™ 5.3.2.8 www.ti.com Connect Register This register guards the device from noise, hot connection of an emulator cable, or accidental scan by a misconfigured scan controller. This register reduces the chances of accidentally engaging debug functions due to noise or accidental scans. Refer to Figure 5-10 and Table 5-11 for more details. Figure 5-10. Connect Register Bit TDI Access Reset 7 Write W 0 6 4 Reserved R 0 3 0 ConnectKey RW b0110 TDO Table 5-11.
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ICEPick™ www.ti.com Table 5-12. ROUTER DR Scan Chain Description Bit 31 Field Write Enable Width Type 1 W Reset 0 Description On scan-in: 0: Only a read is performed. 1: A write to the specified register is performed. On scan-out: If the previous scan resulted in a write to a ROUTER addressed register, then when bit 31 is scanned out during the next trip through the Shift DR state, it indicates whether the previous write succeeded. If 1, the previous write failed.
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ICEPick™ www.ti.com Table 5-13. Control Block Registers Register Register Name 0x0 All0s 0x1 Control 0x2 Linking Mode 0x3-0xF Reserved 5.3.4.1.1 All0s Register This register is a dummy register that returns 0 when read. Writes are ignored. There are not any side effects to writing or reading this register. Table 5-14. All0s Register Bit Field Width Type Reset Description 23-0 Zero 24 R 0 Read zero. 5.3.4.1.2 ICEPick™ Control Register Table 5-15.
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ICEPick™ www.ti.com 5.3.4.2 Test TAP Linking Block The Test TAP Linking block contains the control and status registers shown in Table 5-18 . These registers are used in to select of secondary TAPs into the master scan path. Each TAP has its own Test TAP Control and Status register. Table 5-18.
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ICEPick™ www.ti.com Table 5-21. Secondary Debug TAP Register [SDTR] Bit Field Width Type Reset Description 23-21 Reserved 3 RW 0 Reserved W 0 When 0, this bit does not influence the clock and the power settings to the module. While this bit is 1, if power or clock for TAP’s module is not allowed to be turned off once turned on. If the target does not have power or clock when setting this bit, InhibitSleep will not change power/clock state until the target is powered and clocked again.
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ICEPick™ www.ti.com Table 5-21. Secondary Debug TAP Register [SDTR] (continued) Bit 0 Field TapPresent Width Type 1 R Reset Description - When 0, there is not a TAP assigned to this spot. When 1, this TAP exists in the device. If a TAP does not exist, the rest of the controls and status bits in this register are considered to be non-operational.
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ICEMelter™ www.ti.com Table 5-22. Reset Control Value Command Description 000 Normal Operation Reset operates under the normal control of the application or device controls. 001 Wait in reset (Extend reset) The module(s) controlled by this secondary TAP will remain in the reset state once the reset has been asserted. This bit alone does not reset the processor. 010 Reserved Reserved 011 Reserved Reserved 1xx Cancel Cancels reset command lockout 5.
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Debug and Shutdown www.ti.com 5.7 Debug and Shutdown The debugger cannot stay connected in shutdown mode because the power source for debug subsystem turns off in this mode. This means that entering shutdown will cause abrupt disconnection from the emulator. To facilitate debugging of the shutdown scenarios, the CC26xx devices have some considerations: • If a device is in shutdown mode, activity on TCK will cause immediate wakeup.
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Profiler Register www.ti.com Table 5-24. Profiler Register Fields 410 Bit Width Description 77:61 17 Reserved 60:59 2 CPUs sleep state: 00: Run mode 01: Sleep mode 1x: Deepsleep mode 58 1 1: Warm reset in progress 0: No warm reset active 57 1 Error in compressed program counter values 1: The value returned in bits 56:36 cannot be trusted. 0: The value returned in bits 56:36 can be trusted.
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Chapter 6 SWCU117A – February 2015 – Revised March 2015 Power, Reset, and Clock Management This chapter details the flexible power management and clock control (PRCM) of the CC26xx device. Topic 6.1 6.2 ........................................................................................................................... Page Introduction ..................................................................................................... 412 PRCM Registers .........................................
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Introduction 6.1 www.ti.com Introduction Power and clock management (PRCM) in the CC26xx device is highly flexible to facilitate low-power applications. The following sections describe details for clock and power control in addition to covering reset features. The features in this chapter are embedded and optimized in TI-RTOS. TI-RTOS users may regard this chapter as informative only. Figure 6-1.
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Introduction www.ti.com 6.1.1 System CPU Mode The following chapter refers to the system CPU mode so it is important to understand what this means. The system CPU has three different operation modes: run, mode, and deepsleep (see Table 6-3). Each mode is used to gate internal clocks in the system CPU, in addition to peripheral clocks that may be gated in accordance to the current system CPU mode. Deepsleep mode is, in some cases, one of several requirements for powering down voltage and power domains.
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Introduction www.ti.com Figure 6-2. CC26xx Supply System VDDS LDO selected by PRCM:VDCTL.ULDO. Legend Voltage regulators Digital LDO Global LDO VDDR Voltage domain VDD DC-DC converter Power domain Micro LDO MCU_VD is controlled by AON_WUC:MCUCFG and AON_EVENT:MCUWUSEL. AON_VD MCU_VD MCU_AON is powered whenever MCU_VD is powered. Modules in AON is always powered when CC26xx is not in shutdown mode. AON AUX_PD is powered on by AON_WUC:AUXCTL.AUX_FORCE_ON = 1. For power off see AUX section.
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Introduction www.ti.com 6.1.2.2 External Regulator Mode The CC26xx device has an option to be supplied by an external regulator with a voltage range of 1.65 V to 1.95 V. In this mode, the VDDS and VDDR pins are tied together. To enable external regulator mode, the VDDS_DCDC pin and the DCDC_SW pins must be connected to ground. This effectively disables both the internal Global LDO and the internal DC/DC regulator.
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Introduction www.ti.com Figure 6-3. Digital Power Partitioning in CC26xx Legend MCU_VD Voltage domain MCU_AON CPU_PD PERIPH_PD Always-on logic System CPU PRCM Wakeup interrupt controller JTAG DAP DMA controller Power domain CRYPTO core Event fabric True random number gen.
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Introduction www.ti.com 6.1.3.1 MCU_VD The MCU voltage domain contains the CPU system divided into multiple power domains, as shown in Figure 6-3. MCU_VD also includes always-on logic not encapsulated in a power domain, but is powered whenever MCU_VD is powered. This in Figure 6-3 shows this logic as MCU_AON. MCU_VD is powered up by any enabled wake-up source. Requirements to power off MCU_VD is found in register description of [PRCM:VDCTL.MCU_VD]. 6.1.3.1.
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Introduction www.ti.com 6.1.4.1.1 Controlling the Oscillators Figure 6-3 shows that the oscillator interface is located in AUX_PD. For the system CPU to access the oscillator interface, perform the following steps: • Power on AUX_PD by setting [AON_WUC:AUXCTL:AUX_FORCE_ON] = 1 • Ensure AUX_PD is powered up by checking the bit [AON_WUC:PWRSTAT:AUX_PD_ON] • Turn on the oscillator interface clock in [AUX_WUC:MODCLKEN0: AUX_DDI0_OSC] = 1 Table 6-4.
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Introduction www.ti.com Figure 6-5. System Clock Muxing DDI_0_OSC:CTL0.SCLK_LF_SRC_SEL RCOSC 48 MHz / 1536 0 XTAL 24 MHz / 768 1 SCLK_LF RCOSC 32 kHz 2 3 XTAL 32.768 kHz 0 External 32 kHz 1 SCLK_LF_AUX DDI_0_OSC:CTL0.XOSC_LF_DIG_BYPASS DDI_0_OSC:CTL0.SCLK_HF_SRC_SEL RCOSC 48 MHz 0 SCLK_HF XTAL 24 MHz x2 1 ACLK_ADC DDI_0_OSC:CTL0.ACLK_TDC_SRC_SEL RCOSC 48 MHz 0 /2 1 ACLK_TDC XTAL 24 MHz 2 Unused 3 DDI_0_OSC:CTL0.
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Introduction 6.1.4.2 www.ti.com Clocks in MCU_VD AON_WUC supports MCU_VD with a clock that is divided and gated by PRCM before being distributed to all modules in MCU_VD. Figure 6-6 shows which registers in PRCM defines division and gate control for all module clocks. When no BUS transactions can occur, hardware will automatically gate the SYSBUS clock. These conditions must true to gate the SYSBUS: • • • • System CPU in deepsleep mode [PRCM.SECDMACLKGDS.DMA_CLK_EN] = 0 [PRCM.SECDMACLKGDS.
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Introduction www.ti.com Figure 6-6. Clocks in MCU_VD MCU clock SCLK_HF in active and Idle modes. Selected by AON_WUC:MCUCLK.PWR_DWN_SRC in standby mode. SCLK_HF SCLK_LF RFCORE_PD Divider Divide by 2 Clock gate PRCM:RFCCLKG.CLK_EN VIMS_PD Clock gate PRCM:VIMSCLKG.CLK_EN CPU_PD Conditional clock gate Clock disabled when system CPU is in SLEEP or DEEPSLEEP. Else clock is running.
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Introduction www.ti.com 6.1.4.2.1 Clock Gating As seen in Figure 6-6, the peripheral modules have conditional clock gates that depend on the system CPU mode. The clock of a module may be enabled or disabled when the system CPU mode changes. Example: • [PRCM:I2CCLKGR.CLK_EN] = 1 • [PRCM:I2CCLKGS.CLK_EN] = 0 • [PRCM:I2CCLKGDS.
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Introduction www.ti.com Table 6-5.
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Introduction 6.1.5.2 www.ti.com Active Mode Active mode is defined as any possible chip state where CPU_PD is powered, including BUS_PD and VIMS_PD (see Figure 6-2). In active mode, all modules are available and power consumption is highly application dependent. Power saving features are: • Enable the DC-DC converter • Power only the necessary power domains • Enable only the necessary module clocks NOTE: Wake-up time for a power domain in the CC26xx device requires approximately 15 µs.
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Introduction www.ti.com Table 6-6. Example Sequence for Setting CC26xx in Standby Mode (continued) 6.1.5.5 Description Register Required step Set the LF clocks to correct source [DDI_0_OSC:CTL0.SCLK_LF_SRC_SEL] Yes Configure recharge interval [AON_WUC:RECHARGECFG] Yes Configure one or more wake-up sources for MCU [AON_EVENT:MCUWUSEL] Yes Configure power-down clock for MCU [AON_WUC:MCUCLK.PWR_DWN:SRC] No (Default: No clock) Configure power-down clock for AUX [AON_WUC:AUXCLK.
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Introduction www.ti.com 6.1.6 Reset The CC26xx device has several sources of reset, some are triggered due to errors or unexpected behavior, while others is user initiated. Resets may result in reset of: • The entire chip • A power domain • A voltage domain • A single digital module for debug purposes 6.1.6.1 System Resets A reset resulting in a complete power-up sequence and system CPU boot sequence is defined a system reset. The [AON_SYSCTL:RESETCTL.
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PRCM Registers www.ti.com 6.1.6.3 Software-Initiated Reset of MCU_VD A feature to request a reset of MCU_VD is available. When writing the [PRCM:SWRESET.MCU] register, AON_WUC will do a controlled reset sequence of MCU_VD. This reset will also clear the PRCM and other logic in MCU_AON. 6.1.6.4 Reset of the MCU_VD Power Domains and Modules Reset of logic in power domains are hardware controlled. A module without retention is reset when the encapsulating power domain is power cycled.
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PRCM Registers www.ti.com 6.2.1 PRCM Registers Table 6-8 lists the memory-mapped registers for the PRCM. All register offset addresses not listed in Table 6-8 should be considered as reserved locations and the register contents should not be modified. Table 6-8. PRCM Registers Offset Acronym Register Name 0h INFRCLKDIVR Infrastructure Clock Division Factor For Run Mode Section 6.2.1.1 Section 4h INFRCLKDIVS Infrastructure Clock Division Factor For Sleep Mode Section 6.2.1.
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PRCM Registers www.ti.com Table 6-8. PRCM Registers (continued) Offset Acronym Register Name 140h PDSTAT0 Power Domain Status Section 6.2.1.42 144h PDSTAT0RFC RFC Power Domain Status Section 6.2.1.43 148h PDSTAT0SERIAL SERIAL Power Domain Status Section 6.2.1.44 14Ch PDSTAT0PERIPH PERIPH Power Domain Status Section 6.2.1.45 17Ch PDCTL1 Power Domain Control Section 6.2.1.46 184h PDCTL1CPU CPU Power Domain Control Section 6.2.1.
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PRCM Registers 6.2.1.1 www.ti.com INFRCLKDIVR Register (Offset = 0h) [reset = X] INFRCLKDIVR is shown in Figure 6-7 and described in Table 6-9. Infrastructure Clock Division Factor For Run Mode Figure 6-7. INFRCLKDIVR Register 31 30 29 28 27 26 25 24 23 RESERVED R-X 15 14 13 12 11 10 9 8 RESERVED R-X 7 22 21 20 19 18 17 16 6 5 4 3 2 1 0 RATIO R/W-X Table 6-9.
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PRCM Registers www.ti.com 6.2.1.2 INFRCLKDIVS Register (Offset = 4h) [reset = X] INFRCLKDIVS is shown in Figure 6-8 and described in Table 6-10. Infrastructure Clock Division Factor For Sleep Mode Figure 6-8. INFRCLKDIVS Register 31 30 29 28 27 26 25 24 23 RESERVED R-X 15 14 13 12 11 10 9 8 RESERVED R-X 7 22 21 20 19 18 17 16 6 5 4 3 2 1 0 RATIO R/W-X Table 6-10.
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PRCM Registers 6.2.1.3 www.ti.com INFRCLKDIVDS Register (Offset = 8h) [reset = X] INFRCLKDIVDS is shown in Figure 6-9 and described in Table 6-11. Infrastructure Clock Division Factor For DeepSleep Mode Figure 6-9. INFRCLKDIVDS Register 31 30 29 28 27 26 25 24 23 RESERVED R-X 15 14 13 12 11 10 9 8 RESERVED R-X 7 22 21 20 19 18 17 16 6 5 4 3 2 1 0 RATIO R/W-X Table 6-11.
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PRCM Registers www.ti.com 6.2.1.4 VDCTL Register (Offset = Ch) [reset = X] VDCTL is shown in Figure 6-10 and described in Table 6-12. MCU Voltage Domain Control Figure 6-10. VDCTL Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 MCU_VD R/W-X 1 RESERVED R/W-X 0 ULDO R/W-X RESERVED R/W-X 23 22 21 20 RESERVED R/W-X 15 14 13 12 RESERVED R/W-X 7 6 5 RESERVED R/W-X 4 Table 6-12.
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PRCM Registers 6.2.1.5 www.ti.com CLKLOADCTL Register (Offset = 28h) [reset = X] CLKLOADCTL is shown in Figure 6-11 and described in Table 6-13. Clock Load Control Figure 6-11. CLKLOADCTL Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 LOAD_DONE R-1h 0 LOAD W-X RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 4 RESERVED R-X Table 6-13.
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PRCM Registers www.ti.com 6.2.1.6 RFCCLKG Register (Offset = 2Ch) [reset = X] RFCCLKG is shown in Figure 6-12 and described in Table 6-14. RFC Clock Gate Figure 6-12. RFCCLKG Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CLK_EN R/W-1h RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 4 RESERVED R-X Table 6-14.
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PRCM Registers 6.2.1.7 www.ti.com VIMSCLKG Register (Offset = 30h) [reset = X] VIMSCLKG is shown in Figure 6-13 and described in Table 6-15. VIMS Clock Gate Figure 6-13. VIMSCLKG Register 31 30 29 28 27 26 25 24 23 RESERVED R-X 15 14 13 12 11 10 9 8 RESERVED R-X 7 22 21 20 19 18 17 16 6 5 4 3 2 1 0 CLK_EN R/W-3h Table 6-15.
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PRCM Registers www.ti.com 6.2.1.8 SECDMACLKGR Register (Offset = 3Ch) [reset = X] SECDMACLKGR is shown in Figure 6-14 and described in Table 6-16. TRNG, CRYPTO And UDMA Clock Gate For Run Mode Figure 6-14. SECDMACLKGR Register 31 30 29 28 27 26 25 24 19 18 17 16 12 RESERVED R-X 11 10 9 8 DMA_CLK_EN R/W-X 4 3 2 1 TRNG_CLK_E N R/W-X 0 CRYPTO_CLK _EN R/W-X RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 7 6 5 RESERVED R-X Table 6-16.
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PRCM Registers 6.2.1.9 www.ti.com SECDMACLKGS Register (Offset = 40h) [reset = X] SECDMACLKGS is shown in Figure 6-15 and described in Table 6-17. TRNG, CRYPTO And UDMA Clock Gate For Sleep Mode Figure 6-15. SECDMACLKGS Register 31 30 29 28 27 26 25 24 19 18 17 16 12 RESERVED R-X 11 10 9 8 DMA_CLK_EN R/W-X 4 3 2 1 TRNG_CLK_E N R/W-X 0 CRYPTO_CLK _EN R/W-X RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 7 6 5 RESERVED R-X Table 6-17.
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PRCM Registers www.ti.com 6.2.1.10 SECDMACLKGDS Register (Offset = 44h) [reset = X] SECDMACLKGDS is shown in Figure 6-16 and described in Table 6-18. TRNG, CRYPTO And UDMA Clock Gate For Deep Sleep Mode Figure 6-16. SECDMACLKGDS Register 31 30 29 28 27 26 25 24 19 18 17 16 12 RESERVED R-X 11 10 9 8 DMA_CLK_EN R/W-X 4 3 2 1 TRNG_CLK_E N R/W-X 0 CRYPTO_CLK _EN R/W-X RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 7 6 5 RESERVED R-X Table 6-18.
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PRCM Registers www.ti.com 6.2.1.11 GPIOCLKGR Register (Offset = 48h) [reset = X] GPIOCLKGR is shown in Figure 6-17 and described in Table 6-19. GPIO Clock Gate For Run Mode Figure 6-17. GPIOCLKGR Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CLK_EN R/W-X RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 4 RESERVED R-X Table 6-19.
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PRCM Registers www.ti.com 6.2.1.12 GPIOCLKGS Register (Offset = 4Ch) [reset = X] GPIOCLKGS is shown in Figure 6-18 and described in Table 6-20. GPIO Clock Gate For Sleep Mode Figure 6-18. GPIOCLKGS Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CLK_EN R/W-X RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 4 RESERVED R-X Table 6-20.
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PRCM Registers www.ti.com 6.2.1.13 GPIOCLKGDS Register (Offset = 50h) [reset = X] GPIOCLKGDS is shown in Figure 6-19 and described in Table 6-21. GPIO Clock Gate For Deep Sleep Mode Figure 6-19. GPIOCLKGDS Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CLK_EN R/W-X RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 4 RESERVED R-X Table 6-21.
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PRCM Registers www.ti.com 6.2.1.14 GPTCLKGR Register (Offset = 54h) [reset = X] GPTCLKGR is shown in Figure 6-20 and described in Table 6-22. GPT Clock Gate For Run Mode Figure 6-20. GPTCLKGR Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 RESERVED R-X 24 23 RESERVED R-X 8 7 22 21 20 19 18 17 16 6 5 4 3 2 1 CLK_EN R/W-X 0 Table 6-22.
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PRCM Registers www.ti.com 6.2.1.15 GPTCLKGS Register (Offset = 58h) [reset = X] GPTCLKGS is shown in Figure 6-21 and described in Table 6-23. GPT Clock Gate For Sleep Mode Figure 6-21. GPTCLKGS Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 RESERVED R-X 24 23 RESERVED R-X 8 7 22 21 20 19 18 17 16 6 5 4 3 2 1 CLK_EN R/W-X 0 Table 6-23.
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PRCM Registers www.ti.com 6.2.1.16 GPTCLKGDS Register (Offset = 5Ch) [reset = X] GPTCLKGDS is shown in Figure 6-22 and described in Table 6-24. GPT Clock Gate For Deep Sleep Mode Figure 6-22. GPTCLKGDS Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 RESERVED R-X 24 23 RESERVED R-X 8 7 22 21 20 19 18 17 16 6 5 4 3 2 1 CLK_EN R/W-X 0 Table 6-24.
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PRCM Registers www.ti.com 6.2.1.17 I2CCLKGR Register (Offset = 60h) [reset = X] I2CCLKGR is shown in Figure 6-23 and described in Table 6-25. I2C Clock Gate For Run Mode Figure 6-23. I2CCLKGR Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CLK_EN R/W-X RESERVED R/W-X 23 22 21 20 RESERVED R/W-X 15 14 13 12 RESERVED R/W-X 7 6 5 4 RESERVED R/W-X Table 6-25.
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PRCM Registers www.ti.com 6.2.1.18 I2CCLKGS Register (Offset = 64h) [reset = X] I2CCLKGS is shown in Figure 6-24 and described in Table 6-26. I2C Clock Gate For Sleep Mode Figure 6-24. I2CCLKGS Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CLK_EN R/W-X RESERVED R/W-X 23 22 21 20 RESERVED R/W-X 15 14 13 12 RESERVED R/W-X 7 6 5 4 RESERVED R/W-X Table 6-26.
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PRCM Registers www.ti.com 6.2.1.19 I2CCLKGDS Register (Offset = 68h) [reset = X] I2CCLKGDS is shown in Figure 6-25 and described in Table 6-27. I2C Clock Gate For Deep Sleep Mode Figure 6-25. I2CCLKGDS Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CLK_EN R/W-X RESERVED R/W-X 23 22 21 20 RESERVED R/W-X 15 14 13 12 RESERVED R/W-X 7 6 5 4 RESERVED R/W-X Table 6-27.
PAGE 449
PRCM Registers www.ti.com 6.2.1.20 UARTCLKGR Register (Offset = 6Ch) [reset = X] UARTCLKGR is shown in Figure 6-26 and described in Table 6-28. UART Clock Gate For Run Mode Figure 6-26. UARTCLKGR Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CLK_EN R/W-X RESERVED R/W-X 23 22 21 20 RESERVED R/W-X 15 14 13 12 RESERVED R/W-X 7 6 5 4 RESERVED R/W-X Table 6-28.
PAGE 450
PRCM Registers www.ti.com 6.2.1.21 UARTCLKGS Register (Offset = 70h) [reset = X] UARTCLKGS is shown in Figure 6-27 and described in Table 6-29. UART Clock Gate For Sleep Mode Figure 6-27. UARTCLKGS Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CLK_EN R/W-X RESERVED R/W-X 23 22 21 20 RESERVED R/W-X 15 14 13 12 RESERVED R/W-X 7 6 5 4 RESERVED R/W-X Table 6-29.
PAGE 451
PRCM Registers www.ti.com 6.2.1.22 UARTCLKGDS Register (Offset = 74h) [reset = X] UARTCLKGDS is shown in Figure 6-28 and described in Table 6-30. UART Clock Gate For Deep Sleep Mode Figure 6-28. UARTCLKGDS Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CLK_EN R/W-X RESERVED R/W-X 23 22 21 20 RESERVED R/W-X 15 14 13 12 RESERVED R/W-X 7 6 5 4 RESERVED R/W-X Table 6-30.
PAGE 452
PRCM Registers www.ti.com 6.2.1.23 SSICLKGR Register (Offset = 78h) [reset = X] SSICLKGR is shown in Figure 6-29 and described in Table 6-31. SSI Clock Gate For Run Mode Figure 6-29. SSICLKGR Register 31 30 29 28 27 26 25 24 23 RESERVED R-X 15 14 13 12 11 10 9 8 RESERVED R-X 7 22 21 20 19 18 17 16 6 5 4 3 2 1 0 CLK_EN R/W-X Table 6-31.
PAGE 453
PRCM Registers www.ti.com 6.2.1.24 SSICLKGS Register (Offset = 7Ch) [reset = X] SSICLKGS is shown in Figure 6-30 and described in Table 6-32. SSI Clock Gate For Sleep Mode Figure 6-30. SSICLKGS Register 31 30 29 28 27 26 25 24 23 RESERVED R-X 15 14 13 12 11 10 9 8 RESERVED R-X 7 22 21 20 19 18 17 16 6 5 4 3 2 1 0 CLK_EN R/W-X Table 6-32.
PAGE 454
PRCM Registers www.ti.com 6.2.1.25 SSICLKGDS Register (Offset = 80h) [reset = X] SSICLKGDS is shown in Figure 6-31 and described in Table 6-33. SSI Clock Gate For Deep Sleep Mode Figure 6-31. SSICLKGDS Register 31 30 29 28 27 26 25 24 23 RESERVED R-X 15 14 13 12 11 10 9 8 RESERVED R-X 7 22 21 20 19 18 17 16 6 5 4 3 2 1 0 CLK_EN R/W-X Table 6-33.
PAGE 455
PRCM Registers www.ti.com 6.2.1.26 I2SCLKGR Register (Offset = 84h) [reset = X] I2SCLKGR is shown in Figure 6-32 and described in Table 6-34. I2S Clock Gate For Run Mode Figure 6-32. I2SCLKGR Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CLK_EN R/W-X RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 4 RESERVED R-X Table 6-34.
PAGE 456
PRCM Registers www.ti.com 6.2.1.27 I2SCLKGS Register (Offset = 88h) [reset = X] I2SCLKGS is shown in Figure 6-33 and described in Table 6-35. I2S Clock Gate For Sleep Mode Figure 6-33. I2SCLKGS Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CLK_EN R/W-X RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 4 RESERVED R-X Table 6-35.
PAGE 457
PRCM Registers www.ti.com 6.2.1.28 I2SCLKGDS Register (Offset = 8Ch) [reset = X] I2SCLKGDS is shown in Figure 6-34 and described in Table 6-36. I2S Clock Gate For Deep Sleep Mode Figure 6-34. I2SCLKGDS Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CLK_EN R/W-X RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 4 RESERVED R-X Table 6-36.
PAGE 458
PRCM Registers www.ti.com 6.2.1.29 CPUCLKDIV Register (Offset = B8h) [reset = X] CPUCLKDIV is shown in Figure 6-35 and described in Table 6-37. Internal. Only to be used through TI provided API. Figure 6-35. CPUCLKDIV Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RATIO R/W-X RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 4 RESERVED R-X Table 6-37.
PAGE 459
PRCM Registers www.ti.com 6.2.1.30 I2SBCLKSEL Register (Offset = C8h) [reset = X] I2SBCLKSEL is shown in Figure 6-36 and described in Table 6-38. I2S Clock Control Figure 6-36. I2SBCLKSEL Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 SPARE R/W-X 8 SPARE R/W-X 7 22 21 20 19 18 17 16 6 5 4 3 2 1 0 SRC R/W-X Table 6-38. I2SBCLKSEL Register Field Descriptions Bit 31-1 0 Field Type Reset Description SPARE R/W X Software should not rely on the value of a reserved.
PAGE 460
PRCM Registers www.ti.com 6.2.1.31 GPTCLKDIV Register (Offset = CCh) [reset = X] GPTCLKDIV is shown in Figure 6-37 and described in Table 6-39. GPT Scalar Figure 6-37. GPTCLKDIV Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 RESERVED R-X 24 23 RESERVED R-X 8 7 22 21 20 19 18 17 16 6 5 4 3 2 1 0 RATIO R/W-X Table 6-39. GPTCLKDIV Register Field Descriptions Bit 460 Field Type Reset Description 31-4 RESERVED R X Software should not rely on the value of a reserved.
PAGE 461
PRCM Registers www.ti.com 6.2.1.32 I2SCLKCTL Register (Offset = D0h) [reset = X] I2SCLKCTL is shown in Figure 6-38 and described in Table 6-40. I2S Clock Control Figure 6-38. I2SCLKCTL Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 SMPL_ON_PO SEDGE R/W-X 2 1 WCLK_PHASE 0 EN R/W-X R/W-X RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 4 RESERVED R-X Table 6-40.
PAGE 462
PRCM Registers www.ti.com 6.2.1.33 I2SMCLKDIV Register (Offset = D4h) [reset = X] I2SMCLKDIV is shown in Figure 6-39 and described in Table 6-41. MCLK Division Ratio Figure 6-39. I2SMCLKDIV Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 MDIV R/W-X 3 2 1 0 Table 6-41. I2SMCLKDIV Register Field Descriptions Bit 31-10 9-0 462 Field Type Reset Description RESERVED R X Software should not rely on the value of a reserved.
PAGE 463
PRCM Registers www.ti.com 6.2.1.34 I2SBCLKDIV Register (Offset = D8h) [reset = X] I2SBCLKDIV is shown in Figure 6-40 and described in Table 6-42. BCLK Division Ratio Figure 6-40. I2SBCLKDIV Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 BDIV R/W-X 3 2 1 0 Table 6-42. I2SBCLKDIV Register Field Descriptions Bit 31-10 9-0 Field Type Reset Description RESERVED R X Software should not rely on the value of a reserved.
PAGE 464
PRCM Registers www.ti.com 6.2.1.35 I2SWCLKDIV Register (Offset = DCh) [reset = X] I2SWCLKDIV is shown in Figure 6-41 and described in Table 6-43. WCLK Division Ratio Figure 6-41. I2SWCLKDIV Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 WDIV R/W-X 6 5 4 3 2 1 0 Table 6-43. I2SWCLKDIV Register Field Descriptions Bit 464 Field Type Reset Description 31-16 RESERVED R X Software should not rely on the value of a reserved.
PAGE 465
PRCM Registers www.ti.com 6.2.1.36 SWRESET Register (Offset = 10Ch) [reset = X] SWRESET is shown in Figure 6-42 and described in Table 6-44. SW Initiated Resets Figure 6-42. SWRESET Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 MCU W-X 1 RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 RESERVED R-X 4 0 RESERVED W-X Table 6-44.
PAGE 466
PRCM Registers www.ti.com 6.2.1.37 WARMRESET Register (Offset = 110h) [reset = X] WARMRESET is shown in Figure 6-43 and described in Table 6-45. WARM Reset Control And Status Figure 6-43. WARMRESET Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 WR_TO_PINR ESET R/W-X 1 LOCKUP_STA T R-X 0 WDT_STAT RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 RESERVED 4 R-X R-X Table 6-45.
PAGE 467
PRCM Registers www.ti.com 6.2.1.38 PDCTL0 Register (Offset = 12Ch) [reset = X] PDCTL0 is shown in Figure 6-44 and described in Table 6-46. Power Domain Control Figure 6-44. PDCTL0 Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 PERIPH_ON R/W-X 1 SERIAL_ON R/W-X 0 RFC_ON R/W-X RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 RESERVED R-X 4 Table 6-46.
PAGE 468
PRCM Registers www.ti.com 6.2.1.39 PDCTL0RFC Register (Offset = 130h) [reset = X] PDCTL0RFC is shown in Figure 6-45 and described in Table 6-47. RFC Power Domain Control Figure 6-45. PDCTL0RFC Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 RESERVED R-X 8 7 RESERVED R-X 22 21 20 19 18 17 16 6 5 4 3 2 1 0 ON R/W-X Table 6-47.
PAGE 469
PRCM Registers www.ti.com 6.2.1.40 PDCTL0SERIAL Register (Offset = 134h) [reset = X] PDCTL0SERIAL is shown in Figure 6-46 and described in Table 6-48. SERIAL Power Domain Control Figure 6-46. PDCTL0SERIAL Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 RESERVED R-X 8 7 RESERVED R-X 22 21 20 19 18 17 16 6 5 4 3 2 1 0 ON R/W-X Table 6-48.
PAGE 470
PRCM Registers www.ti.com 6.2.1.41 PDCTL0PERIPH Register (Offset = 138h) [reset = X] PDCTL0PERIPH is shown in Figure 6-47 and described in Table 6-49. PERIPH Power Domain Control Figure 6-47. PDCTL0PERIPH Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 RESERVED R-X 8 7 RESERVED R-X 22 21 20 19 18 17 16 6 5 4 3 2 1 0 ON R/W-X Table 6-49.
PAGE 471
PRCM Registers www.ti.com 6.2.1.42 PDSTAT0 Register (Offset = 140h) [reset = X] PDSTAT0 is shown in Figure 6-48 and described in Table 6-50. Power Domain Status Figure 6-48. PDSTAT0 Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 PERIPH_ON R-X 1 SERIAL_ON R-X 0 RFC_ON R-X RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 RESERVED R-X 4 Table 6-50.
PAGE 472
PRCM Registers www.ti.com 6.2.1.43 PDSTAT0RFC Register (Offset = 144h) [reset = X] PDSTAT0RFC is shown in Figure 6-49 and described in Table 6-51. RFC Power Domain Status Figure 6-49. PDSTAT0RFC Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 RESERVED R-X 8 7 RESERVED R-X 22 21 20 19 18 17 16 6 5 4 3 2 1 0 ON R-X Table 6-51.
PAGE 473
PRCM Registers www.ti.com 6.2.1.44 PDSTAT0SERIAL Register (Offset = 148h) [reset = X] PDSTAT0SERIAL is shown in Figure 6-50 and described in Table 6-52. SERIAL Power Domain Status Figure 6-50. PDSTAT0SERIAL Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 RESERVED R-X 8 7 RESERVED R-X 22 21 20 19 18 17 16 6 5 4 3 2 1 0 ON R-X Table 6-52.
PAGE 474
PRCM Registers www.ti.com 6.2.1.45 PDSTAT0PERIPH Register (Offset = 14Ch) [reset = X] PDSTAT0PERIPH is shown in Figure 6-51 and described in Table 6-53. PERIPH Power Domain Status Figure 6-51. PDSTAT0PERIPH Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 RESERVED R-X 8 7 RESERVED R-X 22 21 20 19 18 17 16 6 5 4 3 2 1 0 ON R-X Table 6-53.
PAGE 475
PRCM Registers www.ti.com 6.2.1.46 PDCTL1 Register (Offset = 17Ch) [reset = X] PDCTL1 is shown in Figure 6-52 and described in Table 6-54. Power Domain Control Figure 6-52. PDCTL1 Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 VIMS_MODE R/W-1h 2 RFC_ON R/W-X 1 CPU_ON R/W-1h 0 RESERVED R-X RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 RESERVED R-X 5 4 RESERVED R/W-X Table 6-54.
PAGE 476
PRCM Registers www.ti.com 6.2.1.47 PDCTL1CPU Register (Offset = 184h) [reset = X] PDCTL1CPU is shown in Figure 6-53 and described in Table 6-55. CPU Power Domain Control Figure 6-53. PDCTL1CPU Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 RESERVED R-X 8 7 RESERVED R-X 22 21 20 19 18 17 16 6 5 4 3 2 1 0 ON R/W1h Table 6-55.
PAGE 477
PRCM Registers www.ti.com 6.2.1.48 PDCTL1RFC Register (Offset = 188h) [reset = X] PDCTL1RFC is shown in Figure 6-54 and described in Table 6-56. RFC Power Domain Control Figure 6-54. PDCTL1RFC Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 RESERVED R-X 8 7 RESERVED R-X 22 21 20 19 18 17 16 6 5 4 3 2 1 0 ON R/W-X Table 6-56.
PAGE 478
PRCM Registers www.ti.com 6.2.1.49 PDCTL1VIMS Register (Offset = 18Ch) [reset = X] PDCTL1VIMS is shown in Figure 6-55 and described in Table 6-57. VIMS Power Domain Control Figure 6-55. PDCTL1VIMS Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 RESERVED R-X 8 7 RESERVED R-X 22 21 20 19 18 17 16 6 5 4 3 2 1 0 ON R/W1h Table 6-57.
PAGE 479
PRCM Registers www.ti.com 6.2.1.50 PDSTAT1 Register (Offset = 194h) [reset = X] PDSTAT1 is shown in Figure 6-56 and described in Table 6-58. Power Domain Status Figure 6-56. PDSTAT1 Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 VIMS_MODE R-1h 2 RFC_ON R-X 1 CPU_ON R-1h 0 RESERVED R-X RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 RESERVED R-X 5 4 BUS_ON R-1h Table 6-58.
PAGE 480
PRCM Registers www.ti.com 6.2.1.51 PDSTAT1BUS Register (Offset = 198h) [reset = X] PDSTAT1BUS is shown in Figure 6-57 and described in Table 6-59. BUS Power Domain Status Figure 6-57. PDSTAT1BUS Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 RESERVED R-X 8 7 RESERVED R-X 22 21 20 19 18 17 16 6 5 4 3 2 1 0 ON R-1h Table 6-59.
PAGE 481
PRCM Registers www.ti.com 6.2.1.52 PDSTAT1RFC Register (Offset = 19Ch) [reset = X] PDSTAT1RFC is shown in Figure 6-58 and described in Table 6-60. RFC Power Domain Status Figure 6-58. PDSTAT1RFC Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 RESERVED R-X 8 7 RESERVED R-X 22 21 20 19 18 17 16 6 5 4 3 2 1 0 ON R-X Table 6-60.
PAGE 482
PRCM Registers www.ti.com 6.2.1.53 PDSTAT1CPU Register (Offset = 1A0h) [reset = X] PDSTAT1CPU is shown in Figure 6-59 and described in Table 6-61. CPU Power Domain Status Figure 6-59. PDSTAT1CPU Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 RESERVED R-X 8 7 RESERVED R-X 22 21 20 19 18 17 16 6 5 4 3 2 1 0 ON R-1h Table 6-61.
PAGE 483
PRCM Registers www.ti.com 6.2.1.54 PDSTAT1VIMS Register (Offset = 1A4h) [reset = X] PDSTAT1VIMS is shown in Figure 6-60 and described in Table 6-62. VIMS Power Domain Status Figure 6-60. PDSTAT1VIMS Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 RESERVED R-X 8 7 RESERVED R-X 22 21 20 19 18 17 16 6 5 4 3 2 1 0 ON R-1h Table 6-62.
PAGE 484
PRCM Registers www.ti.com 6.2.1.55 RFCMODESEL Register (Offset = 1D0h) [reset = X] RFCMODESEL is shown in Figure 6-61 and described in Table 6-63. Selected RFC Mode Figure 6-61. RFCMODESEL Register 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 RESERVED R-X 9 8 RESERVED R-X 7 22 21 20 19 18 17 16 6 5 4 3 2 1 CURR R/W-X 0 Table 6-63.
PAGE 485
PRCM Registers www.ti.com 6.2.1.56 RAMRETEN Register (Offset = 224h) [reset = X] RAMRETEN is shown in Figure 6-62 and described in Table 6-64. Memory Retention Control Figure 6-62. RAMRETEN Register 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 RESERVED R-X 9 8 RESERVED R-X 7 22 21 20 19 18 17 16 6 5 4 3 2 RFC R/W-X 1 0 VIMS R/W-3h Table 6-64.
PAGE 486
PRCM Registers www.ti.com 6.2.1.57 RAMHWOPT Register (Offset = 250h) [reset = X] RAMHWOPT is shown in Figure 6-63 and described in Table 6-65. CONFIG SIZE For SRAM Figure 6-63. RAMHWOPT Register 31 30 29 28 27 26 25 24 23 RESERVED R-X 15 14 13 12 11 10 9 8 RESERVED R-X 7 22 21 20 19 18 17 6 5 4 3 2 1 16 0 SIZE R-3h Table 6-65.
PAGE 487
PRCM Registers www.ti.
PAGE 488
PRCM Registers www.ti.com 6.2.2 AON_SYSCTL Registers Table 6-66 lists the memory-mapped registers for the AON_SYSCTL. All register offset addresses not listed in Table 6-66 should be considered as reserved locations and the register contents should not be modified. Table 6-66. AON_SYSCTL Registers 488 Offset Acronym Register Name 0h PWRCTL Power Management Section 6.2.2.1 4h RESETCTL Reset Management Section 6.2.2.2 8h SLEEPCTL Sleep Mode Section 6.2.2.
PAGE 489
PRCM Registers www.ti.com 6.2.2.1 PWRCTL Register (Offset = 0h) [reset = X] PWRCTL is shown in Figure 6-64 and described in Table 6-67. Power Management This register controls bitfields for setting low level power management features such as selection of regulator for VDDR supply and control of IO ring where certain segments can be enabled / disabled. Figure 6-64.
PAGE 490
PRCM Registers 6.2.2.2 www.ti.com RESETCTL Register (Offset = 4h) [reset = X] RESETCTL is shown in Figure 6-65 and described in Table 6-68. Reset Management This register contains bitfields releated to system reset such as reset source and reset request and control of brown out resets. Figure 6-65.
PAGE 491
PRCM Registers www.ti.com Table 6-68.
PAGE 492
PRCM Registers 6.2.2.3 www.ti.com SLEEPCTL Register (Offset = 8h) [reset = X] SLEEPCTL is shown in Figure 6-66 and described in Table 6-69. Sleep Mode This register is used to unfreeze the IO pad ring after waking up from SHUTDOWN Figure 6-66. SLEEPCTL Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 IO_PAD_SLEE P_DIS R/W-X RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 4 RESERVED R-X Table 6-69.
PAGE 493
PRCM Registers www.ti.com 6.2.3 AON_WUC Registers Table 17-56 lists the memory-mapped registers for the AON_WUC. All register offset addresses not listed in Table 17-56 should be considered as reserved locations and the register contents should not be modified. Table 6-70. AON_WUC Registers Offset Acronym Register Name Section 0h MCUCLK MCU Clock Management Section 17.8.4.1 4h AUXCLK AUX Clock Management Section 17.8.4.2 8h MCUCFG MCU Configuration Section 17.8.4.
PAGE 494
PRCM Registers 6.2.3.1 www.ti.com MCUCLK Register (Offset = 0h) [reset = X] MCUCLK is shown in Figure 17-36 and described in Table 17-57. MCU Clock Management This register contains bitfields related to the MCU clock. Figure 6-67. MCUCLK Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 RCOSC_HF_C AL_DONE R/W-X RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 RESERVED 4 R-X 1 0 PWR_DWN_SRC R/W-X Table 6-71.
PAGE 495
PRCM Registers www.ti.com 6.2.3.2 AUXCLK Register (Offset = 4h) [reset = X] AUXCLK is shown in Figure 17-37 and described in Table 17-58. AUX Clock Management This register contains bitfields that are relevant for setting up the clock to the AUX domain. Figure 6-68.
PAGE 496
PRCM Registers 6.2.3.3 www.ti.com MCUCFG Register (Offset = 8h) [reset = X] MCUCFG is shown in Figure 17-38 and described in Table 17-59. MCU Configuration This register contains power management related bitfields for the MCU domain. Figure 6-69. MCUCFG Register 31 30 29 28 27 26 25 24 19 18 17 VIRT_OFF R/W-X 16 FIXED_WU_EN R/W-X 11 10 9 8 3 2 1 SRAM_RET_EN R/W-Fh 0 RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 4 RESERVED R-X Table 6-73.
PAGE 497
PRCM Registers www.ti.com 6.2.3.4 AUXCFG Register (Offset = Ch) [reset = X] AUXCFG is shown in Figure 17-39 and described in Table 17-60. AUX Configuration This register contains power management related signals for the AUX domain. Figure 6-70. AUXCFG Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RAM_RET_EN R/W-1h RESERVED R/W-X 23 22 21 20 RESERVED R/W-X 15 14 13 12 RESERVED R/W-X 7 6 5 4 RESERVED R/W-X Table 6-74.
PAGE 498
PRCM Registers 6.2.3.5 www.ti.com AUXCTL Register (Offset = 10h) [reset = X] AUXCTL is shown in Figure 17-40 and described in Table 17-61. AUX Control This register contains events and control signals for the AUX domain. Figure 6-71. AUXCTL Register 31 RESET_REQ R/W-X 30 29 28 23 22 21 20 27 RESERVED R-X 26 25 24 19 18 17 16 11 10 9 8 3 2 SCE_RUN_EN 1 SWEV R/W-X R/W-X 0 AUX_FORCE_ ON R/W-X RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 RESERVED 4 R-X Table 6-75.
PAGE 499
PRCM Registers www.ti.com 6.2.3.6 PWRSTAT Register (Offset = 14h) [reset = X] PWRSTAT is shown in Figure 17-41 and described in Table 17-62. Power Status This register is used to monitor various power management related signals in AON. Most signals are for test, calibration and debug purpose only, and others can be used to detect that AUX or JTAG domains are powered up. Figure 6-72.
PAGE 500
PRCM Registers 6.2.3.7 www.ti.com SHUTDOWN Register (Offset = 18h) [reset = X] SHUTDOWN is shown in Figure 17-42 and described in Table 17-63. Shutdown Control This register contains bitfields required for entering shutdown mode Figure 6-73. SHUTDOWN Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 RESERVED R/W-X 8 7 RESERVED R/W-X 22 21 20 19 18 17 16 6 5 4 3 2 1 0 EN R/W-X Table 6-77.
PAGE 501
PRCM Registers www.ti.com 6.2.3.8 CTL0 Register (Offset = 20h) [reset = X] CTL0 is shown in Figure 17-43 and described in Table 17-64. Control 0 This register contains various chip level control and debug bitfields. Figure 6-74. CTL0 Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 PWR_DWN_DI S R/W-X 3 AUX_SRAM_E RASE W-X 2 MCU_SRAM_E RASE W-X 1 RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 4 RESERVED R/W-X 0 RESERVED R-X Table 6-78.
PAGE 502
PRCM Registers 6.2.3.9 www.ti.com CTL1 Register (Offset = 24h) [reset = X] CTL1 is shown in Figure 17-44 and described in Table 17-65. Control 1 This register contains various chip level control and debug bitfields. Figure 6-75. CTL1 Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 MCU_RESET_ SRC R/W1C-X 0 MCU_WARM_ RESET R/W1C-X RESERVED R/W-X 23 22 21 20 RESERVED R/W-X 15 14 13 12 RESERVED R/W-X 7 6 5 4 RESERVED R/W-X Table 6-79.
PAGE 503
PRCM Registers www.ti.com 6.2.3.10 RECHARGECFG Register (Offset = 30h) [reset = X] RECHARGECFG is shown in Figure 17-45 and described in Table 17-66. Recharge Controller Configuration This register sets all relevant patameters for controlling the recharge algorithm. Figure 6-76.
PAGE 504
PRCM Registers www.ti.com Table 6-80. RECHARGECFG Register Field Descriptions (continued) 504 Bit Field Type Reset Description 2-0 PER_E R/W X Number of 32 KHz clocks between activation of recharge controller For recharge algorithm, PERIOD is the initial period when entering powerdown mode. The adaptive recharge algorithm will not change this register PERIOD will effectively be a 16 bit value coded in a 5 bit mantissa and 3 bit exponent: This field sets the Exponent of the Period.
PAGE 505
PRCM Registers www.ti.com 6.2.3.11 RECHARGESTAT Register (Offset = 34h) [reset = X] RECHARGESTAT is shown in Figure 17-46 and described in Table 17-67. Recharge Controller Status This register controls various status registers which are updated during recharge. The register is mostly intended for test and debug. Figure 6-77.
PAGE 506
PRCM Registers www.ti.com 6.2.3.12 OSCCFG Register (Offset = 38h) [reset = X] OSCCFG is shown in Figure 17-47 and described in Table 17-68. Oscillator Configuration This register sets the period for Amplitude compensation requests sent to the oscillator control system. The amplitude compensations is only applicable when XOSC_HF is running in low power mode. Figure 6-78.
PAGE 507
PRCM Registers www.ti.com 6.2.3.13 JTAGCFG Register (Offset = 40h) [reset = X] JTAGCFG is shown in Figure 17-48 and described in Table 17-69. JTAG Configuration This register contains control for configuration of the JTAG domain,- hereunder access permissions for each TAP. Figure 6-79.
PAGE 508
PRCM Registers www.ti.com 6.2.3.14 JTAGUSERCODE Register (Offset = 44h) [reset = B99A02Fh] JTAGUSERCODE is shown in Figure 17-49 and described in Table 17-70. JTAG USERCODE Boot code copies the JTAG USERCODE to this register from where it is forwarded to the debug subsystem. Figure 6-80. JTAGUSERCODE Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 USER_CODE R/W-B99A02Fh 9 8 7 6 5 4 3 2 1 0 Table 6-84.
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PRCM Registers www.ti.com 6.2.4 DDI_0_OSC Registers Table 6-85 lists the memory-mapped registers for the DDI_0_OSC. All register offset addresses not listed in Table 6-85 should be considered as reserved locations and the register contents should not be modified. Table 6-85. DDI_0_OSC Registers Offset Acronym Register Name Section 0h CTL0 Control 0 Section 6.2.4.1 4h CTL1 Control 1 Section 6.2.4.2 8h RADCEXTCFG RADC External Configuration Section 6.2.4.
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PRCM Registers 6.2.4.1 www.ti.com CTL0 Register (Offset = 0h) [reset = X] CTL0 is shown in Figure 6-81 and described in Table 6-86. Control 0 Controls various clock source selects Figure 6-81.
PAGE 511
PRCM Registers www.ti.com Table 6-86. CTL0 Register Field Descriptions (continued) Bit Field Type Reset Description RESERVED R/W X Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 12 RCOSC_LF_TRIMMED R/W X Internal. Only to be used through TI provided API. 11 XOSC_HF_POWER_MO DE R/W X Internal. Only to be used through TI provided API.
PAGE 512
PRCM Registers 6.2.4.2 www.ti.com CTL1 Register (Offset = 4h) [reset = X] CTL1 is shown in Figure 6-82 and described in Table 6-87. Control 1 This register contains various OSC_DIG configuration Figure 6-82. CTL1 Register 31 30 29 28 27 26 25 24 19 18 17 RCOSCHFCTR IMFRACT_EN R/W-X 16 SPARE2 11 10 9 8 3 2 RESERVED R/W-X 23 RESERVED 22 21 14 13 20 RCOSCHFCTRIMFRACT R/W-X R/W-X 15 12 R/W-X SPARE2 R/W-X 7 6 5 4 SPARE2 R/W-X 1 0 XOSC_HF_FAST_START R/W-X Table 6-87.
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PRCM Registers www.ti.com 6.2.4.3 RADCEXTCFG Register (Offset = 8h) [reset = X] RADCEXTCFG is shown in Figure 6-83 and described in Table 6-88. RADC External Configuration Figure 6-83. RADCEXTCFG Register 31 30 29 23 22 HPM_IBIAS_WAIT_CNT R/W-X 15 28 27 HPM_IBIAS_WAIT_CNT R/W-X 21 20 13 12 11 5 RADC_MODE_ IS_SAR R/W-X 4 3 14 26 R/W-X 24 17 16 10 9 RADC_DAC_TH R/W-X 8 19 18 LPM_IBIAS_WAIT_CNT R/W-X IDAC_STEP R/W-X 7 6 RADC_DAC_TH 25 2 RESERVED 1 0 R/W-X Table 6-88.
PAGE 514
PRCM Registers 6.2.4.4 www.ti.com AMPCOMPCTL Register (Offset = Ch) [reset = X] AMPCOMPCTL is shown in Figure 6-84 and described in Table 6-89. Amplitude Compensation Control Figure 6-84.
PAGE 515
PRCM Registers www.ti.com 6.2.4.5 AMPCOMPTH1 Register (Offset = 10h) [reset = X] AMPCOMPTH1 is shown in Figure 6-85 and described in Table 6-90. Amplitude Compensation Threashold 1 This register contains various threshhold values for amplitude compensation algorithm Figure 6-85.
PAGE 516
PRCM Registers 6.2.4.6 www.ti.com AMPCOMPTH2 Register (Offset = 14h) [reset = X] AMPCOMPTH2 is shown in Figure 6-86 and described in Table 6-91. Amplitude Compensation Threashold 2 This register contains various threshhold values for amplitude compensation algorithm. Figure 6-86.
PAGE 517
PRCM Registers www.ti.com 6.2.4.7 ANABYPASSVAL1 Register (Offset = 18h) [reset = X] ANABYPASSVAL1 is shown in Figure 6-87 and described in Table 6-92. Analog Bypass Values 1 Figure 6-87. ANABYPASSVAL1 Register 31 30 29 28 27 26 25 24 RESERVED R/W-X 23 22 21 20 19 RESERVED R/W-X 18 17 XOSC_HF_ROW_Q12 R/W-X 16 15 14 13 12 11 XOSC_HF_COLUMN_Q12 R/W-X 10 9 8 7 6 5 4 3 XOSC_HF_COLUMN_Q12 R/W-X 2 1 0 Table 6-92.
PAGE 518
PRCM Registers 6.2.4.8 www.ti.com ANABYPASSVAL2 Register (Offset = 1Ch) [reset = X] ANABYPASSVAL2 is shown in Figure 6-88 and described in Table 6-93. Internal. Only to be used through TI provided API. Figure 6-88. ANABYPASSVAL2 Register 31 30 29 28 27 26 25 15 14 RESERVED R/W-X 13 12 11 10 9 24 23 RESERVED R/W-X 22 21 20 19 18 17 16 8 7 6 5 XOSC_HF_IBIASTHERM R/W-X 4 3 2 1 0 Table 6-93.
PAGE 519
PRCM Registers www.ti.com 6.2.4.9 ATESTCTL Register (Offset = 20h) [reset = X] ATESTCTL is shown in Figure 6-89 and described in Table 6-94. Analog Test Control Figure 6-89. ATESTCTL Register 31 30 SPARE30 R/W-X 23 22 29 SCLK_LF_AUX _EN R/W-X 28 21 20 27 26 RESERVED 25 24 R/W-X 19 18 17 16 11 10 9 8 3 2 1 0 RESERVED R/W-X 15 14 13 12 RESERVED R/W-X 7 6 5 4 RESERVED R/W-X Table 6-94.
PAGE 520
PRCM Registers www.ti.com 6.2.4.10 ADCDOUBLERNANOAMPCTL Register (Offset = 24h) [reset = X] ADCDOUBLERNANOAMPCTL is shown in Figure 6-90 and described in Table 6-95. ADC Doubler Nanoamp Control Figure 6-90.
PAGE 521
PRCM Registers www.ti.com 6.2.4.11 XOSCHFCTL Register (Offset = 28h) [reset = X] XOSCHFCTL is shown in Figure 6-91 and described in Table 6-96. XOSCHF Control Figure 6-91. XOSCHFCTL Register 31 30 29 28 27 26 25 24 19 18 17 16 12 11 10 9 8 PEAK_DET_ITRIM R/W-X 4 3 HP_BUF_ITRIM R/W-X 2 1 RESERVED R/W-X 23 22 21 20 RESERVED R/W-X 15 14 13 RESERVED R/W-X 7 RESERVED R/W-X 6 BYPASS R/W-X 5 RESERVED R/W-X 0 LP_BUF_ITRIM R/W-X Table 6-96.
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PRCM Registers www.ti.com 6.2.4.12 LFOSCCTL Register (Offset = 2Ch) [reset = X] LFOSCCTL is shown in Figure 6-92 and described in Table 6-97. Low Frequency Oscillator Control Figure 6-92. LFOSCCTL Register 31 30 29 28 27 26 25 18 17 24 RESERVED R/W-X 23 22 XOSCLF_REGULATOR_TRIM R/W-X 15 14 21 20 19 XOSCLF_CMIRRWR_RATIO R/W-X 13 12 11 10 RESERVED R/W-X 7 6 5 16 RESERVED R/W-X 4 3 RCOSCLF_CTUNE_TRIM R/W-X 2 9 8 RCOSCLF_RTUNE_TRIM R/W-X 1 0 Table 6-97.
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PRCM Registers www.ti.com 6.2.4.13 RCOSCHFCTL Register (Offset = 30h) [reset = X] RCOSCHFCTL is shown in Figure 6-93 and described in Table 6-98. RCOSCHF Control Figure 6-93. RCOSCHFCTL Register 31 30 29 15 14 13 28 27 12 11 RCOSCHF_CTRIM R/W-X 26 25 10 9 24 23 RESERVED R/W-X 8 7 22 21 20 19 18 17 16 6 5 4 3 RESERVED R/W-X 2 1 0 Table 6-98.
PAGE 524
PRCM Registers www.ti.com 6.2.4.14 STAT0 Register (Offset = 34h) [reset = X] STAT0 is shown in Figure 6-94 and described in Table 6-99. Status 0 This register contains status signals from OSC_DIG Figure 6-94.
PAGE 525
PRCM Registers www.ti.com Table 6-99. STAT0 Register Field Descriptions (continued) Bit Field Type Reset Description 12 RESERVED R X Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 11 XOSC_HF_LP_BUF_EN R X XOSC_HF_LP_BUF_EN 10 XOSC_HF_HP_BUF_EN R X XOSC_HF_HP_BUF_EN 9 RESERVED R X Software should not rely on the value of a reserved.
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PRCM Registers www.ti.com 6.2.4.15 STAT1 Register (Offset = 38h) [reset = X] STAT1 is shown in Figure 6-95 and described in Table 6-100. Status 1 This register contains status signals from OSC_DIG Figure 6-95.
PAGE 527
PRCM Registers www.ti.com Table 6-100.
PAGE 528
PRCM Registers www.ti.com 6.2.4.16 STAT2 Register (Offset = 3Ch) [reset = X] STAT2 is shown in Figure 6-96 and described in Table 6-101. Status 2 This register contains status signals from AMPCOMP FSM Figure 6-96.
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Chapter 7 SWCU117A – February 2015 – Revised March 2015 Versatile Instruction Memory System (VIMS) The main instruction memories are encapsulated in a Versatile Instruction Memory System (VIMS) module, which includes the following memories: • 128-kB FLASH • 8-kB RAM Cache or general purpose RAM (GPRAM) • 115-kB Boot ROM An overview of the VIMS module is shown in Figure 7-1. Figure 7-1.
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www.ti.com 530 Topic ........................................................................................................................... 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 VIMS Configurations ......................................................................................... VIMS Software (SW) Remarks ............................................................................ VIMS Registers .................................................................................................
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VIMS Configurations www.ti.com 7.1 VIMS Configurations 7.1.1 VIMS Modes The VIMS cache RAM block and the Cache block can operate in the following modes: • GPRAM • CACHE • OFF The current mode is shown in VIMS.STAT.*, and mode switching is controlled through VIMS.CTL.MODE. The mode transitions are shown in Figure 7-2. Lines in black are software initiated changes through CTL.MODE. Lines in brown are hardware initiated changes. The invalidating state is a transition state controlled by hardware.
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VIMS Configurations www.ti.com Figure 7-3. VIMS Module in GPRAM Mode GPRAM address space icode/dcode icode/dcode GP-RAM SYSCODE and USERCODE address space FLASH sysbus sysbus rom BROM address space 7.1.1.2 Off Mode In off mode, the RAM block is disabled and cannot be accessed by the CPU or by the system bus. The Flash block has no cache support, and all accesses to the flash are routed directly to the Flash block. Figure 7-4.
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VIMS Configurations www.ti.com Figure 7-5. VIMS Module in Cache Mode SYSCODE address space icode/dcode CACHE USERCODE address space FLASH USERCODE and SYSCODE address space sysbus rom BROM address space In cache mode, all CPU accesses to the flash SYSCODE address space are directed to the cache first. The cache looks up the input address in the internal tag RAM to determine whether the access is a cache hit or a cache miss. In the case of a cache miss, the access is forwarded to the Flash block.
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VIMS Configurations www.ti.com 7.1.2 VIMS Flash Line Buffering The VIMS module contains two flash line buffers because the flash word size is 64 bits. • A line buffer is placed in the flash CPU bus path that is controlled by the [VIMS.CTL.IDCODE_LB_DIS] register. • A line buffer is placed in the flash system bus path that is controlled by the [VIMS.CTL.SYSBUS_LB_DIS] register.
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VIMS Software (SW) Remarks www.ti.com Table 7-1. Valid Retention Combination for VIMS Memory Mode 7.2.2.1 Retention Enabled Comment TAG-RAM CACHE-RAM VIMS Logic 1 No No Yes SW must compensate for loss of data in RAMs. 2 No Yes Yes Will work in GPRAM mode, without SW intervention 3 Yes Yes Yes Mode 1 Mode 1 is intended for use when the system is in off mode, cache mode.
PAGE 536
VIMS Software (SW) Remarks www.ti.com Figure 7-8.
PAGE 537
VIMS Registers www.ti.com 7.3 VIMS Registers Table 7-2 lists the memory-mapped registers for the VIMS. All register offset addresses not listed in Table 7-2 should be considered as reserved locations and the register contents should not be modified. Table 7-2. VIMS Registers Offset Acronym Register Name 0h STAT Status Section 7.3.1 4h CTL Control Section 7.3.
PAGE 538
VIMS Registers www.ti.com 7.3.1 STAT Register (Offset = 0h) [reset = X] STAT is shown in Figure 7-9 and described in Table 7-3. Status Displays current VIMS mode and line buffer status Figure 7-9. STAT Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 MODE_CHAN GING R-X 2 INV 1 RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 RESERVED R-X 5 4 IDCODE_LB_D SYSBUS_LB_D IS IS R-X R-X R-X 0 MODE R-X Table 7-3.
PAGE 539
VIMS Registers www.ti.com 7.3.2 CTL Register (Offset = 4h) [reset = X] CTL is shown in Figure 7-10 and described in Table 7-4. Control Configure VIMS mode and line buffer settings Figure 7-10.
PAGE 540
ROM 7.4 www.ti.com ROM The ROM contains a serial bootloader with SPI and UART support (see Chapter 8, Bootloader chapter), as well as Driver Library and RF stack support. See , Memory Map chapter for details. 7.5 EEFUSE TBD 7.6 FLASH The flash memory is organized as a set of 4-KB blocks that can be individually erased. An individual 32-bit word can be programmed to change bits from 1 to 0.
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FLASH www.ti.com 7.6.2.1 Disabling Debug Access TBD 7.6.3 FLASH Memory Programming During a flash memory write or erase operation, the Flash memory must not be read. If instruction execution is required during a flash memory operation, the executing code must be placed in SRAM (and executed from SRAM) while the flash operation is in progress. 7.6.4 FLASH Read Timings TBD 7.6.5 Power Mode Operations TBD 7.
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VIMS Registers www.ti.com 7.7.1 FLASHMEM Registers Table 7-6 lists the memory-mapped registers for the FLASHMEM. All register offset addresses not listed in Table 7-6 should be considered as reserved locations and the register contents should not be modified. Table 7-6.
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VIMS Registers www.ti.com 7.7.2 FLASH Registers Table 7-7 lists the memory-mapped registers for the FLASH. All register offset addresses not listed in Table 7-7 should be considered as reserved locations and the register contents should not be modified. Table 7-7. FLASH Registers Offset Acronym Register Name 1Ch STAT FMC and Efuse Status Section 7.7.2.1 Section 24h CFG Configuration Section 7.7.2.2 28h SYSCODE_START Syscode Start Address Offset Configuration Section 7.7.2.
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VIMS Registers www.ti.com Table 7-7. FLASH Registers (continued) Offset Acronym Register Name 208Ch FVHVCT3 FMC VHVCT3 Trim Section 7.7.2.45 Section 2090h FVNVCT FMC VNVCT Trim Section 7.7.2.46 2094h FVSLP FMC VSL_P Trim Section 7.7.2.47 2098h FVWLCT FMC VWLCT Trim Section 7.7.2.48 209Ch FEFUSECTL FMC EFUSE Control Section 7.7.2.49 20A0h FEFUSESTAT FMC EFUSE Status Section 7.7.2.50 20A4h FEFUSEDATA FMC EFUSE Data Section 7.7.2.
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VIMS Registers www.ti.com Table 7-7. FLASH Registers (continued) Offset Acronym Register Name 2270h FSM_STEP_SIZE FMC FSM EC Step Size Section 7.7.2.92 Section 2274h FSM_PUL_CNTR FMC FSM Pulse Counter Section 7.7.2.93 2278h FSM_EC_STEP_HEIGHT FMC FSM EC Step Height Section 7.7.2.94 227Ch FSM_ST_MACHINE FMC FSM_ST_MACHINE Section 7.7.2.95 2280h FSM_FLES FMC FLES Memory Control Bits Section 7.7.2.96 2288h FSM_WR_ENA FMC FSM Register Write Enable Section 7.7.2.
PAGE 546
VIMS Registers 7.7.2.1 www.ti.com STAT Register (Offset = 1Ch) [reset = X] STAT is shown in Figure 7-11 and described in Table 7-8. FMC and Efuse Status Figure 7-11. STAT Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 EFUSE_ERRCODE 9 8 1 BUSY 0 POWER_MOD E R-X RESERVED R-X 23 22 21 20 RESERVED R-X 15 EFUSE_BLAN K R-X 14 EFUSE_TIMEO UT R-X 13 EFUSE_CRC_ ERROR R-X 12 7 6 5 RESERVED 4 R-X 3 R-X 2 SAMHOLD_DI S R-X R-X Table 7-8.
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VIMS Registers www.ti.com 7.7.2.2 CFG Register (Offset = 24h) [reset = X] CFG is shown in Figure 7-12 and described in Table 7-9. Internal. Only to be used through TI provided API. Figure 7-12.
PAGE 548
VIMS Registers 7.7.2.3 www.ti.com SYSCODE_START Register (Offset = 28h) [reset = X] SYSCODE_START is shown in Figure 7-13 and described in Table 7-10. Internal. Only to be used through TI provided API. Figure 7-13. SYSCODE_START Register 31 30 29 28 27 15 14 13 12 11 26 25 10 9 RESERVED R-X 24 23 RESERVED R-X 8 7 22 21 20 19 18 17 16 6 5 4 3 2 1 SYSCODE_START R/W-X 0 Table 7-10.
PAGE 549
VIMS Registers www.ti.com 7.7.2.4 FLASH_SIZE Register (Offset = 2Ch) [reset = X] FLASH_SIZE is shown in Figure 7-14 and described in Table 7-11. Internal. Only to be used through TI provided API. Figure 7-14. FLASH_SIZE Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 SECTORS R/W-X 1 0 Table 7-11. FLASH_SIZE Register Field Descriptions Field Type Reset Description 31-8 Bit RESERVED R X Internal.
PAGE 550
VIMS Registers 7.7.2.5 www.ti.com FWLOCK Register (Offset = 3Ch) [reset = X] FWLOCK is shown in Figure 7-15 and described in Table 7-12. Internal. Only to be used through TI provided API. Figure 7-15. FWLOCK Register 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 RESERVED R-X 9 8 RESERVED R-X 7 22 21 20 19 18 17 16 6 5 4 3 2 1 FWLOCK R/W-X 0 Table 7-12. FWLOCK Register Field Descriptions Bit 550 Field Type Reset Description 31-3 RESERVED R X Internal.
PAGE 551
VIMS Registers www.ti.com 7.7.2.6 FWFLAG Register (Offset = 40h) [reset = X] FWFLAG is shown in Figure 7-16 and described in Table 7-13. Internal. Only to be used through TI provided API. Figure 7-16. FWFLAG Register 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 RESERVED R-X 9 8 RESERVED R-X 7 22 21 20 19 18 17 16 6 5 4 3 2 1 FWFLAG R/W-X 0 Table 7-13. FWFLAG Register Field Descriptions Field Type Reset Description 31-3 Bit RESERVED R X Internal.
PAGE 552
VIMS Registers 7.7.2.7 www.ti.com EFUSE Register (Offset = 1000h) [reset = X] EFUSE is shown in Figure 7-17 and described in Table 7-14. Internal. Only to be used through TI provided API. Figure 7-17. EFUSE Register 31 30 29 RESERVED R-X 15 14 13 28 27 26 25 INSTRUCTION R/W-X 12 11 10 9 24 23 8 7 DUMPWORD R/W-X 22 21 6 5 20 19 RESERVED R-X 4 3 18 17 16 2 1 0 Table 7-14. EFUSE Register Field Descriptions Bit 552 Field Type Reset Description 31-29 RESERVED R X Internal.
PAGE 553
VIMS Registers www.ti.com 7.7.2.8 EFUSEADDR Register (Offset = 1004h) [reset = X] EFUSEADDR is shown in Figure 7-18 and described in Table 7-15. Internal. Only to be used through TI provided API. Figure 7-18. EFUSEADDR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED BLOCK R-X R/W-X 9 8 7 6 5 4 ROW R/W-X 3 2 1 0 Table 7-15. EFUSEADDR Register Field Descriptions Field Type Reset Description 31-16 Bit RESERVED R X Internal.
PAGE 554
VIMS Registers 7.7.2.9 www.ti.com DATAUPPER Register (Offset = 1008h) [reset = X] DATAUPPER is shown in Figure 7-19 and described in Table 7-16. Internal. Only to be used through TI provided API. Figure 7-19. DATAUPPER Register 31 30 29 28 27 26 25 15 14 13 12 11 RESERVED R-X 10 9 24 23 RESERVED R-X 8 7 22 21 20 19 6 5 SPARE R/W-X 4 3 18 17 16 2 1 0 P R EEN R/W-X R/W-X R/W-X Table 7-16.
PAGE 555
VIMS Registers www.ti.com 7.7.2.10 DATALOWER Register (Offset = 100Ch) [reset = X] DATALOWER is shown in Figure 7-20 and described in Table 7-17. Internal. Only to be used through TI provided API. Figure 7-20. DATALOWER Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DATA R/W-X 9 8 7 6 5 4 3 2 1 0 Table 7-17. DATALOWER Register Field Descriptions Bit Field Type Reset Description 31-0 DATA R/W X Internal. Only to be used through TI provided API.
PAGE 556
VIMS Registers www.ti.com 7.7.2.11 EFUSECFG Register (Offset = 1010h) [reset = X] EFUSECFG is shown in Figure 7-21 and described in Table 7-18. Internal. Only to be used through TI provided API. Figure 7-21. EFUSECFG Register 31 30 29 28 27 26 25 24 19 18 17 16 9 8 IDLEGATING R/W-X 1 0 GATING R/W-1h RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 11 10 7 6 RESERVED R-X 5 4 3 2 SLAVEPOWER R/W-X RESERVED R-X Table 7-18.
PAGE 557
VIMS Registers www.ti.com 7.7.2.12 EFUSESTAT Register (Offset = 1014h) [reset = X] EFUSESTAT is shown in Figure 7-22 and described in Table 7-19. Internal. Only to be used through TI provided API. Figure 7-22. EFUSESTAT Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RESETDONE R-1h RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 4 RESERVED R-X Table 7-19.
PAGE 558
VIMS Registers www.ti.com 7.7.2.13 ACC Register (Offset = 1018h) [reset = X] ACC is shown in Figure 7-23 and described in Table 7-20. Internal. Only to be used through TI provided API. Figure 7-23. ACC Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 RESERVED ACCUMULATOR R-X R-X 8 7 6 5 4 3 2 1 0 Table 7-20. ACC Register Field Descriptions Bit 558 Field Type Reset Description 31-24 RESERVED R X Internal. Only to be used through TI provided API.
PAGE 559
VIMS Registers www.ti.com 7.7.2.14 BOUNDARY Register (Offset = 101Ch) [reset = X] BOUNDARY is shown in Figure 7-24 and described in Table 7-21. Internal. Only to be used through TI provided API. Figure 7-24.
PAGE 560
VIMS Registers www.ti.com 7.7.2.15 EFUSEFLAG Register (Offset = 1020h) [reset = X] EFUSEFLAG is shown in Figure 7-25 and described in Table 7-22. Internal. Only to be used through TI provided API. Figure 7-25. EFUSEFLAG Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 RESERVED R-X 8 7 RESERVED R-X 22 21 20 19 18 17 16 6 5 4 3 2 1 0 KEY R-X Table 7-22. EFUSEFLAG Register Field Descriptions Bit 31-1 0 560 Field Type Reset Description RESERVED R X Internal.
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VIMS Registers www.ti.com 7.7.2.16 EFUSEKEY Register (Offset = 1024h) [reset = X] EFUSEKEY is shown in Figure 7-26 and described in Table 7-23. Internal. Only to be used through TI provided API. Figure 7-26. EFUSEKEY Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 CODE R/W-X 9 8 7 6 5 4 3 2 1 0 Table 7-23. EFUSEKEY Register Field Descriptions Bit Field Type Reset Description 31-0 CODE R/W X Internal. Only to be used through TI provided API.
PAGE 562
VIMS Registers www.ti.com 7.7.2.17 EFUSERELEASE Register (Offset = 1028h) [reset = 0h] EFUSERELEASE is shown in Figure 7-27 and described in Table 7-24. Internal. Only to be used through TI provided API. Figure 7-27. EFUSERELEASE Register 31 30 29 28 27 ODPYEAR R-0h 26 25 24 23 22 ODPMONTH R-0h 21 20 19 15 14 13 12 11 EFUSEYEAR R-0h 10 9 8 7 6 EFUSEMONTH R-0h 5 4 3 18 ODPDAY R-0h 17 16 2 1 EFUSEDAY R-0h 0 Table 7-24.
PAGE 563
VIMS Registers www.ti.com 7.7.2.18 EFUSEPINS Register (Offset = 102Ch) [reset = X] EFUSEPINS is shown in Figure 7-28 and described in Table 7-25. Internal. Only to be used through TI provided API. Figure 7-28.
PAGE 564
VIMS Registers www.ti.com 7.7.2.19 EFUSECRA Register (Offset = 1030h) [reset = X] EFUSECRA is shown in Figure 7-29 and described in Table 7-26. Internal. Only to be used through TI provided API. Figure 7-29. EFUSECRA Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 DATA R/W-X 1 0 Table 7-26. EFUSECRA Register Field Descriptions Bit 564 Field Type Reset Description 31-6 RESERVED R X Internal. Only to be used through TI provided API.
PAGE 565
VIMS Registers www.ti.com 7.7.2.20 EFUSEREAD Register (Offset = 1034h) [reset = X] EFUSEREAD is shown in Figure 7-30 and described in Table 7-27. Internal. Only to be used through TI provided API. Figure 7-30. EFUSEREAD Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 8 DATABIT R/W-X 4 READCLOCK R/W-X 3 DEBUG R/W-X 2 SPARE R/W-X 1 0 MARGIN R/W-X Table 7-27.
PAGE 566
VIMS Registers www.ti.com 7.7.2.21 EFUSEPROGRAM Register (Offset = 1038h) [reset = X] EFUSEPROGRAM is shown in Figure 7-31 and described in Table 7-28. Internal. Only to be used through TI provided API. Figure 7-31.
PAGE 567
VIMS Registers www.ti.com 7.7.2.22 EFUSEERROR Register (Offset = 103Ch) [reset = X] EFUSEERROR is shown in Figure 7-32 and described in Table 7-29. Internal. Only to be used through TI provided API. Figure 7-32. EFUSEERROR Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 CODE R/W-X 1 0 RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 RESERVED R-X 5 DONE R/W-X 4 Table 7-29.
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VIMS Registers www.ti.com 7.7.2.23 SINGLEBIT Register (Offset = 1040h) [reset = X] SINGLEBIT is shown in Figure 7-33 and described in Table 7-30. Internal. Only to be used through TI provided API. Figure 7-33. SINGLEBIT Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FROM0 R-X FROMN R-X 23 22 21 20 FROMN R-X 15 14 13 12 FROMN R-X 7 6 5 4 FROMN R-X Table 7-30.
PAGE 569
VIMS Registers www.ti.com 7.7.2.24 TWOBIT Register (Offset = 1044h) [reset = X] TWOBIT is shown in Figure 7-34 and described in Table 7-31. Internal. Only to be used through TI provided API. Figure 7-34. TWOBIT Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FROM0 R-X FROMN R-X 23 22 21 20 FROMN R-X 15 14 13 12 FROMN R-X 7 6 5 4 FROMN R-X Table 7-31. TWOBIT Register Field Descriptions Field Type Reset Description 31-1 Bit FROMN R X Internal.
PAGE 570
VIMS Registers www.ti.com 7.7.2.25 SELFTESTCYC Register (Offset = 1048h) [reset = X] SELFTESTCYC is shown in Figure 7-35 and described in Table 7-32. Internal. Only to be used through TI provided API. Figure 7-35. SELFTESTCYC Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 CYCLES R/W-X 9 8 7 6 5 4 3 2 1 0 Table 7-32. SELFTESTCYC Register Field Descriptions Bit 31-0 570 Field Type Reset Description CYCLES R/W X Internal.
PAGE 571
VIMS Registers www.ti.com 7.7.2.26 SELFTESTSIGN Register (Offset = 104Ch) [reset = X] SELFTESTSIGN is shown in Figure 7-36 and described in Table 7-33. Internal. Only to be used through TI provided API. Figure 7-36. SELFTESTSIGN Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 SIGNATURE R/W-X 9 8 7 6 5 4 3 2 1 0 Table 7-33. SELFTESTSIGN Register Field Descriptions Bit 31-0 Field Type Reset Description SIGNATURE R/W X Internal.
PAGE 572
VIMS Registers www.ti.com 7.7.2.27 FRDCTL Register (Offset = 2000h) [reset = X] FRDCTL is shown in Figure 7-37 and described in Table 7-34. Internal. Only to be used through TI provided API. Figure 7-37. FRDCTL Register 31 30 29 28 27 26 25 15 14 13 RESERVED R-X 12 11 10 9 RWAIT R/W-2h 24 23 RESERVED R-X 8 7 22 21 20 6 5 4 19 18 17 16 3 2 1 0 RM R-X Table 7-34. FRDCTL Register Field Descriptions Bit 572 Field Type Reset Description 31-12 RESERVED R X Internal.
PAGE 573
VIMS Registers www.ti.com 7.7.2.28 FSPRD Register (Offset = 2004h) [reset = X] FSPRD is shown in Figure 7-38 and described in Table 7-35. Internal. Only to be used through TI provided API. Figure 7-38. FSPRD Register 31 30 29 28 27 26 25 15 14 13 12 11 RMBSEM R/W-X 10 9 24 23 DIS_PREEMPT R-X 8 7 22 21 20 19 18 6 5 4 RESERVED R-X 3 2 17 16 1 0 RM1 RM0 R/W-X R/W-X Table 7-35.
PAGE 574
VIMS Registers www.ti.com 7.7.2.29 FEDACCTL1 Register (Offset = 2008h) [reset = X] FEDACCTL1 is shown in Figure 7-39 and described in Table 7-36. Internal. Only to be used through TI provided API. Figure 7-39. FEDACCTL1 Register 31 30 29 28 RESERVED R-X 27 26 25 24 SUSP_IGNR R/W-X 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 EDACEN R-X 15 14 13 12 EDACEN R-X 7 6 5 4 EDACEN R-X Table 7-36.
PAGE 575
VIMS Registers www.ti.com 7.7.2.30 FEDACSTAT Register (Offset = 201Ch) [reset = X] FEDACSTAT is shown in Figure 7-40 and described in Table 7-37. Internal. Only to be used through TI provided API. Figure 7-40. FEDACSTAT Register 31 30 29 28 27 26 25 RVF_INT R/W1C-X 24 FSM_DONE R/W1C-X RESERVED R-X 23 22 21 20 19 ERR_PRF_FLG R-X 18 17 16 15 14 13 12 11 ERR_PRF_FLG R-X 10 9 8 7 6 5 4 2 1 0 3 ERR_PRF_FLG R-X Table 7-37.
PAGE 576
VIMS Registers www.ti.com 7.7.2.31 FBPROT Register (Offset = 2030h) [reset = X] FBPROT is shown in Figure 7-41 and described in Table 7-38. Internal. Only to be used through TI provided API. Figure 7-41. FBPROT Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 PROTL1DIS R/W-X RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 4 RESERVED R-X Table 7-38.
PAGE 577
VIMS Registers www.ti.com 7.7.2.32 FBSE Register (Offset = 2034h) [reset = X] FBSE is shown in Figure 7-42 and described in Table 7-39. Internal. Only to be used through TI provided API. Figure 7-42. FBSE Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 BSE R/W-X 6 5 4 3 2 1 0 Table 7-39. FBSE Register Field Descriptions Field Type Reset Description 31-16 Bit RESERVED R X Internal. Only to be used through TI provided API.
PAGE 578
VIMS Registers www.ti.com 7.7.2.33 FBBUSY Register (Offset = 2038h) [reset = X] FBBUSY is shown in Figure 7-43 and described in Table 7-40. Internal. Only to be used through TI provided API. Figure 7-43. FBBUSY Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 BUSY R-FEh 2 1 0 Table 7-40. FBBUSY Register Field Descriptions Bit 578 Field Type Reset Description 31-8 RESERVED R X Internal. Only to be used through TI provided API.
PAGE 579
VIMS Registers www.ti.com 7.7.2.34 FBAC Register (Offset = 203Ch) [reset = X] FBAC is shown in Figure 7-44 and described in Table 7-41. Internal. Only to be used through TI provided API. Figure 7-44. FBAC Register 31 30 29 28 27 26 25 24 RESERVED R-X 23 22 21 20 RESERVED R-X 19 18 17 16 OTPPROTDIS R/W-X 15 14 13 12 11 10 9 8 3 2 1 0 BAGP R/W-X 7 6 5 4 VREADS R/W-Fh Table 7-41. FBAC Register Field Descriptions Bit Field Type Reset Description RESERVED R X Internal.
PAGE 580
VIMS Registers www.ti.com 7.7.2.35 FBFALLBACK Register (Offset = 2040h) [reset = X] FBFALLBACK is shown in Figure 7-45 and described in Table 7-42. Internal. Only to be used through TI provided API. Figure 7-45.
PAGE 581
VIMS Registers www.ti.com 7.7.2.36 FBPRDY Register (Offset = 2044h) [reset = X] FBPRDY is shown in Figure 7-46 and described in Table 7-43. Internal. Only to be used through TI provided API. Figure 7-46. FBPRDY Register 31 30 29 28 27 26 25 24 RESERVED R-7Fh 23 22 21 20 RESERVED R-7Fh 19 18 17 16 BANKBUSY R-1h 15 PUMPRDY R-X 14 13 12 11 RESERVED R-7Fh 10 9 8 7 6 5 4 RESERVED R-7Fh 3 2 1 0 BANKRDY R-X Table 7-43.
PAGE 582
VIMS Registers www.ti.com 7.7.2.37 FPAC1 Register (Offset = 2048h) [reset = X] FPAC1 is shown in Figure 7-47 and described in Table 7-44. Internal. Only to be used through TI provided API. Figure 7-47. FPAC1 Register 31 30 29 28 27 26 RESERVED R-X 23 22 25 24 PSLEEPTDIS R/W-208h 21 20 19 18 17 16 12 11 PUMPRESET_PW R/W-208h 10 9 8 2 1 PSLEEPTDIS R/W-208h 15 14 13 7 6 5 PUMPRESET_PW R/W-208h 4 3 RESERVED R-X 0 PUMPPWR R/W-1h Table 7-44.
PAGE 583
VIMS Registers www.ti.com 7.7.2.38 FPAC2 Register (Offset = 204Ch) [reset = X] FPAC2 is shown in Figure 7-48 and described in Table 7-45. Internal. Only to be used through TI provided API. Figure 7-48. FPAC2 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 PAGP R/W-X 6 5 4 3 2 1 0 Table 7-45. FPAC2 Register Field Descriptions Field Type Reset Description 31-16 Bit RESERVED R X Internal. Only to be used through TI provided API.
PAGE 584
VIMS Registers www.ti.com 7.7.2.39 FMAC Register (Offset = 2050h) [reset = X] FMAC is shown in Figure 7-49 and described in Table 7-46. Internal. Only to be used through TI provided API. Figure 7-49. FMAC Register 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 RESERVED R-X 9 8 RESERVED R-X 7 22 21 20 19 18 17 16 6 5 4 3 2 1 BANK R/W-X 0 Table 7-46. FMAC Register Field Descriptions Bit 584 Field Type Reset Description 31-3 RESERVED R X Internal.
PAGE 585
VIMS Registers www.ti.com 7.7.2.40 FMSTAT Register (Offset = 2054h) [reset = X] FMSTAT is shown in Figure 7-50 and described in Table 7-47. Internal. Only to be used through TI provided API. Figure 7-50.
PAGE 586
VIMS Registers www.ti.com 7.7.2.41 FLOCK Register (Offset = 2064h) [reset = X] FLOCK is shown in Figure 7-51 and described in Table 7-48. Internal. Only to be used through TI provided API. Figure 7-51. FLOCK Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 ENCOM R/W-55AAh 5 4 3 2 1 0 Table 7-48. FLOCK Register Field Descriptions Bit 586 Field Type Reset Description 31-16 RESERVED R X Internal. Only to be used through TI provided API.
PAGE 587
VIMS Registers www.ti.com 7.7.2.42 FVREADCT Register (Offset = 2080h) [reset = X] FVREADCT is shown in Figure 7-52 and described in Table 7-49. Internal. Only to be used through TI provided API. Figure 7-52. FVREADCT Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 RESERVED R-X 24 23 RESERVED R-X 8 7 22 21 20 19 18 17 16 6 5 4 3 2 1 VREADCT R/W-8h 0 Table 7-49. FVREADCT Register Field Descriptions Field Type Reset Description 31-4 Bit RESERVED R X Internal.
PAGE 588
VIMS Registers www.ti.com 7.7.2.43 FVHVCT1 Register (Offset = 2084h) [reset = X] FVHVCT1 is shown in Figure 7-53 and described in Table 7-50. Internal. Only to be used through TI provided API. Figure 7-53. FVHVCT1 Register 31 30 29 28 27 RESERVED R-X 26 25 24 23 22 21 TRIM13_E R/W-8h 20 19 18 17 VHVCT_E R/W-4h 16 15 14 13 12 11 RESERVED R-X 10 9 8 7 6 5 TRIM13_PV R/W-8h 4 3 2 1 VHVCT_PV R/W-8h 0 Table 7-50.
PAGE 589
VIMS Registers www.ti.com 7.7.2.44 FVHVCT2 Register (Offset = 2088h) [reset = X] FVHVCT2 is shown in Figure 7-54 and described in Table 7-51. Internal. Only to be used through TI provided API. Figure 7-54. FVHVCT2 Register 31 30 29 28 27 RESERVED R-X 26 25 24 15 14 13 12 10 9 8 7 RESERVED R-X 11 23 22 21 TRIM13_P R/W-Ah 20 19 18 17 VHVCT_P R/W-2h 16 6 4 3 2 0 5 1 Table 7-51.
PAGE 590
VIMS Registers www.ti.com 7.7.2.45 FVHVCT3 Register (Offset = 208Ch) [reset = X] FVHVCT3 is shown in Figure 7-55 and described in Table 7-52. Internal. Only to be used through TI provided API. Figure 7-55. FVHVCT3 Register 31 30 29 28 27 26 25 RESERVED R-X 24 23 22 21 20 19 15 14 13 12 11 10 9 RESERVED R-X 8 7 6 5 4 3 18 17 WCT R/W-Fh 2 1 VHVCT_READ R/W-X 16 0 Table 7-52.
PAGE 591
VIMS Registers www.ti.com 7.7.2.46 FVNVCT Register (Offset = 2090h) [reset = X] FVNVCT is shown in Figure 7-56 and described in Table 7-53. Internal. Only to be used through TI provided API. Figure 7-56. FVNVCT Register 31 15 30 29 28 27 26 25 14 13 RESERVED R-X 12 11 10 VCG2P5CT R/W-8h 9 24 23 RESERVED R-X 8 7 22 21 20 19 18 17 16 6 5 RESERVED R-X 4 3 2 VIN_CT R/W-X 1 0 Table 7-53.
PAGE 592
VIMS Registers www.ti.com 7.7.2.47 FVSLP Register (Offset = 2094h) [reset = X] FVSLP is shown in Figure 7-57 and described in Table 7-54. Internal. Only to be used through TI provided API. Figure 7-57. FVSLP Register 31 30 29 28 27 26 25 15 14 13 VSL_P R/W-8h 12 11 10 9 24 23 RESERVED R-X 8 7 22 21 20 19 18 17 16 6 5 RESERVED R-X 4 3 2 1 0 Table 7-54. FVSLP Register Field Descriptions Bit 592 Field Type Reset Description 31-16 RESERVED R X Internal.
PAGE 593
VIMS Registers www.ti.com 7.7.2.48 FVWLCT Register (Offset = 2098h) [reset = X] FVWLCT is shown in Figure 7-58 and described in Table 7-55. Internal. Only to be used through TI provided API. Figure 7-58. FVWLCT Register 31 30 29 28 27 15 14 13 12 11 26 25 10 9 RESERVED R-X 24 23 RESERVED R-X 8 7 22 21 20 19 18 17 16 6 5 4 3 2 VWLCT_P R/W-8h 1 0 Table 7-55. FVWLCT Register Field Descriptions Field Type Reset Description 31-5 Bit RESERVED R X Internal.
PAGE 594
VIMS Registers www.ti.com 7.7.2.49 FEFUSECTL Register (Offset = 209Ch) [reset = X] FEFUSECTL is shown in Figure 7-59 and described in Table 7-56. Internal. Only to be used through TI provided API. Figure 7-59. FEFUSECTL Register 31 30 29 RESERVED R-X 28 27 26 25 CHAIN_SEL R/W-7h 24 23 22 21 20 19 18 17 WRITE_EN R/W-X 16 BP_SEL R/W-1h 9 8 EF_CLRZ R/W-1h 1 0 RESERVED R-X 15 14 13 12 RESERVED R-X 11 10 7 6 RESERVED R-X 5 4 EF_TEST R/W-X 3 2 EFUSE_EN R/W-Ah Table 7-56.
PAGE 595
VIMS Registers www.ti.com 7.7.2.50 FEFUSESTAT Register (Offset = 20A0h) [reset = X] FEFUSESTAT is shown in Figure 7-60 and described in Table 7-57. Internal. Only to be used through TI provided API. Figure 7-60. FEFUSESTAT Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SHIFT_DONE R/W1C-X RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 4 RESERVED R-X Table 7-57.
PAGE 596
VIMS Registers www.ti.com 7.7.2.51 FEFUSEDATA Register (Offset = 20A4h) [reset = X] FEFUSEDATA is shown in Figure 7-61 and described in Table 7-58. Internal. Only to be used through TI provided API. Figure 7-61. FEFUSEDATA Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 FEFUSEDATA R/W-X 9 8 7 6 5 4 3 2 1 0 Table 7-58. FEFUSEDATA Register Field Descriptions Bit 31-0 596 Field Type Reset Description FEFUSEDATA R/W X Internal.
PAGE 597
VIMS Registers www.ti.com 7.7.2.52 FSEQPMP Register (Offset = 20A8h) [reset = X] FSEQPMP is shown in Figure 7-62 and described in Table 7-59. Internal. Only to be used through TI provided API. Figure 7-62. FSEQPMP Register 31 30 29 28 27 26 RESERVED R/W-8h 23 22 25 24 17 16 TRIM_3P4 R/W-5h 21 RESERVED R-X 20 19 18 TRIM_1P7 R/W-X TRIM_0P8 R/W-8h 15 RESERVED R-X 14 13 VIN_AT_X R/W-X 12 7 6 5 4 11 10 RESERVED R-X 9 8 VIN_BY_PASS R/W-X 3 2 1 0 SEQ_PUMP R/W-X Table 7-59.
PAGE 598
VIMS Registers www.ti.com 7.7.2.53 FBSTROBES Register (Offset = 2100h) [reset = X] FBSTROBES is shown in Figure 7-63 and described in Table 7-60. Internal. Only to be used through TI provided API. Figure 7-63.
PAGE 599
VIMS Registers www.ti.com 7.7.2.54 FPSTROBES Register (Offset = 2104h) [reset = X] FPSTROBES is shown in Figure 7-64 and described in Table 7-61. Internal. Only to be used through TI provided API. Figure 7-64. FPSTROBES Register 31 30 29 28 27 26 25 24 19 18 17 16 12 RESERVED R-X 11 10 9 8 EXECUTEZ R/W-1h 4 3 2 1 V3PWRDNZ R/W-1h 0 V5PWRDNZ R/W-1h RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 7 6 5 RESERVED R-X Table 7-61.
PAGE 600
VIMS Registers www.ti.com 7.7.2.55 FBMODE Register (Offset = 2108h) [reset = X] FBMODE is shown in Figure 7-65 and described in Table 7-62. Internal. Only to be used through TI provided API. Figure 7-65. FBMODE Register 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 RESERVED R-X 9 8 RESERVED R-X 7 22 21 20 19 18 17 16 6 5 4 3 2 1 MODE R/W-X 0 Table 7-62. FBMODE Register Field Descriptions Bit 600 Field Type Reset Description 31-3 RESERVED R X Internal.
PAGE 601
VIMS Registers www.ti.com 7.7.2.56 FTCR Register (Offset = 210Ch) [reset = X] FTCR is shown in Figure 7-66 and described in Table 7-63. Internal. Only to be used through TI provided API. Figure 7-66. FTCR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 TCR R/W-X 1 0 Table 7-63. FTCR Register Field Descriptions Field Type Reset Description 31-7 Bit RESERVED R X Internal. Only to be used through TI provided API.
PAGE 602
VIMS Registers www.ti.com 7.7.2.57 FADDR Register (Offset = 2110h) [reset = X] FADDR is shown in Figure 7-67 and described in Table 7-64. Internal. Only to be used through TI provided API. Figure 7-67. FADDR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 FADDR R/W-X 9 8 7 6 5 4 3 2 1 0 Table 7-64. FADDR Register Field Descriptions Bit 31-0 602 Field Type Reset Description FADDR R/W X Internal. Only to be used through TI provided API.
PAGE 603
VIMS Registers www.ti.com 7.7.2.58 FTCTL Register (Offset = 211Ch) [reset = X] FTCTL is shown in Figure 7-68 and described in Table 7-65. Internal. Only to be used through TI provided API. Figure 7-68. FTCTL Register 31 30 29 28 27 26 25 24 19 18 17 16 WDATA_BLK_ CLR R/W-X 11 10 9 8 3 2 1 TEST_EN R/W-X 0 RESERVED R-X RESERVED R-X 23 22 21 15 14 13 20 RESERVED R-X 12 RESERVED R-X 7 6 5 4 RESERVED R-X Table 7-65.
PAGE 604
VIMS Registers www.ti.com 7.7.2.59 FWPWRITE0 Register (Offset = 2120h) [reset = FFFFFFFFh] FWPWRITE0 is shown in Figure 7-69 and described in Table 7-66. Internal. Only to be used through TI provided API. Figure 7-69. FWPWRITE0 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 FWPWRITE0 R/W-FFFFFFFFh 9 8 7 6 5 4 3 2 1 0 Table 7-66. FWPWRITE0 Register Field Descriptions Bit 31-0 604 Field Type Reset FWPWRITE0 R/W FFFFFFFFh Internal.
PAGE 605
VIMS Registers www.ti.com 7.7.2.60 FWPWRITE1 Register (Offset = 2124h) [reset = FFFFFFFFh] FWPWRITE1 is shown in Figure 7-70 and described in Table 7-67. Internal. Only to be used through TI provided API. Figure 7-70. FWPWRITE1 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 FWPWRITE1 R/W-FFFFFFFFh 9 8 7 6 5 4 3 2 1 0 Table 7-67. FWPWRITE1 Register Field Descriptions Bit 31-0 Field Type Reset FWPWRITE1 R/W FFFFFFFFh Internal.
PAGE 606
VIMS Registers www.ti.com 7.7.2.61 FWPWRITE2 Register (Offset = 2128h) [reset = FFFFFFFFh] FWPWRITE2 is shown in Figure 7-71 and described in Table 7-68. Internal. Only to be used through TI provided API. Figure 7-71. FWPWRITE2 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 FWPWRITE2 R/W-FFFFFFFFh 9 8 7 6 5 4 3 2 1 0 Table 7-68. FWPWRITE2 Register Field Descriptions Bit 31-0 606 Field Type Reset FWPWRITE2 R/W FFFFFFFFh Internal.
PAGE 607
VIMS Registers www.ti.com 7.7.2.62 FWPWRITE3 Register (Offset = 212Ch) [reset = FFFFFFFFh] FWPWRITE3 is shown in Figure 7-72 and described in Table 7-69. Internal. Only to be used through TI provided API. Figure 7-72. FWPWRITE3 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 FWPWRITE3 R/W-FFFFFFFFh 9 8 7 6 5 4 3 2 1 0 Table 7-69. FWPWRITE3 Register Field Descriptions Bit 31-0 Field Type Reset FWPWRITE3 R/W FFFFFFFFh Internal.
PAGE 608
VIMS Registers www.ti.com 7.7.2.63 FWPWRITE4 Register (Offset = 2130h) [reset = FFFFFFFFh] FWPWRITE4 is shown in Figure 7-73 and described in Table 7-70. Internal. Only to be used through TI provided API. Figure 7-73. FWPWRITE4 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 FWPWRITE4 R/W-FFFFFFFFh 9 8 7 6 5 4 3 2 1 0 Table 7-70. FWPWRITE4 Register Field Descriptions Bit 31-0 608 Field Type Reset FWPWRITE4 R/W FFFFFFFFh Internal.
PAGE 609
VIMS Registers www.ti.com 7.7.2.64 FWPWRITE5 Register (Offset = 2134h) [reset = FFFFFFFFh] FWPWRITE5 is shown in Figure 7-74 and described in Table 7-71. Internal. Only to be used through TI provided API. Figure 7-74. FWPWRITE5 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 FWPWRITE5 R/W-FFFFFFFFh 9 8 7 6 5 4 3 2 1 0 Table 7-71. FWPWRITE5 Register Field Descriptions Bit 31-0 Field Type Reset FWPWRITE5 R/W FFFFFFFFh Internal.
PAGE 610
VIMS Registers www.ti.com 7.7.2.65 FWPWRITE6 Register (Offset = 2138h) [reset = FFFFFFFFh] FWPWRITE6 is shown in Figure 7-75 and described in Table 7-72. Internal. Only to be used through TI provided API. Figure 7-75. FWPWRITE6 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 FWPWRITE6 R/W-FFFFFFFFh 9 8 7 6 5 4 3 2 1 0 Table 7-72. FWPWRITE6 Register Field Descriptions Bit 31-0 610 Field Type Reset FWPWRITE6 R/W FFFFFFFFh Internal.
PAGE 611
VIMS Registers www.ti.com 7.7.2.66 FWPWRITE7 Register (Offset = 213Ch) [reset = FFFFFFFFh] FWPWRITE7 is shown in Figure 7-76 and described in Table 7-73. Internal. Only to be used through TI provided API. Figure 7-76. FWPWRITE7 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 FWPWRITE7 R/W-FFFFFFFFh 9 8 7 6 5 4 3 2 1 0 Table 7-73. FWPWRITE7 Register Field Descriptions Bit 31-0 Field Type Reset FWPWRITE7 R/W FFFFFFFFh Internal.
PAGE 612
VIMS Registers www.ti.com 7.7.2.67 FWPWRITE_ECC Register (Offset = 2140h) [reset = FFFFFFFFh] FWPWRITE_ECC is shown in Figure 7-77 and described in Table 7-74. Internal. Only to be used through TI provided API. Figure 7-77. FWPWRITE_ECC Register 31 30 29 28 27 ECCBYTES07_00 R/W-FFh 26 25 24 23 22 21 20 19 ECCBYTES15_08 R/W-FFh 18 17 16 15 14 13 12 11 ECCBYTES23_16 R/W-FFh 10 9 8 7 6 5 4 3 ECCBYTES31_24 R/W-FFh 2 1 0 Table 7-74.
PAGE 613
VIMS Registers www.ti.com 7.7.2.68 FSWSTAT Register (Offset = 2144h) [reset = X] FSWSTAT is shown in Figure 7-78 and described in Table 7-75. Internal. Only to be used through TI provided API. Figure 7-78. FSWSTAT Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SAFELV R-1h RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 4 RESERVED R-X Table 7-75.
PAGE 614
VIMS Registers www.ti.com 7.7.2.69 FSM_GLBCTL Register (Offset = 2200h) [reset = X] FSM_GLBCTL is shown in Figure 7-79 and described in Table 7-76. Internal. Only to be used through TI provided API. Figure 7-79. FSM_GLBCTL Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CLKSEL R-1h RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 4 RESERVED R-X Table 7-76.
PAGE 615
VIMS Registers www.ti.com 7.7.2.70 FSM_STATE Register (Offset = 2204h) [reset = X] FSM_STATE is shown in Figure 7-80 and described in Table 7-77. Internal. Only to be used through TI provided API. Figure 7-80. FSM_STATE Register 31 30 29 28 27 26 25 24 19 18 17 16 RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 11 CTRLENZ R-1h 10 EXECUTEZ R-1h 9 RESERVED R-X 8 FSM_ACT R-X 5 4 3 2 1 0 RESERVED R-X 7 TIOTP_ACT R-X 6 OTP_ACT R-X RESERVED R-X Table 7-77.
PAGE 616
VIMS Registers www.ti.com 7.7.2.71 FSM_STAT Register (Offset = 2208h) [reset = X] FSM_STAT is shown in Figure 7-81 and described in Table 7-78. Internal. Only to be used through TI provided API. Figure 7-81. FSM_STAT Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 NON_OP 1 OVR_PUL_CN T R-X 0 INV_DAT RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 RESERVED 4 R-X R-1h R-X Table 7-78.
PAGE 617
VIMS Registers www.ti.com 7.7.2.72 FSM_CMD Register (Offset = 220Ch) [reset = X] FSM_CMD is shown in Figure 7-82 and described in Table 7-79. Internal. Only to be used through TI provided API. Figure 7-82. FSM_CMD Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 1 FSMCMD R/W-X 0 Table 7-79. FSM_CMD Register Field Descriptions Field Type Reset Description 31-6 Bit RESERVED R X Internal. Only to be used through TI provided API.
PAGE 618
VIMS Registers www.ti.com 7.7.2.73 FSM_PE_OSU Register (Offset = 2210h) [reset = X] FSM_PE_OSU is shown in Figure 7-83 and described in Table 7-80. Internal. Only to be used through TI provided API. Figure 7-83. FSM_PE_OSU Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED PGM_OSU R-X R/W-X 9 8 7 6 5 4 3 2 ERA_OSU R/W-X 1 0 Table 7-80. FSM_PE_OSU Register Field Descriptions Bit 618 Field Type Reset Description 31-16 RESERVED R X Internal.
PAGE 619
VIMS Registers www.ti.com 7.7.2.74 FSM_VSTAT Register (Offset = 2214h) [reset = X] FSM_VSTAT is shown in Figure 7-84 and described in Table 7-81. Internal. Only to be used through TI provided API. Figure 7-84. FSM_VSTAT Register 31 15 30 29 14 13 VSTAT_CNT R/W-3h 28 27 26 25 12 11 10 9 24 23 RESERVED R-X 8 7 22 21 20 19 18 17 16 6 5 RESERVED R-X 4 3 2 1 0 Table 7-81. FSM_VSTAT Register Field Descriptions Field Type Reset Description 31-16 Bit RESERVED R X Internal.
PAGE 620
VIMS Registers www.ti.com 7.7.2.75 FSM_PE_VSU Register (Offset = 2218h) [reset = X] FSM_PE_VSU is shown in Figure 7-85 and described in Table 7-82. Internal. Only to be used through TI provided API. Figure 7-85. FSM_PE_VSU Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED PGM_VSU R-X R/W-X 9 8 7 6 5 4 3 2 ERA_VSU R/W-X 1 0 Table 7-82. FSM_PE_VSU Register Field Descriptions Bit 620 Field Type Reset Description 31-16 RESERVED R X Internal.
PAGE 621
VIMS Registers www.ti.com 7.7.2.76 FSM_CMP_VSU Register (Offset = 221Ch) [reset = X] FSM_CMP_VSU is shown in Figure 7-86 and described in Table 7-83. Internal. Only to be used through TI provided API. Figure 7-86. FSM_CMP_VSU Register 31 30 29 28 27 26 25 15 14 13 ADD_EXZ R/W-X 12 11 10 9 24 23 RESERVED R-X 8 7 22 21 20 19 18 17 16 6 5 RESERVED R-X 4 3 2 1 0 Table 7-83.
PAGE 622
VIMS Registers www.ti.com 7.7.2.77 FSM_EX_VAL Register (Offset = 2220h) [reset = X] FSM_EX_VAL is shown in Figure 7-87 and described in Table 7-84. Internal. Only to be used through TI provided API. Figure 7-87. FSM_EX_VAL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED REP_VSU R-X R/W-3h 9 8 7 6 5 4 3 2 EXE_VALD R/W-1h 1 0 Table 7-84. FSM_EX_VAL Register Field Descriptions Bit 622 Field Type Reset Description 31-16 RESERVED R X Internal.
PAGE 623
VIMS Registers www.ti.com 7.7.2.78 FSM_RD_H Register (Offset = 2224h) [reset = X] FSM_RD_H is shown in Figure 7-88 and described in Table 7-85. Internal. Only to be used through TI provided API. Figure 7-88. FSM_RD_H Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 RD_H R/W-5Ah 1 0 Table 7-85. FSM_RD_H Register Field Descriptions Field Type Reset Description 31-8 Bit RESERVED R X Internal. Only to be used through TI provided API.
PAGE 624
VIMS Registers www.ti.com 7.7.2.79 FSM_P_OH Register (Offset = 2228h) [reset = X] FSM_P_OH is shown in Figure 7-89 and described in Table 7-86. Internal. Only to be used through TI provided API. Figure 7-89. FSM_P_OH Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED PGM_OH R-X R/W-1h 9 8 7 6 5 4 3 2 RESERVED R-X 1 0 Table 7-86. FSM_P_OH Register Field Descriptions Bit 624 Field Type Reset Description 31-16 RESERVED R X Internal.
PAGE 625
VIMS Registers www.ti.com 7.7.2.80 FSM_ERA_OH Register (Offset = 222Ch) [reset = X] FSM_ERA_OH is shown in Figure 7-90 and described in Table 7-87. Internal. Only to be used through TI provided API. Figure 7-90. FSM_ERA_OH Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 ERA_OH R/W-1h 5 4 3 2 1 0 Table 7-87. FSM_ERA_OH Register Field Descriptions Field Type Reset Description 31-16 Bit RESERVED R X Internal.
PAGE 626
VIMS Registers www.ti.com 7.7.2.81 FSM_SAV_PPUL Register (Offset = 2230h) [reset = X] FSM_SAV_PPUL is shown in Figure 7-91 and described in Table 7-88. Internal. Only to be used through TI provided API. Figure 7-91. FSM_SAV_PPUL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 SAV_P_PUL R-X 3 2 1 0 Table 7-88. FSM_SAV_PPUL Register Field Descriptions Bit 626 Field Type Reset Description 31-12 RESERVED R X Internal.
PAGE 627
VIMS Registers www.ti.com 7.7.2.82 FSM_PE_VH Register (Offset = 2234h) [reset = X] FSM_PE_VH is shown in Figure 7-92 and described in Table 7-89. Internal. Only to be used through TI provided API. Figure 7-92. FSM_PE_VH Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED PGM_VH R-X R/W-1h 9 8 7 6 5 4 3 2 ERA_VH R-X 1 0 Table 7-89. FSM_PE_VH Register Field Descriptions Field Type Reset Description 31-16 Bit RESERVED R X Internal.
PAGE 628
VIMS Registers www.ti.com 7.7.2.83 FSM_PRG_PW Register (Offset = 2240h) [reset = X] FSM_PRG_PW is shown in Figure 7-93 and described in Table 7-90. Internal. Only to be used through TI provided API. Figure 7-93. FSM_PRG_PW Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 RESERVED PROG_PUL_WIDTH R-X R/W-X 4 3 2 1 0 Table 7-90. FSM_PRG_PW Register Field Descriptions Bit 628 Field Type Reset Description 31-16 RESERVED R X Internal.
PAGE 629
VIMS Registers www.ti.com 7.7.2.84 FSM_ERA_PW Register (Offset = 2244h) [reset = X] FSM_ERA_PW is shown in Figure 7-94 and described in Table 7-91. Internal. Only to be used through TI provided API. Figure 7-94. FSM_ERA_PW Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 FSM_ERA_PW R/W-X 9 8 7 6 5 4 3 2 1 0 Table 7-91. FSM_ERA_PW Register Field Descriptions Bit 31-0 Field Type Reset Description FSM_ERA_PW R/W X Internal. Only to be used through TI provided API.
PAGE 630
VIMS Registers www.ti.com 7.7.2.85 FSM_SAV_ERA_PUL Register (Offset = 2254h) [reset = X] FSM_SAV_ERA_PUL is shown in Figure 7-95 and described in Table 7-92. Internal. Only to be used through TI provided API. Figure 7-95. FSM_SAV_ERA_PUL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 SAV_ERA_PUL R-X 3 2 1 0 Table 7-92. FSM_SAV_ERA_PUL Register Field Descriptions Bit 630 Field Type Reset Description 31-12 RESERVED R X Internal.
PAGE 631
VIMS Registers www.ti.com 7.7.2.86 FSM_TIMER Register (Offset = 2258h) [reset = X] FSM_TIMER is shown in Figure 7-96 and described in Table 7-93. Internal. Only to be used through TI provided API. Figure 7-96. FSM_TIMER Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 FSM_TIMER R-X 9 8 7 6 5 4 3 2 1 0 Table 7-93. FSM_TIMER Register Field Descriptions Bit 31-0 Field Type Reset Description FSM_TIMER R X Internal. Only to be used through TI provided API.
PAGE 632
VIMS Registers www.ti.com 7.7.2.87 FSM_MODE Register (Offset = 225Ch) [reset = X] FSM_MODE is shown in Figure 7-97 and described in Table 7-94. Internal. Only to be used through TI provided API. Figure 7-97. FSM_MODE Register 31 30 29 28 27 26 25 24 RESERVED R-X 23 22 21 20 19 18 RDV_SUBMODE R-X 17 16 PGM_SUBMODE R-X 12 11 9 8 SAV_ERA_MO DE R-X 1 CMD R-X 0 RESERVED R-X 15 14 ERA_SUBMODE 13 SUBMODE 10 SAV_PGM_CMD R-X R-X R-X 7 6 SAV_ERA_MODE R-X 5 4 MODE R-X 3 2 Table 7-94.
PAGE 633
VIMS Registers www.ti.com 7.7.2.88 FSM_PGM Register (Offset = 2260h) [reset = X] FSM_PGM is shown in Figure 7-98 and described in Table 7-95. Internal. Only to be used through TI provided API. Figure 7-98. FSM_PGM Register 31 30 29 28 RESERVED R-X 27 26 25 15 14 13 11 10 9 12 24 23 PGM_BANK R-X 8 7 PGM_ADDR R-X 22 21 20 6 5 4 19 18 PGM_ADDR R-X 3 2 17 16 1 0 Table 7-95. FSM_PGM Register Field Descriptions Field Type Reset Description 31-26 Bit RESERVED R X Internal.
PAGE 634
VIMS Registers www.ti.com 7.7.2.89 FSM_ERA Register (Offset = 2264h) [reset = X] FSM_ERA is shown in Figure 7-99 and described in Table 7-96. Internal. Only to be used through TI provided API. Figure 7-99. FSM_ERA Register 31 30 29 28 RESERVED R-X 27 26 25 24 23 ERA_BANK R-X 22 21 20 15 14 13 11 10 9 8 7 ERA_ADDR R-X 6 5 4 12 19 18 ERA_ADDR R-X 3 2 17 16 1 0 Table 7-96.
PAGE 635
VIMS Registers www.ti.com 7.7.2.90 FSM_PRG_PUL Register (Offset = 2268h) [reset = X] FSM_PRG_PUL is shown in Figure 7-100 and described in Table 7-97. Internal. Only to be used through TI provided API. Figure 7-100. FSM_PRG_PUL Register 31 30 29 28 27 26 25 RESERVED R-X 24 23 15 14 13 RESERVED R-X 12 11 10 8 7 9 22 21 6 5 MAX_PRG_PUL R/W-32h 20 19 4 3 18 17 BEG_EC_LEVEL R/W-4h 2 1 16 0 Table 7-97.
PAGE 636
VIMS Registers www.ti.com 7.7.2.91 FSM_ERA_PUL Register (Offset = 226Ch) [reset = X] FSM_ERA_PUL is shown in Figure 7-101 and described in Table 7-98. Internal. Only to be used through TI provided API. Figure 7-101. FSM_ERA_PUL Register 31 30 29 28 27 26 25 RESERVED R-X 24 23 15 14 13 RESERVED R-X 12 11 10 8 7 9 22 21 6 5 MAX_ERA_PUL R/W-BB8h 20 19 4 3 18 17 MAX_EC_LEVEL R/W-4h 2 1 16 0 Table 7-98.
PAGE 637
VIMS Registers www.ti.com 7.7.2.92 FSM_STEP_SIZE Register (Offset = 2270h) [reset = X] FSM_STEP_SIZE is shown in Figure 7-102 and described in Table 7-99. Internal. Only to be used through TI provided API. Figure 7-102. FSM_STEP_SIZE Register 31 30 29 15 14 13 28 27 RESERVED R-X 12 11 26 25 24 23 22 21 20 19 EC_STEP_SIZE R/W-X 18 17 16 10 9 8 7 RESERVED R-X 6 5 2 1 0 4 3 Table 7-99.
PAGE 638
VIMS Registers www.ti.com 7.7.2.93 FSM_PUL_CNTR Register (Offset = 2274h) [reset = X] FSM_PUL_CNTR is shown in Figure 7-103 and described in Table 7-100. Internal. Only to be used through TI provided API. Figure 7-103. FSM_PUL_CNTR Register 31 30 29 15 14 13 RESERVED R-X 28 27 RESERVED R-X 12 11 26 25 24 23 22 21 20 19 CUR_EC_LEVEL R-X 10 9 8 7 6 5 PUL_CNTR R-X 4 3 18 17 16 2 1 0 Table 7-100.
PAGE 639
VIMS Registers www.ti.com 7.7.2.94 FSM_EC_STEP_HEIGHT Register (Offset = 2278h) [reset = X] FSM_EC_STEP_HEIGHT is shown in Figure 7-104 and described in Table 7-101. Internal. Only to be used through TI provided API. Figure 7-104. FSM_EC_STEP_HEIGHT Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 EC_STEP_HEIGHT R/W-X 0 RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 4 RESERVED R-X Table 7-101.
PAGE 640
VIMS Registers www.ti.com 7.7.2.95 FSM_ST_MACHINE Register (Offset = 227Ch) [reset = X] FSM_ST_MACHINE is shown in Figure 7-105 and described in Table 7-102. Internal. Only to be used through TI provided API. Figure 7-105.
PAGE 641
VIMS Registers www.ti.com 7.7.2.96 FSM_FLES Register (Offset = 2280h) [reset = X] FSM_FLES is shown in Figure 7-106 and described in Table 7-103. Internal. Only to be used through TI provided API. Figure 7-106. FSM_FLES Register 31 30 29 28 27 26 25 15 14 13 RESERVED R-X 12 11 10 9 BLK_TIOTP R/W-X 24 23 RESERVED R-X 8 7 22 21 20 19 18 17 16 6 5 4 3 BLK_OTP R/W-X 2 1 0 Table 7-103.
PAGE 642
VIMS Registers www.ti.com 7.7.2.97 FSM_WR_ENA Register (Offset = 2288h) [reset = X] FSM_WR_ENA is shown in Figure 7-107 and described in Table 7-104. Internal. Only to be used through TI provided API. Figure 7-107. FSM_WR_ENA Register 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 RESERVED R-X 9 8 RESERVED R-X 7 22 21 20 19 18 17 16 6 5 4 3 2 1 WR_ENA R/W-2h 0 Table 7-104.
PAGE 643
VIMS Registers www.ti.com 7.7.2.98 FSM_ACC_PP Register (Offset = 228Ch) [reset = X] FSM_ACC_PP is shown in Figure 7-108 and described in Table 7-105. Internal. Only to be used through TI provided API. Figure 7-108. FSM_ACC_PP Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 FSM_ACC_PP R-X 9 8 7 6 5 4 3 2 1 0 Table 7-105. FSM_ACC_PP Register Field Descriptions Bit 31-0 Field Type Reset Description FSM_ACC_PP R X Internal. Only to be used through TI provided API.
PAGE 644
VIMS Registers www.ti.com 7.7.2.99 FSM_ACC_EP Register (Offset = 2290h) [reset = X] FSM_ACC_EP is shown in Figure 7-109 and described in Table 7-106. Internal. Only to be used through TI provided API. Figure 7-109. FSM_ACC_EP Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 ACC_EP R-X 5 4 3 2 1 0 Table 7-106. FSM_ACC_EP Register Field Descriptions Bit 644 Field Type Reset Description 31-16 RESERVED R X Internal.
PAGE 645
VIMS Registers www.ti.com 7.7.2.100 FSM_ADDR Register (Offset = 22A0h) [reset = X] FSM_ADDR is shown in Figure 7-110 and described in Table 7-107. Internal. Only to be used through TI provided API. Figure 7-110. FSM_ADDR Register 31 RESERVED R-X 30 23 22 29 BANK R-X 28 21 20 27 26 25 24 CUR_ADDR R-X 19 18 17 16 11 10 9 8 3 2 1 0 CUR_ADDR R-X 15 14 13 12 CUR_ADDR R-X 7 6 5 4 CUR_ADDR R-X Table 7-107.
PAGE 646
VIMS Registers www.ti.com 7.7.2.101 FSM_SECTOR Register (Offset = 22A4h) [reset = X] FSM_SECTOR is shown in Figure 7-111 and described in Table 7-108. Internal. Only to be used through TI provided API. Figure 7-111. FSM_SECTOR Register 31 30 29 28 27 26 25 15 14 13 12 11 10 FSM_SECTOR_EXTENSION R-X 9 24 23 SECT_ERASED R/W-FFFFh 8 7 22 21 20 19 18 17 16 6 5 SECTOR R-X 4 3 2 1 SEC_OUT R-X 0 Table 7-108.
PAGE 647
VIMS Registers www.ti.com 7.7.2.102 FMC_REV_ID Register (Offset = 22A8h) [reset = 0h] FMC_REV_ID is shown in Figure 7-112 and described in Table 7-109. Internal. Only to be used through TI provided API. Figure 7-112. FMC_REV_ID Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 MOD_VERSION R-0h 9 8 7 6 5 4 CONFIG_CRC R-0h 3 2 1 0 Table 7-109. FMC_REV_ID Register Field Descriptions Field Type Reset Description 31-12 Bit MOD_VERSION R 0h Internal.
PAGE 648
VIMS Registers www.ti.com 7.7.2.103 FSM_ERR_ADDR Register (Offset = 22ACh) [reset = X] FSM_ERR_ADDR is shown in Figure 7-113 and described in Table 7-110. Internal. Only to be used through TI provided API. Figure 7-113. FSM_ERR_ADDR Register 31 30 29 15 14 13 28 27 12 11 FSM_ERR_ADDR R-X 26 25 10 9 24 23 FSM_ERR_ADDR R-X 8 7 22 21 20 19 6 5 RESERVED R-X 4 3 18 17 2 1 FSM_ERR_BANK R-X 16 0 Table 7-110.
PAGE 649
VIMS Registers www.ti.com 7.7.2.104 FSM_PGM_MAXPUL Register (Offset = 22B0h) [reset = X] FSM_PGM_MAXPUL is shown in Figure 7-114 and described in Table 7-111. Internal. Only to be used through TI provided API. Figure 7-114. FSM_PGM_MAXPUL Register 31 30 29 28 27 26 25 15 14 13 RESERVED R-X 12 11 10 9 24 23 RESERVED R-X 8 7 22 21 20 19 18 17 16 6 5 4 FSM_PGM_MAXPUL R-X 3 2 1 0 Table 7-111.
PAGE 650
VIMS Registers www.ti.com 7.7.2.105 FSM_EXECUTE Register (Offset = 22B4h) [reset = X] FSM_EXECUTE is shown in Figure 7-115 and described in Table 7-112. Internal. Only to be used through TI provided API. Figure 7-115. FSM_EXECUTE Register 31 30 29 28 27 15 14 13 12 11 26 25 RESERVED R-X 10 9 RESERVED R-X 24 23 22 21 20 19 8 7 6 5 4 3 18 17 SUSPEND_NOW R/W-Ah 2 1 FSMEXECUTE R/W-Ah 16 0 Table 7-112.
PAGE 651
VIMS Registers www.ti.com 7.7.2.106 FSM_SECTOR1 Register (Offset = 22C0h) [reset = FFFFFFFFh] FSM_SECTOR1 is shown in Figure 7-116 and described in Table 7-113. Internal. Only to be used through TI provided API. Figure 7-116. FSM_SECTOR1 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 FSM_SECTOR1 R/W-FFFFFFFFh 9 8 7 6 5 4 3 2 1 0 Table 7-113. FSM_SECTOR1 Register Field Descriptions Bit 31-0 Field Type Reset FSM_SECTOR1 R/W FFFFFFFFh Internal.
PAGE 652
VIMS Registers www.ti.com 7.7.2.107 FSM_SECTOR2 Register (Offset = 22C4h) [reset = X] FSM_SECTOR2 is shown in Figure 7-117 and described in Table 7-114. Internal. Only to be used through TI provided API. Figure 7-117. FSM_SECTOR2 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 FSM_SECTOR2 R/W-X 9 8 7 6 5 4 3 2 1 0 Table 7-114. FSM_SECTOR2 Register Field Descriptions Bit 31-0 652 Field Type Reset Description FSM_SECTOR2 R/W X Internal.
PAGE 653
VIMS Registers www.ti.com 7.7.2.108 FSM_BSLE0 Register (Offset = 22E0h) [reset = X] FSM_BSLE0 is shown in Figure 7-118 and described in Table 7-115. Internal. Only to be used through TI provided API. Figure 7-118. FSM_BSLE0 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 FSM_BSLE0 R/W-X 9 8 7 6 5 4 3 2 1 0 Table 7-115. FSM_BSLE0 Register Field Descriptions Bit 31-0 Field Type Reset Description FSM_BSLE0 R/W X Internal. Only to be used through TI provided API.
PAGE 654
VIMS Registers www.ti.com 7.7.2.109 FSM_BSLE1 Register (Offset = 22E4h) [reset = X] FSM_BSLE1 is shown in Figure 7-119 and described in Table 7-116. Internal. Only to be used through TI provided API. Figure 7-119. FSM_BSLE1 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 FSM_BSL1 R/W-X 9 8 7 6 5 4 3 2 1 0 Table 7-116. FSM_BSLE1 Register Field Descriptions Bit 31-0 654 Field Type Reset Description FSM_BSL1 R/W X Internal.
PAGE 655
VIMS Registers www.ti.com 7.7.2.110 FSM_BSLP0 Register (Offset = 22F0h) [reset = X] FSM_BSLP0 is shown in Figure 7-120 and described in Table 7-117. Internal. Only to be used through TI provided API. Figure 7-120. FSM_BSLP0 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 FSM_BSLP0 R/W-X 9 8 7 6 5 4 3 2 1 0 Table 7-117. FSM_BSLP0 Register Field Descriptions Bit 31-0 Field Type Reset Description FSM_BSLP0 R/W X Internal. Only to be used through TI provided API.
PAGE 656
VIMS Registers www.ti.com 7.7.2.111 FSM_BSLP1 Register (Offset = 22F4h) [reset = X] FSM_BSLP1 is shown in Figure 7-121 and described in Table 7-118. Internal. Only to be used through TI provided API. Figure 7-121. FSM_BSLP1 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 FSM_BSL1 R/W-X 9 8 7 6 5 4 3 2 1 0 Table 7-118. FSM_BSLP1 Register Field Descriptions Bit 31-0 656 Field Type Reset Description FSM_BSL1 R/W X Internal.
PAGE 657
VIMS Registers www.ti.com 7.7.2.112 FCFG_BANK Register (Offset = 2400h) [reset = X] FCFG_BANK is shown in Figure 7-122 and described in Table 7-119. Internal. Only to be used through TI provided API. Figure 7-122. FCFG_BANK Register 31 30 23 22 21 EE_BANK_WIDTH R-X 15 14 7 29 13 28 27 EE_BANK_WIDTH R-X 26 25 24 20 18 17 EE_NUM_BANK R-X 16 10 9 8 2 1 MAIN_NUM_BANK R-1h 0 19 12 11 MAIN_BANK_WIDTH R-40h 6 5 MAIN_BANK_WIDTH R-40h 4 3 Table 7-119.
PAGE 658
VIMS Registers www.ti.com 7.7.2.113 FCFG_WRAPPER Register (Offset = 2404h) [reset = X] FCFG_WRAPPER is shown in Figure 7-123 and described in Table 7-120. Internal. Only to be used through TI provided API. Figure 7-123.
PAGE 659
VIMS Registers www.ti.com 7.7.2.114 FCFG_BNK_TYPE Register (Offset = 2408h) [reset = X] FCFG_BNK_TYPE is shown in Figure 7-124 and described in Table 7-121. Internal. Only to be used through TI provided API. Figure 7-124. FCFG_BNK_TYPE Register 31 30 29 B7_TYPE R-X 28 27 26 25 B6_TYPE R-X 24 23 22 21 B5_TYPE R-X 20 19 18 17 B4_TYPE R-X 16 15 14 13 B3_TYPE R-X 12 11 10 9 B2_TYPE R-X 8 7 6 5 B1_TYPE R-X 4 3 2 1 B0_TYPE R-3h 0 Table 7-121.
PAGE 660
VIMS Registers www.ti.com 7.7.2.115 FCFG_B0_START Register (Offset = 2410h) [reset = X] FCFG_B0_START is shown in Figure 7-125 and described in Table 7-122. Internal. Only to be used through TI provided API. Figure 7-125. FCFG_B0_START Register 31 30 29 B0_MAX_SECTOR R-X 28 23 22 21 15 14 7 6 27 26 25 B0_MUX_FACTOR R-2h 24 20 19 B0_START_ADDR R-X 18 17 16 13 12 11 B0_START_ADDR R-X 10 9 8 5 4 3 B0_START_ADDR R-X 2 1 0 Table 7-122.
PAGE 661
VIMS Registers www.ti.com 7.7.2.116 FCFG_B1_START Register (Offset = 2414h) [reset = X] FCFG_B1_START is shown in Figure 7-126 and described in Table 7-123. Internal. Only to be used through TI provided API. Figure 7-126. FCFG_B1_START Register 31 30 29 B1_MAX_SECTOR R-X 28 23 22 21 15 14 7 6 27 26 25 B1_MUX_FACTOR R-X 24 20 19 B1_START_ADDR R-X 18 17 16 13 12 11 B1_START_ADDR R-X 10 9 8 5 4 3 B1_START_ADDR R-X 2 1 0 Table 7-123.
PAGE 662
VIMS Registers www.ti.com 7.7.2.117 FCFG_B2_START Register (Offset = 2418h) [reset = X] FCFG_B2_START is shown in Figure 7-127 and described in Table 7-124. Internal. Only to be used through TI provided API. Figure 7-127. FCFG_B2_START Register 31 30 29 B2_MAX_SECTOR R-X 28 23 22 21 15 14 7 6 27 26 25 B2_MUX_FACTOR R-X 24 20 19 B2_START_ADDR R-X 18 17 16 13 12 11 B2_START_ADDR R-X 10 9 8 5 4 3 B2_START_ADDR R-X 2 1 0 Table 7-124.
PAGE 663
VIMS Registers www.ti.com 7.7.2.118 FCFG_B3_START Register (Offset = 241Ch) [reset = X] FCFG_B3_START is shown in Figure 7-128 and described in Table 7-125. Internal. Only to be used through TI provided API. Figure 7-128. FCFG_B3_START Register 31 30 29 B3_MAX_SECTOR R-X 28 23 22 21 15 14 7 6 27 26 25 B3_MUX_FACTOR R-X 24 20 19 B3_START_ADDR R-X 18 17 16 13 12 11 B3_START_ADDR R-X 10 9 8 5 4 3 B3_START_ADDR R-X 2 1 0 Table 7-125.
PAGE 664
VIMS Registers www.ti.com 7.7.2.119 FCFG_B4_START Register (Offset = 2420h) [reset = X] FCFG_B4_START is shown in Figure 7-129 and described in Table 7-126. Internal. Only to be used through TI provided API. Figure 7-129. FCFG_B4_START Register 31 30 29 B4_MAX_SECTOR R-X 28 23 22 21 15 14 7 6 27 26 25 B4_MUX_FACTOR R-X 24 20 19 B4_START_ADDR R-X 18 17 16 13 12 11 B4_START_ADDR R-X 10 9 8 5 4 3 B4_START_ADDR R-X 2 1 0 Table 7-126.
PAGE 665
VIMS Registers www.ti.com 7.7.2.120 FCFG_B5_START Register (Offset = 2424h) [reset = X] FCFG_B5_START is shown in Figure 7-130 and described in Table 7-127. Internal. Only to be used through TI provided API. Figure 7-130. FCFG_B5_START Register 31 30 29 B5_MAX_SECTOR R-X 28 23 22 21 15 14 7 6 27 26 25 B5_MUX_FACTOR R-X 24 20 19 B5_START_ADDR R-X 18 17 16 13 12 11 B5_START_ADDR R-X 10 9 8 5 4 3 B5_START_ADDR R-X 2 1 0 Table 7-127.
PAGE 666
VIMS Registers www.ti.com 7.7.2.121 FCFG_B6_START Register (Offset = 2428h) [reset = X] FCFG_B6_START is shown in Figure 7-131 and described in Table 7-128. Internal. Only to be used through TI provided API. Figure 7-131. FCFG_B6_START Register 31 30 29 B6_MAX_SECTOR R-X 28 23 22 21 15 14 7 6 27 26 25 B6_MUX_FACTOR R-X 24 20 19 B6_START_ADDR R-X 18 17 16 13 12 11 B6_START_ADDR R-X 10 9 8 5 4 3 B6_START_ADDR R-X 2 1 0 Table 7-128.
PAGE 667
VIMS Registers www.ti.com 7.7.2.122 FCFG_B7_START Register (Offset = 242Ch) [reset = X] FCFG_B7_START is shown in Figure 7-132 and described in Table 7-129. Internal. Only to be used through TI provided API. Figure 7-132. FCFG_B7_START Register 31 30 29 B7_MAX_SECTOR R-X 28 23 22 21 15 14 7 6 27 26 25 B7_MUX_FACTOR R-X 24 20 19 B7_START_ADDR R-X 18 17 16 13 12 11 B7_START_ADDR R-X 10 9 8 5 4 3 B7_START_ADDR R-X 2 1 0 Table 7-129.
PAGE 668
VIMS Registers www.ti.com 7.7.2.123 FCFG_B0_SSIZE0 Register (Offset = 2430h) [reset = X] FCFG_B0_SSIZE0 is shown in Figure 7-133 and described in Table 7-130. Internal. Only to be used through TI provided API. Figure 7-133. FCFG_B0_SSIZE0 Register 31 30 29 RESERVED R-X 28 27 26 25 24 23 15 14 12 11 10 9 RESERVED R-X 8 7 13 22 21 20 B0_NUM_SECTORS R-20h 6 5 4 19 3 18 17 2 1 B0_SECT_SIZE R-4h 16 0 Table 7-130.
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ROM Functions www.ti.com 7.8 ROM Functions Overview of memory contents: • eFuse – Contains mostly critical chip-trim items needed before bootloader starts – Interfaced through the Flash module in the digital core • Flash trim • Ram repair • Analog trim (bandgap, brown-out, selected regulators, internal 48-MHz RC Oscillator) • JTAG TAP/DAP lock • CRC check (8 bits) – The only critical item here is the JTAG TAP/DAP lock that is locked by default (if a fuse is blown).
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SRAM 7.9 www.ti.com SRAM The CC26xx provides 20-kB single-cycle on-chip SRAM with full retention in all power modes, except shutdown. Retention can be configured in 4-kB blocks to save power. Because read-modify-write (RMW) operations are very time consuming, ARM has introduced bit-banding technology in the Cortex-M3 processor. With a bit-band-enabled processor, certain regions in the memory map (SRAM and peripheral space) can use address aliases to access individual bits in one atomic operation.
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Chapter 8 SWCU117A – February 2015 – Revised March 2015 Bootloader This section describes the CC26xx bootloader. Topic 8.1 8.2 ........................................................................................................................... Page Bootloader Functionality ................................................................................... 672 Bootloader Interfaces ........................................................................................
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Bootloader Functionality 8.1 www.ti.com Bootloader Functionality The CC26xx devices include a simple ROM-based bootloader that can communicate with an external device over the serial interfaces on the UART0 and SSI0 peripherals. The same communication protocol is used on both serial interfaces. These peripherals are IPs from ARM®. The main purpose of the ROM bootloader is to support functionality for downloading a flash image. 8.1.
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Bootloader Interfaces www.ti.com 8.2.1 Packet Handling The bootloader uses well-defined packets to ensure reliable communications with the external communicating program. All communications—with the exception of the UART auto-baud (see Section 8.2.2.1, UART Transport)—use these well-defined packets. The packets are always acknowledged or not acknowledged by the communicating devices with defined ACK/NACK bytes. The packets use the same format for receiving and sending packets.
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Bootloader Interfaces www.ti.com To illustrate packet handling, the basic packet format is shown in Figure 8-1. In Figure 8-1, the top line shows the device that is transmitting data; the bottom line is the response from the other device. In this case, a 6-byte packet is sent with the data shown in Figure 8-2. This data results in a checksum of 0x48+0x6f+0x6c+0x61 which, when truncated to 8 bits, is 0x84. The first byte transmitted holds the size of the packet in number of bytes.
PAGE 675
Bootloader Interfaces www.ti.com Table 8-3. Configuration of Serial Interfaces Signal QFN48 / 7x7 QFN32 / 5x5 QFN32 / 4x4 UART0 RX UART_RX DIO2 DIO1 DIO1 UART0 TX UART_TX DIO3 DIO0 DIO2 SSI0 Clk SSP_CLK DIO10 DIO10 DIO8 SSI0 Fss SSP_FSS DIO11 DIO9 DIO7 SSI0 RX SSP_RX DIO9 DIO11 DIO9 SSI0 TX SSP_TX DIO8 DIO12 DIO0 The bootloader will initially configure only the input pins on the two serial interfaces.
PAGE 676
Bootloader Interfaces www.ti.com The format used for SSI communications is the Motorola format with SPH set to 1 and SPO set to 1 (See the Stellaris Family data sheet for more information on this format). The SSI interface has a hardware requirement that limits the maximum rate of the SSI clock to be at most 1/12 the frequency of the SSI module clock (48 MHz / 12 = 4 MHz).
PAGE 677
Bootloader Interfaces www.ti.com Table 8-4. Supported Bootloader Commands (continued) Command Command Value Bytes in Packet COMMAND_CRC32 0x27 15 Calculates CRC32 over a specified memory area. The number of reads per memory location is specified. COMMAND_GET_CHIP_ID 0x28 3 Returns the 32-bit UserID from the AON_WUC JTAGUSERCODE register with MSB first. The ID is returned within a protocol packet.
PAGE 678
Bootloader Interfaces 8.2.3.2 www.ti.com COMMAND_DOWNLOAD This command is sent to the bootloader to indicate where to store data in flash and how many bytes will be sent by the COMMAND_SEND_DATA commands that follow. The command consists of two 32-bit values that are both transferred MSB first. The first 32-bit value is the address to start programming data into, while the second is the 32-bit size of the data that will be sent.
PAGE 679
Bootloader Interfaces www.ti.com NOTE: Sectors protected by write-protect bits in FCFG1 and CCFG are not erased. If the sector address of the top sector (including the CCFG area) is specified, the actual erase is followed by a programming operation of all the DAP and TAP configuration parameters and the BOOTLOADER_ENABLE parameter within CCFG with values equal to the corresponding parameters within FCFG1.
PAGE 680
Bootloader Interfaces 8.2.3.6 www.ti.com COMMAND_RESET This command tells the bootloader to perform a reset of the CC26xx MCU domain. Use this command after downloading a new flash image to the CC26xx to cause the new application to start from a reset. The normal boot sequence occurs and the flash image runs as if from a hardware reset. Also, use this command to reset the bootloader if a critical error occurs and the host device wants to restart communication with the bootloader.
PAGE 681
Bootloader Interfaces www.ti.com 8.2.3.8 COMMAND_CRC32 This command checks a flash area using CRC32. The command consists of three 32-bit values that are all transferred MSB first. The first 32-bit value is the address in memory from where the CRC32 calculation starts, the second 32-bit value is the number of bytes comprised by the CRC32 calculation, and the third 32-bit value is the number of read repeats for each data location.
PAGE 682
Bootloader Interfaces 8.2.3.9 www.ti.com COMMAND_BANK_ERASE This command does not perform any erase operation if the CCFG parameter BANK_ERASE_DIS is set. When COMMAND_BANK_ERASE is not set, this command will erase all main bank flash sectors including CCFG not protected by write-protect bits in FCFG1 and CCFG. The command sends the ACK in response to the command after the actual erase operation is performed.
PAGE 683
Bootloader Interfaces www.ti.com NOTE: The COMMAND_SET_CCFG command can only change CCFG parameter value bits from 1 to 0. Attempting to change any bit from 0 to 1 results in an error status which can be observed by a following COMMAND_GET_STATUS command. The only way to change CCFG parameter value bits from 0 to 1 is by erasing the complete CCFG flash sector. The command sends the ACK signal in response to the command after the actual flash programming has terminated.
PAGE 684
Bootloader Interfaces www.ti.com Table 8-6. Defined CCFG Field IDs and Field values (continued) Field ID 684 Field Value Description 7: ID_PBIST2_TAP_LCK Bit[31:8] – Don’t care Bit[7:0] – 0xC5 = TAP unlocked Any other value than 0xC5 will force a locked TAP after a following boot sequence. 8: ID_BANK_ERASE_DIS Bit[31:1] – Don’t care Bit[0] – 0 = Bank erase disable If 0 the COMMAND_BANK_ERASE bootloader command will not force any erase operation.
PAGE 685
Chapter 9 SWCU117A – February 2015 – Revised March 2015 Device Configuration The Device Configuration chapter describes the device configuration areas. The Factory Configuration (FCFG) and Customer Configuration (CCFG) areas are located in flash. The FCFG is set by Texas Instruments during device production and contains device specific trim values and configuration. The CCFG should be set by the application and contains configuration parameters for the ROM bootcode, device hardware, and device firmware.
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Customer Configuration (CCFG) 9.1 www.ti.com Customer Configuration (CCFG) • • • • • Image valid bit (normally set by the programming tool) Failure analysis access configuration Custom MAC address Bootloader configuration TAP and DAP access configuration In TI distributed software, the CCFG parameters are set at compile time in the ccfg.c file. The CCFG settings are set by default to allow full debugging of the device. The CCFG settings are not recommended for production.
PAGE 687
Customer Configuration (CCFG) www.ti.com 9.1.1 CCFG Registers Table 9-1 lists the memory-mapped registers for the CCFG. All register offset addresses not listed in Table 9-1 should be considered as reserved locations and the register contents should not be modified. Table 9-1. CCFG Registers Offset Acronym Register Name FACh MODE_CONF_1 Mode Configuration 1 Section 9.1.1.1 Section FB0h SIZE_AND_DIS_FLAGS CCFG Size and Disable Flags Section 9.1.1.
PAGE 688
Customer Configuration (CCFG) 9.1.1.1 www.ti.com MODE_CONF_1 Register (Offset = FACh) [reset = FFFBFFFFh] MODE_CONF_1 is shown in Figure 9-1 and described in Table 9-2. Mode Configuration 1 Figure 9-1.
PAGE 689
Customer Configuration (CCFG) www.ti.com 9.1.1.2 SIZE_AND_DIS_FLAGS Register (Offset = FB0h) [reset = FFFFFFFFh] SIZE_AND_DIS_FLAGS is shown in Figure 9-2 and described in Table 9-3. CCFG Size and Disable Flags Figure 9-2.
PAGE 690
Customer Configuration (CCFG) 9.1.1.3 www.ti.com MODE_CONF Register (Offset = FB4h) [reset = FFFFFFFFh] MODE_CONF is shown in Figure 9-3 and described in Table 9-4. Mode Configuration 0 Figure 9-3.
PAGE 691
Customer Configuration (CCFG) www.ti.com Table 9-4. MODE_CONF Register Field Descriptions (continued) Bit Field Type Reset Description XOSC_FREQ R/W 3h Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. 17 XOSC_CAP_MOD R/W 1h Enable modification (delta) to XOSC cap-array. Value specified in XOSC_CAPARRAY_DELTA.
PAGE 692
Customer Configuration (CCFG) 9.1.1.4 www.ti.com VOLT_LOAD_0 Register (Offset = FB8h) [reset = FFFFFFFFh] VOLT_LOAD_0 is shown in Figure 9-4 and described in Table 9-5. Voltage Load 0 Enabled by MODE_CONF.VDDR_EXT_LOAD. Figure 9-4. VOLT_LOAD_0 Register 31 30 29 28 27 VDDR_EXT_TP45 R/W-FFh 26 25 24 23 22 21 20 19 VDDR_EXT_TP25 R/W-FFh 18 17 16 15 14 13 12 11 VDDR_EXT_TP5 R/W-FFh 10 9 8 7 6 5 4 3 VDDR_EXT_TM15 R/W-FFh 2 1 0 Table 9-5.
PAGE 693
Customer Configuration (CCFG) www.ti.com 9.1.1.5 VOLT_LOAD_1 Register (Offset = FBCh) [reset = FFFFFFFFh] VOLT_LOAD_1 is shown in Figure 9-5 and described in Table 9-6. Voltage Load 1 Enabled by MODE_CONF.VDDR_EXT_LOAD. Figure 9-5. VOLT_LOAD_1 Register 31 30 29 28 27 26 VDDR_EXT_TP125 R/W-FFh 25 24 23 22 21 20 19 18 VDDR_EXT_TP105 R/W-FFh 17 16 15 14 13 12 11 VDDR_EXT_TP85 R/W-FFh 9 8 7 6 5 4 3 VDDR_EXT_TP65 R/W-FFh 1 0 10 2 Table 9-6.
PAGE 694
Customer Configuration (CCFG) 9.1.1.6 www.ti.com RTC_OFFSET Register (Offset = FC0h) [reset = FFFFFFFFh] RTC_OFFSET is shown in Figure 9-6 and described in Table 9-7. Real Time Clock Offset Enabled by MODE_CONF.RTC_COMP. Figure 9-6. RTC_OFFSET Register 31 30 29 15 14 13 28 27 12 11 RTC_COMP_P1 R/W-FFh 26 25 10 9 24 23 RTC_COMP_P0 R/W-FFFFh 8 7 22 21 6 5 20 19 4 3 RTC_COMP_P2 R/W-FFh 18 17 16 2 1 0 Table 9-7.
PAGE 695
Customer Configuration (CCFG) www.ti.com 9.1.1.7 FREQ_OFFSET Register (Offset = FC4h) [reset = FFFFFFFFh] FREQ_OFFSET is shown in Figure 9-7 and described in Table 9-8. Frequency Offset Figure 9-7. FREQ_OFFSET Register 31 30 29 15 14 13 28 27 12 11 HF_COMP_P1 R/W-FFh 26 25 10 9 24 23 HF_COMP_P0 R/W-FFFFh 8 7 22 21 6 5 20 19 4 3 HF_COMP_P2 R/W-FFh 18 17 16 2 1 0 Table 9-8.
PAGE 696
Customer Configuration (CCFG) 9.1.1.8 www.ti.com IEEE_MAC_0 Register (Offset = FC8h) [reset = FFFFFFFFh] IEEE_MAC_0 is shown in Figure 9-8 and described in Table 9-9. IEEE MAC Address 0 Figure 9-8. IEEE_MAC_0 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ADDR R/W-FFFFFFFFh 9 8 7 6 5 4 3 2 1 0 Table 9-9. IEEE_MAC_0 Register Field Descriptions 696 Bit Field Type Reset 31-0 ADDR R/W FFFFFFFFh Bits[31:0] of the 64-bits custom IEEE MAC address.
PAGE 697
Customer Configuration (CCFG) www.ti.com 9.1.1.9 IEEE_MAC_1 Register (Offset = FCCh) [reset = FFFFFFFFh] IEEE_MAC_1 is shown in Figure 9-9 and described in Table 9-10. IEEE MAC Address 1 Figure 9-9. IEEE_MAC_1 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ADDR R/W-FFFFFFFFh 9 8 7 6 5 4 3 2 1 0 Table 9-10. IEEE_MAC_1 Register Field Descriptions Bit Field Type Reset 31-0 ADDR R/W FFFFFFFFh Bits[63:32] of the 64-bits custom IEEE MAC address.
PAGE 698
Customer Configuration (CCFG) www.ti.com 9.1.1.10 IEEE_BLE_0 Register (Offset = FD0h) [reset = FFFFFFFFh] IEEE_BLE_0 is shown in Figure 9-10 and described in Table 9-11. IEEE BLE Address 0 Figure 9-10. IEEE_BLE_0 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ADDR R/W-FFFFFFFFh 9 8 7 6 5 4 3 2 1 0 Table 9-11. IEEE_BLE_0 Register Field Descriptions 698 Bit Field Type Reset 31-0 ADDR R/W FFFFFFFFh Bits[31:0] of the 64-bits custom IEEE BLE address.
PAGE 699
Customer Configuration (CCFG) www.ti.com 9.1.1.11 IEEE_BLE_1 Register (Offset = FD4h) [reset = FFFFFFFFh] IEEE_BLE_1 is shown in Figure 9-11 and described in Table 9-12. IEEE BLE Address 1 Figure 9-11. IEEE_BLE_1 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ADDR R/W-FFFFFFFFh 9 8 7 6 5 4 3 2 1 0 Table 9-12. IEEE_BLE_1 Register Field Descriptions Bit Field Type Reset 31-0 ADDR R/W FFFFFFFFh Bits[63:32] of the 64-bits custom IEEE BLE address.
PAGE 700
Customer Configuration (CCFG) www.ti.com 9.1.1.12 BL_CONFIG Register (Offset = FD8h) [reset = C5FFFFFFh] BL_CONFIG is shown in Figure 9-12 and described in Table 9-13. Bootloader Configuration Configures the functionality of the ROM boot loader. If both the boot loader is enabled and the failure analysis is enabled it is possible to force entry of the ROM boot loader even if a valid image is present in flash. Figure 9-12.
PAGE 701
Customer Configuration (CCFG) www.ti.com 9.1.1.13 ERASE_CONF Register (Offset = FDCh) [reset = FFFFFFFFh] ERASE_CONF is shown in Figure 9-13 and described in Table 9-14. Erase Configuration Figure 9-13. ERASE_CONF Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 CHIP_ERASE_ DIS_N R/W-1h 3 2 1 0 BANK_ERASE _DIS_N R/W-1h RESERVED R/W-7FFFFFh 23 22 21 20 RESERVED R/W-7FFFFFh 15 14 13 12 RESERVED R/W-7FFFFFh 7 6 5 4 RESERVED R/W-7Fh Table 9-14.
PAGE 702
Customer Configuration (CCFG) www.ti.com 9.1.1.14 CCFG_TI_OPTIONS Register (Offset = FE0h) [reset = FFFFFFC5h] CCFG_TI_OPTIONS is shown in Figure 9-14 and described in Table 9-15. TI Options Figure 9-14. CCFG_TI_OPTIONS Register 31 30 29 15 14 13 28 27 12 11 RESERVED R/W-FFFFFFh 26 25 10 9 24 23 RESERVED R/W-FFFFFFh 8 7 22 21 6 5 20 19 4 3 TI_FA_ENABLE R/W-C5h 18 17 16 2 1 0 Table 9-15.
PAGE 703
Customer Configuration (CCFG) www.ti.com 9.1.1.15 CCFG_TAP_DAP_0 Register (Offset = FE4h) [reset = FFC5C5C5h] CCFG_TAP_DAP_0 is shown in Figure 9-15 and described in Table 9-16. Test Access Points Enable 0 Figure 9-15. CCFG_TAP_DAP_0 Register 31 30 29 15 14 13 28 27 RESERVED R/W-FFh 26 25 24 23 22 21 20 19 18 CPU_DAP_ENABLE R/W-C5h 17 16 12 11 10 PRCM_TAP_ENABLE R/W-C5h 9 8 7 6 5 4 3 2 TEST_TAP_ENABLE R/W-C5h 1 0 Table 9-16.
PAGE 704
Customer Configuration (CCFG) www.ti.com 9.1.1.16 CCFG_TAP_DAP_1 Register (Offset = FE8h) [reset = FFC5C5C5h] CCFG_TAP_DAP_1 is shown in Figure 9-16 and described in Table 9-17. Test Access Points Enable 1 Figure 9-16. CCFG_TAP_DAP_1 Register 31 30 29 15 14 13 28 27 RESERVED R/W-FFh 26 25 24 23 22 21 20 19 18 PBIST2_TAP_ENABLE R/W-C5h 17 16 12 11 10 PBIST1_TAP_ENABLE R/W-C5h 9 8 7 6 5 4 3 2 WUC_TAP_ENABLE R/W-C5h 1 0 Table 9-17.
PAGE 705
Customer Configuration (CCFG) www.ti.com 9.1.1.17 IMAGE_VALID_CONF Register (Offset = FECh) [reset = FFFFFFFFh] IMAGE_VALID_CONF is shown in Figure 9-17 and described in Table 9-18. Image Valid Figure 9-17. IMAGE_VALID_CONF Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 IMAGE_VALID R/W-FFFFFFFFh 9 8 7 6 5 4 3 2 1 0 Table 9-18.
PAGE 706
Customer Configuration (CCFG) www.ti.com 9.1.1.18 CCFG_PROT_31_0 Register (Offset = FF0h) [reset = FFFFFFFFh] CCFG_PROT_31_0 is shown in Figure 9-18 and described in Table 9-19. Protect Sectors 0-31 Each bit write protects one sector from being both programmed and erased. Bit must be set to 0 in order to enable sector write protect. The sector write protection is enabled by setting corresponding bit in the FSM_BSLE0- and FSM_BSLP0-registers in the flash controller. Figure 9-18.
PAGE 707
Customer Configuration (CCFG) www.ti.com Table 9-19.
PAGE 708
Customer Configuration (CCFG) www.ti.com 9.1.1.19 CCFG_PROT_63_32 Register (Offset = FF4h) [reset = FFFFFFFFh] CCFG_PROT_63_32 is shown in Figure 9-19 and described in Table 9-20. Protect Sectors 32-63 Each bit write protects one sector from being both programmed and erased. Bit must be set to 0 in order to enable sector write protect. The sector write protection is enabled by setting corresponding bit in the FSM_BSLE1- and FSM_BSLP1-registers in the flash controller.
PAGE 709
Customer Configuration (CCFG) www.ti.com Table 9-20.
PAGE 710
Customer Configuration (CCFG) www.ti.com 9.1.1.20 CCFG_PROT_95_64 Register (Offset = FF8h) [reset = FFFFFFFFh] CCFG_PROT_95_64 is shown in Figure 9-20 and described in Table 9-21. Protect Sectors 64-95 Each bit write protects one sector from being both programmed and erased. Bit must be set to 0 in order to enable sector write protect. Not in use on CC26xx. Figure 9-20.
PAGE 711
Customer Configuration (CCFG) www.ti.com Table 9-21.
PAGE 712
Customer Configuration (CCFG) www.ti.com 9.1.1.21 CCFG_PROT_127_96 Register (Offset = FFCh) [reset = FFFFFFFFh] CCFG_PROT_127_96 is shown in Figure 9-21 and described in Table 9-22. Protect Sectors 96-127 Each bit write protects one sector from being both programmed and erased. Bit must be set to 0 in order to enable sector write protect. Not in use on CC26xx. Figure 9-21.
PAGE 713
Factory Configuration (FCFG) www.ti.com Table 9-22. CCFG_PROT_127_96 Register Field Descriptions (continued) Bit 9.
PAGE 714
Factory Configuration (FCFG) www.ti.com 9.2.1 FCFG1 Registers Table 9-23 lists the memory-mapped registers for the FCFG1. All register offset addresses not listed in Table 9-23 should be considered as reserved locations and the register contents should not be modified. Table 9-23. FCFG1 Registers Offset Acronym Register Name C4h CONFIG_RF_FRONTEND_DIV5 Configuration of RF Frontend in Divide-by-5 Mode Section 9.2.1.
PAGE 715
Factory Configuration (FCFG) www.ti.com Table 9-23. FCFG1 Registers (continued) Offset Acronym Register Name 2F0h MAC_15_4_0 MAC IEEE 802.15.4 Address 0 Section 9.2.1.44 2F4h MAC_15_4_1 MAC IEEE 802.15.4 Address 1 Section 9.2.1.45 308h FLASH_OTP_DATA4 Flash OTP Data 4 Section 9.2.1.46 30Ch MISC_TRIM Miscellaneous Trim Parameters Section 9.2.1.47 310h RCOSC_HF_TEMPCOMP RCOSC HF Temperature Compensation Section 9.2.1.
PAGE 716
Factory Configuration (FCFG) 9.2.1.1 www.ti.com CONFIG_RF_FRONTEND_DIV5 Register (Offset = C4h) [reset = FFFFFFFFh] CONFIG_RF_FRONTEND_DIV5 is shown in Figure 9-22 and described in Table 9-24. Configuration of RF Frontend in Divide-by-5 Mode Divide-by-5 mode is only available for CC13xx. Figure 9-22.
PAGE 717
Factory Configuration (FCFG) www.ti.com 9.2.1.2 CONFIG_RF_FRONTEND_DIV6 Register (Offset = C8h) [reset = FFFFFFFFh] CONFIG_RF_FRONTEND_DIV6 is shown in Figure 9-23 and described in Table 9-25. Configuration of RF Frontend in Divide-by-6 Mode Divide-by-6 mode is only available for CC13xx. Figure 9-23.
PAGE 718
Factory Configuration (FCFG) 9.2.1.3 www.ti.com CONFIG_RF_FRONTEND_DIV10 Register (Offset = CCh) [reset = FFFFFFFFh] CONFIG_RF_FRONTEND_DIV10 is shown in Figure 9-24 and described in Table 9-26. Configuration of RF Frontend in Divide-by-10 Mode Divide-by-10 mode is only available for CC13xx. Figure 9-24.
PAGE 719
Factory Configuration (FCFG) www.ti.com 9.2.1.4 CONFIG_RF_FRONTEND_DIV12 Register (Offset = D0h) [reset = FFFFFFFFh] CONFIG_RF_FRONTEND_DIV12 is shown in Figure 9-25 and described in Table 9-27. Configuration of RF Frontend in Divide-by-12 Mode Divide-by-12 mode is only available for CC13xx. Figure 9-25.
PAGE 720
Factory Configuration (FCFG) 9.2.1.5 www.ti.com CONFIG_RF_FRONTEND_DIV15 Register (Offset = D4h) [reset = FFFFFFFFh] CONFIG_RF_FRONTEND_DIV15 is shown in Figure 9-26 and described in Table 9-28. Configuration of RF Frontend in Divide-by-15 Mode Divide-by-15 mode is only available for CC13xx. Figure 9-26.
PAGE 721
Factory Configuration (FCFG) www.ti.com 9.2.1.6 CONFIG_RF_FRONTEND_DIV30 Register (Offset = D8h) [reset = FFFFFFFFh] CONFIG_RF_FRONTEND_DIV30 is shown in Figure 9-27 and described in Table 9-29. Configuration of RF Frontend in Divide-by-30 Mode Divide-by-30 mode is only available for CC13xx. Figure 9-27.
PAGE 722
Factory Configuration (FCFG) 9.2.1.7 www.ti.com CONFIG_SYNTH_DIV5 Register (Offset = DCh) [reset = FFFFFFFFh] CONFIG_SYNTH_DIV5 is shown in Figure 9-28 and described in Table 9-30. Configuration of Synthesizer in Divide-by-5 Mode Divide-by-5 mode is only available for CC13xx. Figure 9-28.
PAGE 723
Factory Configuration (FCFG) www.ti.com 9.2.1.8 CONFIG_SYNTH_DIV6 Register (Offset = E0h) [reset = FFFFFFFFh] CONFIG_SYNTH_DIV6 is shown in Figure 9-29 and described in Table 9-31. Configuration of Synthesizer in Divide-by-6 Mode Divide-by-6 mode is only available for CC13xx. Figure 9-29.
PAGE 724
Factory Configuration (FCFG) 9.2.1.9 www.ti.com CONFIG_SYNTH_DIV10 Register (Offset = E4h) [reset = FFFFFFFFh] CONFIG_SYNTH_DIV10 is shown in Figure 9-30 and described in Table 9-32. Configuration of Synthesizer in Divide-by-10 Mode Divide-by-10 mode is only available for CC13xx. Figure 9-30.
PAGE 725
Factory Configuration (FCFG) www.ti.com 9.2.1.10 CONFIG_SYNTH_DIV12 Register (Offset = E8h) [reset = FFFFFFFFh] CONFIG_SYNTH_DIV12 is shown in Figure 9-31 and described in Table 9-33. Configuration of Synthesizer in Divide-by-12 Mode Divide-by-12 mode is only available for CC13xx. Figure 9-31.
PAGE 726
Factory Configuration (FCFG) www.ti.com 9.2.1.11 CONFIG_SYNTH_DIV15 Register (Offset = ECh) [reset = FFFFFFFFh] CONFIG_SYNTH_DIV15 is shown in Figure 9-32 and described in Table 9-34. Configuration of Synthesizer in Divide-by-15 Mode Divide-by-15 mode is only available for CC13xx. Figure 9-32.
PAGE 727
Factory Configuration (FCFG) www.ti.com 9.2.1.12 CONFIG_SYNTH_DIV30 Register (Offset = F0h) [reset = FFFFFFFFh] CONFIG_SYNTH_DIV30 is shown in Figure 9-33 and described in Table 9-35. Configuration of Synthesizer in Divide-by-30 Mode Divide-by-30 mode is only available for CC13xx. Figure 9-33.
PAGE 728
Factory Configuration (FCFG) www.ti.com 9.2.1.13 CONFIG_MISC_ADC_DIV5 Register (Offset = F4h) [reset = FFFFFFFFh] CONFIG_MISC_ADC_DIV5 is shown in Figure 9-34 and described in Table 9-36. Configuration of IFADC in Divide-by-5 Mode Divide-by-5 mode is only available for CC13xx. Figure 9-34.
PAGE 729
Factory Configuration (FCFG) www.ti.com 9.2.1.14 CONFIG_MISC_ADC_DIV6 Register (Offset = F8h) [reset = FFFFFFFFh] CONFIG_MISC_ADC_DIV6 is shown in Figure 9-35 and described in Table 9-37. Configuration of IFADC in Divide-by-6 Mode Divide-by-6 mode is only available for CC13xx. Figure 9-35.
PAGE 730
Factory Configuration (FCFG) www.ti.com 9.2.1.15 CONFIG_MISC_ADC_DIV10 Register (Offset = FCh) [reset = FFFFFFFFh] CONFIG_MISC_ADC_DIV10 is shown in Figure 9-36 and described in Table 9-38. Configuration of IFADC in Divide-by-10 Mode Divide-by-10 mode is only available for CC13xx. Figure 9-36.
PAGE 731
Factory Configuration (FCFG) www.ti.com 9.2.1.16 CONFIG_MISC_ADC_DIV12 Register (Offset = 100h) [reset = FFFFFFFFh] CONFIG_MISC_ADC_DIV12 is shown in Figure 9-37 and described in Table 9-39. Configuration of IFADC in Divide-by-12 Mode Divide-by-12 mode is only available for CC13xx. Figure 9-37.
PAGE 732
Factory Configuration (FCFG) www.ti.com 9.2.1.17 CONFIG_MISC_ADC_DIV15 Register (Offset = 104h) [reset = FFFFFFFFh] CONFIG_MISC_ADC_DIV15 is shown in Figure 9-38 and described in Table 9-40. Configuration of IFADC in Divide-by-15 Mode Divide-by-15 mode is only available for CC13xx. Figure 9-38.
PAGE 733
Factory Configuration (FCFG) www.ti.com 9.2.1.18 CONFIG_MISC_ADC_DIV30 Register (Offset = 108h) [reset = FFFFFFFFh] CONFIG_MISC_ADC_DIV30 is shown in Figure 9-39 and described in Table 9-41. Configuration of IFADC in Divide-by-30 Mode Divide-by-30 mode is only available for CC13xx. Figure 9-39.
PAGE 734
Factory Configuration (FCFG) www.ti.com 9.2.1.19 SHDW_DIE_ID_0 Register (Offset = 118h) [reset = 0h] SHDW_DIE_ID_0 is shown in Figure 9-40 and described in Table 9-42. Shadow of EFUSE:DIE_ID_0 Figure 9-40. SHDW_DIE_ID_0 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ID_31_0 R-0h 9 8 7 6 5 4 3 2 1 0 Table 9-42.
PAGE 735
Factory Configuration (FCFG) www.ti.com 9.2.1.20 SHDW_DIE_ID_1 Register (Offset = 11Ch) [reset = 0h] SHDW_DIE_ID_1 is shown in Figure 9-41 and described in Table 9-43. Shadow of EFUSE:DIE_ID_1 Figure 9-41. SHDW_DIE_ID_1 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ID_63_32 R-0h 9 8 7 6 5 4 3 2 1 0 Table 9-43.
PAGE 736
Factory Configuration (FCFG) www.ti.com 9.2.1.21 SHDW_DIE_ID_2 Register (Offset = 120h) [reset = 0h] SHDW_DIE_ID_2 is shown in Figure 9-42 and described in Table 9-44. Shadow of EFUSE:DIE_ID_2 Figure 9-42. SHDW_DIE_ID_2 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ID_95_64 R-0h 9 8 7 6 5 4 3 2 1 0 Table 9-44.
PAGE 737
Factory Configuration (FCFG) www.ti.com 9.2.1.22 SHDW_DIE_ID_3 Register (Offset = 124h) [reset = 0h] SHDW_DIE_ID_3 is shown in Figure 9-43 and described in Table 9-45. Shadow of EFUSE:DIE_ID_3 Figure 9-43. SHDW_DIE_ID_3 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ID_127_96 R-0h 9 8 7 6 5 4 3 2 1 0 Table 9-45.
PAGE 738
Factory Configuration (FCFG) www.ti.com 9.2.1.23 SHDW_OSC_BIAS_LDO_TRIM Register (Offset = 138h) [reset = 0h] SHDW_OSC_BIAS_LDO_TRIM is shown in Figure 9-44 and described in Table 9-46. Shadow of EFUSE:OSC_BIAS_LDO_TRIM Figure 9-44.
PAGE 739
Factory Configuration (FCFG) www.ti.com 9.2.1.24 SHDW_ANA_TRIM Register (Offset = 13Ch) [reset = 0h] SHDW_ANA_TRIM is shown in Figure 9-45 and described in Table 9-47. Shadow of EFUSE:ANA_TRIM Figure 9-45.
PAGE 740
Factory Configuration (FCFG) www.ti.com 9.2.1.25 FLASH_NUMBER Register (Offset = 164h) [reset = 0h] FLASH_NUMBER is shown in Figure 9-46 and described in Table 9-48. Figure 9-46. FLASH_NUMBER Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 LOT_NUMBER R-0h 9 8 7 6 5 4 3 2 1 0 Table 9-48. FLASH_NUMBER Register Field Descriptions Bit 31-0 740 Field Type Reset Description LOT_NUMBER R 0h Number of the manufacturing lot that produced this unit.
PAGE 741
Factory Configuration (FCFG) www.ti.com 9.2.1.26 FLASH_COORDINATE Register (Offset = 16Ch) [reset = 0h] FLASH_COORDINATE is shown in Figure 9-47 and described in Table 9-49. Figure 9-47. FLASH_COORDINATE Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 XCOORDINATE YCOORDINATE R-0h R-0h 4 3 2 1 0 Table 9-49. FLASH_COORDINATE Register Field Descriptions Field Type Reset Description 31-16 Bit XCOORDINATE R 0h X coordinate of this unit on the wafer.
PAGE 742
Factory Configuration (FCFG) www.ti.com 9.2.1.27 FLASH_E_P Register (Offset = 170h) [reset = 17331A33h] FLASH_E_P is shown in Figure 9-48 and described in Table 9-50. Flash Erase and Program Setup Time Figure 9-48. FLASH_E_P Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PSU ESU PVSU R-17h R-33h R-1Ah 9 8 7 6 5 4 3 EVSU R-33h 2 1 0 Table 9-50.
PAGE 743
Factory Configuration (FCFG) www.ti.com 9.2.1.28 FLASH_C_E_P_R Register (Offset = 174h) [reset = X] FLASH_C_E_P_R is shown in Figure 9-49 and described in Table 9-51. Flash Compaction, Execute, Program and Read Figure 9-49. FLASH_C_E_P_R Register 31 30 29 28 27 26 25 24 23 22 11 10 9 8 7 6 21 RVSU R-Ah 15 14 13 A_EXEZ_SETUP R-2h 12 5 20 19 PV_ACCESS R-Ah 4 3 18 17 16 2 1 0 CVSU R-X Table 9-51.
PAGE 744
Factory Configuration (FCFG) www.ti.com 9.2.1.29 FLASH_P_R_PV Register (Offset = 178h) [reset = X] FLASH_P_R_PV is shown in Figure 9-50 and described in Table 9-52. Flash Program, Read, and Program Verify Figure 9-50. FLASH_P_R_PV Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PH RH PVH R-2h R-6Eh R-2h 9 8 7 6 5 4 3 PVH2 R-X 2 1 0 Table 9-52.
PAGE 745
Factory Configuration (FCFG) www.ti.com 9.2.1.30 FLASH_EH_SEQ Register (Offset = 17Ch) [reset = X] FLASH_EH_SEQ is shown in Figure 9-51 and described in Table 9-53. Flash Erase Hold and Sequence Figure 9-51. FLASH_EH_SEQ Register 31 30 29 28 27 26 25 24 23 22 21 20 EH R-2h 15 14 13 VSTAT R-Fh 12 19 18 17 16 3 2 1 0 SEQ R-X 11 10 9 8 7 6 5 SM_FREQUENCY R-X 4 Table 9-53.
PAGE 746
Factory Configuration (FCFG) www.ti.com 9.2.1.31 FLASH_VHV_E Register (Offset = 180h) [reset = X] FLASH_VHV_E is shown in Figure 9-52 and described in Table 9-54. Flash VHV Erase Figure 9-52. FLASH_VHV_E Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 VHV_E_START VHV_E_STEP_HIGHT R-X R-1h 4 3 2 1 0 Table 9-54. FLASH_VHV_E Register Field Descriptions Bit 746 Field Type Reset Description 31-16 VHV_E_START R X Starting VHV-Erase CT for stairstep erase.
PAGE 747
Factory Configuration (FCFG) www.ti.com 9.2.1.32 FLASH_PP Register (Offset = 184h) [reset = X] FLASH_PP is shown in Figure 9-53 and described in Table 9-55. Flash Program Pulse Figure 9-53. FLASH_PP Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PUMP_SU RESERVED R-X R-0h 9 8 7 6 MAX_PP R-14h 5 4 3 2 1 0 Table 9-55.
PAGE 748
Factory Configuration (FCFG) www.ti.com 9.2.1.33 FLASH_PROG_EP Register (Offset = 188h) [reset = FA00010h] FLASH_PROG_EP is shown in Figure 9-54 and described in Table 9-56. Flash Program and Erase Pulse Figure 9-54. FLASH_PROG_EP Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 MAX_EP PROGRAM_PW R-FA0h R-10h 4 3 2 1 0 Table 9-56.
PAGE 749
Factory Configuration (FCFG) www.ti.com 9.2.1.34 FLASH_ERA_PW Register (Offset = 18Ch) [reset = FA0h] FLASH_ERA_PW is shown in Figure 9-55 and described in Table 9-57. Flash Erase Pulse Width Figure 9-55. FLASH_ERA_PW Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ERASE_PW R-FA0h 9 8 7 6 5 4 3 2 1 0 Table 9-57. FLASH_ERA_PW Register Field Descriptions Bit 31-0 Field Type Reset Description ERASE_PW R FA0h Erase pulse width in half-microseconds.
PAGE 750
Factory Configuration (FCFG) www.ti.com 9.2.1.35 FLASH_VHV Register (Offset = 190h) [reset = X] FLASH_VHV is shown in Figure 9-56 and described in Table 9-58. Flash VHV Figure 9-56. FLASH_VHV Register 31 30 29 RESERVED R-X 28 27 26 25 TRIM13_P R-0h 24 23 22 21 RESERVED R-X 20 19 18 17 VHV_P R-0h 16 15 14 13 RESERVED R-X 12 11 10 9 TRIM13_E R-0h 8 7 6 5 RESERVED R-X 4 3 2 0 1 VHV_E R-4h Table 9-58.
PAGE 751
Factory Configuration (FCFG) www.ti.com 9.2.1.36 FLASH_VHV_PV Register (Offset = 194h) [reset = X] FLASH_VHV_PV is shown in Figure 9-57 and described in Table 9-59. Flash VHV Program Verify Figure 9-57. FLASH_VHV_PV Register 31 30 29 RESERVED R-X 28 15 14 12 11 VCG2P5 R-0h 13 27 26 25 TRIM13_PV R-0h 24 23 10 8 7 9 22 21 RESERVED R-X 6 5 20 4 19 18 17 VHV_PV R-8h 16 3 2 0 1 VINH R-1h Table 9-59.
PAGE 752
Factory Configuration (FCFG) www.ti.com 9.2.1.37 FLASH_V Register (Offset = 198h) [reset = 0h] FLASH_V is shown in Figure 9-58 and described in Table 9-60. Flash Voltages Figure 9-58. FLASH_V Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 VSL_P VWL_P V_READ R-0h R-0h R-0h 9 8 7 6 5 4 3 2 RESERVED R-0h 1 0 Table 9-60.
PAGE 753
Factory Configuration (FCFG) www.ti.com 9.2.1.38 USER_ID Register (Offset = 294h) [reset = 0h] USER_ID is shown in Figure 9-59 and described in Table 9-61. User Identification The value of this register will be written to AON_WUC:JTAGUSERCODE by boot FW while in safezone. Figure 9-59.
PAGE 754
Factory Configuration (FCFG) www.ti.com 9.2.1.39 FLASH_OTP_DATA3 Register (Offset = 2B0h) [reset = X] FLASH_OTP_DATA3 is shown in Figure 9-60 and described in Table 9-62. Flash OTP Data 3 Figure 9-60. FLASH_OTP_DATA3 Register 31 30 29 28 27 EC_STEP_SIZE R-X 26 25 23 EC_STEP_SIZ E R-X 22 DO_PRECOND 21 20 19 MAX_EC_LEVEL 18 17 15 14 R-X 12 16 TRIM_1P7 R-4h 13 24 R-1h 11 10 9 8 4 3 WAIT_SYSCODE R-3h 2 1 0 FLASH_SIZE R-0h 7 6 5 Table 9-62.
PAGE 755
Factory Configuration (FCFG) www.ti.com 9.2.1.40 ANA2_TRIM Register (Offset = 2B4h) [reset = X] ANA2_TRIM is shown in Figure 9-61 and described in Table 9-63. Misc Analog Trim Figure 9-61.
PAGE 756
Factory Configuration (FCFG) www.ti.com Table 9-63. ANA2_TRIM Register Field Descriptions (continued) 756 Bit Field Type Reset Description 2-0 DCDC_HIGH_EN_SEL R 7h Value will be written to ADI_3_REFSYS:DCDCCTL4.HIGH_EN_SEL by boot FW while in safezone.
PAGE 757
Factory Configuration (FCFG) www.ti.com 9.2.1.41 LDO_TRIM Register (Offset = 2B8h) [reset = X] LDO_TRIM is shown in Figure 9-62 and described in Table 9-64. LDO Trim Figure 9-62. LDO_TRIM Register 31 30 RESERVED R-7h 29 28 27 26 VDDR_TRIM_SLEEP R-0h 23 22 21 RESERVED R-1Fh 20 19 15 14 RESERVED R-7h 13 7 6 5 RESERVED R-1Fh 12 11 ITRIM_DIGLDO_LOAD R-X 4 3 25 24 18 17 GLDO_CURSRC R-X 16 10 9 ITRIM_UDIGLDO R-X 8 2 1 VTRIM_DELTA R-3h 0 Table 9-64.
PAGE 758
Factory Configuration (FCFG) www.ti.com 9.2.1.42 MAC_BLE_0 Register (Offset = 2E8h) [reset = 0h] MAC_BLE_0 is shown in Figure 9-63 and described in Table 9-65. MAC BLE Address 0 Figure 9-63. MAC_BLE_0 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ADDR_0_31 R-0h 9 8 7 6 5 4 3 2 1 0 Table 9-65.
PAGE 759
Factory Configuration (FCFG) www.ti.com 9.2.1.43 MAC_BLE_1 Register (Offset = 2ECh) [reset = 0h] MAC_BLE_1 is shown in Figure 9-64 and described in Table 9-66. MAC BLE Address 1 Figure 9-64. MAC_BLE_1 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ADDR_32_63 R-0h 9 8 7 6 5 4 3 2 1 0 Table 9-66.
PAGE 760
Factory Configuration (FCFG) www.ti.com 9.2.1.44 MAC_15_4_0 Register (Offset = 2F0h) [reset = 0h] MAC_15_4_0 is shown in Figure 9-65 and described in Table 9-67. MAC IEEE 802.15.4 Address 0 Figure 9-65. MAC_15_4_0 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ADDR_0_31 R-0h 9 8 7 6 5 4 3 2 1 0 Table 9-67. MAC_15_4_0 Register Field Descriptions Bit 31-0 760 Field Type Reset Description ADDR_0_31 R 0h The first 32-bits of the 64-bit MAC 15.
PAGE 761
Factory Configuration (FCFG) www.ti.com 9.2.1.45 MAC_15_4_1 Register (Offset = 2F4h) [reset = 0h] MAC_15_4_1 is shown in Figure 9-66 and described in Table 9-68. MAC IEEE 802.15.4 Address 1 Figure 9-66. MAC_15_4_1 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ADDR_32_63 R-0h 9 8 7 6 5 4 3 2 1 0 Table 9-68. MAC_15_4_1 Register Field Descriptions Bit 31-0 Field Type Reset Description ADDR_32_63 R 0h The last 32-bits of the 64-bit MAC 15.
PAGE 762
Factory Configuration (FCFG) www.ti.com 9.2.1.46 FLASH_OTP_DATA4 Register (Offset = 308h) [reset = X] FLASH_OTP_DATA4 is shown in Figure 9-67 and described in Table 9-69. Flash OTP Data 4 Figure 9-67.
PAGE 763
Factory Configuration (FCFG) www.ti.com Table 9-69. FLASH_OTP_DATA4 Register Field Descriptions (continued) Bit Field Type Reset Description VIN_AT_X_EXT_WRT R X If AON_SYSCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to FLASH:FSEQPMP.VIN_AT_X by flash device driver FW when a flash write operation is initiated. 15 STANDBY_MODE_SEL_I NT_RD R 1h If AON_SYSCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to FLASH:CFG.
PAGE 764
Factory Configuration (FCFG) www.ti.com 9.2.1.47 MISC_TRIM Register (Offset = 30Ch) [reset = FFFFFF33h] MISC_TRIM is shown in Figure 9-68 and described in Table 9-70. Miscellaneous Trim Parameters Figure 9-68. MISC_TRIM Register 31 30 29 28 27 26 25 15 14 13 12 11 RESERVED R-FFFFFFh 10 9 24 23 RESERVED R-FFFFFFh 8 7 22 21 6 5 20 19 4 3 TEMPVSLOPE R-33h 18 17 16 2 1 0 Table 9-70.
PAGE 765
Factory Configuration (FCFG) www.ti.com 9.2.1.48 RCOSC_HF_TEMPCOMP Register (Offset = 310h) [reset = X] RCOSC_HF_TEMPCOMP is shown in Figure 9-69 and described in Table 9-71. RCOSC HF Temperature Compensation Figure 9-69. RCOSC_HF_TEMPCOMP Register 31 30 29 15 14 13 28 27 FINE_RESISTOR R-X 26 25 24 23 22 21 12 11 10 CTRIMFRACT_QUAD R-X 9 8 7 6 5 20 19 CTRIM R-X 18 17 16 4 3 2 CTRIMFRACT_SLOPE R-3h 1 0 Table 9-71.
PAGE 766
Factory Configuration (FCFG) www.ti.com 9.2.1.49 TRIM_CAL_REVISION Register (Offset = 314h) [reset = 0h] TRIM_CAL_REVISION is shown in Figure 9-70 and described in Table 9-72. Production Test Trim and Calibration Revision Figure 9-70. TRIM_CAL_REVISION Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 FT1 R-0h 9 8 7 MP1 R-0h 6 5 4 3 2 1 0 Table 9-72.
PAGE 767
Factory Configuration (FCFG) www.ti.com 9.2.1.50 ICEPICK_DEVICE_ID Register (Offset = 318h) [reset = 8B99A02Fh] ICEPICK_DEVICE_ID is shown in Figure 9-71 and described in Table 9-73. IcePick Device Identification This register shall hold a value that equals the value of the IcePick DEVICE_ID register. Figure 9-71.
PAGE 768
Factory Configuration (FCFG) www.ti.com 9.2.1.51 FCFG1_REVISION Register (Offset = 31Ch) [reset = 23h] FCFG1_REVISION is shown in Figure 9-72 and described in Table 9-74. Factory Configuration (FCFG1) Revision Figure 9-72. FCFG1_REVISION Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 REV R-23h 9 8 7 6 5 4 3 2 1 0 Table 9-74.
PAGE 769
Factory Configuration (FCFG) www.ti.com 9.2.1.52 MISC_OTP_DATA Register (Offset = 320h) [reset = X] MISC_OTP_DATA is shown in Figure 9-73 and described in Table 9-75. Misc OTP Data Figure 9-73. MISC_OTP_DATA Register 31 30 29 RCOSC_HF_ITUNE R-X 28 27 26 25 RCOSC_HF_CRIM R-X 24 23 22 21 RCOSC_HF_CRIM R-X 20 19 18 16 15 PER_M R-1h 14 13 PER_E R-4h 12 7 6 5 17 PER_M R-1h 11 4 3 TEST_PROGRAM_REV R-0h 10 9 PO_TAIL_RES_TRIM R-6h 2 1 8 0 Table 9-75.
PAGE 770
Factory Configuration (FCFG) www.ti.com 9.2.1.53 IOCONF Register (Offset = 344h) [reset = 7FFFFF8000h] IOCONF is shown in Figure 9-74 and described in Table 9-76. IO Configuration Figure 9-74. IOCONF Register 31 30 29 28 15 14 13 12 27 26 25 11 10 RESERVED R-FFFFFF00h 9 24 23 RESERVED R-FFFFFF00h 8 7 22 21 20 19 18 17 16 6 5 4 3 GPIO_CNT R-0h 2 1 0 Table 9-76.
PAGE 771
Factory Configuration (FCFG) www.ti.com 9.2.1.54 CONFIG_IF_ADC Register (Offset = 34Ch) [reset = X] CONFIG_IF_ADC is shown in Figure 9-75 and described in Table 9-77. Configuration of IF_ADC Figure 9-75. CONFIG_IF_ADC Register 31 30 29 28 27 26 FF2ADJ R-3h 23 22 21 20 19 18 INT3ADJ R-6h 15 14 13 12 11 10 3 2 IFANALDO_TRIM_OUTPUT R-0h INT2ADJ R-Dh 6 IFDIGLDO_TRIM_OUTPUT R-0h 24 17 16 FF1ADJ R-X AAFCAP R-3h 7 25 FF3ADJ R-4h 5 4 9 8 IFDIGLDO_TRIM_OUTPUT R-0h 1 0 Table 9-77.
PAGE 772
Factory Configuration (FCFG) www.ti.com 9.2.1.55 CONFIG_OSC_TOP Register (Offset = 350h) [reset = X] CONFIG_OSC_TOP is shown in Figure 9-76 and described in Table 9-78. Configuration of OSC Figure 9-76.
PAGE 773
Factory Configuration (FCFG) www.ti.com 9.2.1.56 CONFIG_RF_FRONTEND Register (Offset = 354h) [reset = X] CONFIG_RF_FRONTEND is shown in Figure 9-77 and described in Table 9-79. Configuration of RF Frontend in Divide-by-2 Mode Figure 9-77.
PAGE 774
Factory Configuration (FCFG) www.ti.com 9.2.1.57 CONFIG_SYNTH Register (Offset = 358h) [reset = FFFFF000h] CONFIG_SYNTH is shown in Figure 9-78 and described in Table 9-80. Configuration of Synthesizer in Divide-by-2 Mode Figure 9-78. CONFIG_SYNTH Register 31 30 29 RESERVED R-Fh 28 27 26 25 24 23 22 21 20 RFC_MDM_DEMIQMC0 R-FFFFh 15 14 13 12 RFC_MDM_DEMIQMC0 R-FFFFh 11 10 9 8 7 LDOVCO_TRIM_OUTPUT R-0h 6 5 4 19 18 17 16 3 2 1 SLDO_TRIM_OUTPUT R-0h 0 Table 9-80.
PAGE 775
Factory Configuration (FCFG) www.ti.com 9.2.1.58 SOC_ADC_ABS_GAIN Register (Offset = 35Ch) [reset = 0h] SOC_ADC_ABS_GAIN is shown in Figure 9-79 and described in Table 9-81. AUX_ADC Gain in Absolute Reference Mode Figure 9-79. SOC_ADC_ABS_GAIN Register 31 30 29 28 27 26 25 24 23 22 SOC_ADC_ABS_GAIN_TEMP2 R-0h 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 SOC_ADC_ABS_GAIN_TEMP1 R-0h 5 4 3 2 1 0 Table 9-81.
PAGE 776
Factory Configuration (FCFG) www.ti.com 9.2.1.59 SOC_ADC_REL_GAIN Register (Offset = 360h) [reset = 0h] SOC_ADC_REL_GAIN is shown in Figure 9-80 and described in Table 9-82. AUX_ADC Gain in Relative Reference Mode Figure 9-80. SOC_ADC_REL_GAIN Register 31 30 29 28 27 26 25 24 23 22 SOC_ADC_REL_GAIN_TEMP2 R-0h 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 SOC_ADC_REL_GAIN_TEMP1 R-0h 5 4 3 2 1 0 Table 9-82.
PAGE 777
Factory Configuration (FCFG) www.ti.com 9.2.1.60 SOC_ADC_EXT_GAIN Register (Offset = 364h) [reset = 0h] SOC_ADC_EXT_GAIN is shown in Figure 9-81 and described in Table 9-83. AUX_ADC Gain in External Reference Mode Figure 9-81. SOC_ADC_EXT_GAIN Register 31 30 29 28 27 26 25 24 23 22 SOC_ADC_EXT_GAIN_TEMP2 R-0h 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 SOC_ADC_EXT_GAIN_TEMP1 R-0h 5 4 3 2 1 0 Table 9-83.
PAGE 778
Factory Configuration (FCFG) www.ti.com 9.2.1.61 SOC_ADC_OFFSET_INT Register (Offset = 368h) [reset = 0h] SOC_ADC_OFFSET_INT is shown in Figure 9-82 and described in Table 9-84. AUX_ADC Temperature Offsets in Absolute Reference Mode Figure 9-82.
PAGE 779
Factory Configuration (FCFG) www.ti.com 9.2.1.62 SOC_ADC_REF_TRIM_AND_OFFSET_EXT Register (Offset = 36Ch) [reset = 300080h] SOC_ADC_REF_TRIM_AND_OFFSET_EXT is shown in Figure 9-83 and described in Table 9-85. AUX_ADC Reference Trim and Offset for External Reference Mode Figure 9-83.
PAGE 780
Factory Configuration (FCFG) www.ti.com 9.2.1.63 AMPCOMP_TH1 Register (Offset = 370h) [reset = FF7B828Eh] AMPCOMP_TH1 is shown in Figure 9-84 and described in Table 9-86. Ampltude Compensation Threashold 1 Figure 9-84. AMPCOMP_TH1 Register 31 30 29 28 27 26 25 21 20 HPMRAMP3_LTH R-1Eh 19 18 17 13 12 HPMRAMP3_HTH R-20h 11 5 3 2 HPMRAMP1_TH R-Eh 24 RESERVED R-FFh 23 22 15 14 7 6 IBIASCAP_LPTOHP_OL_CNT R-Ah 4 16 RESERVED R-3h 10 9 8 IBIASCAP_LPTOHP_OL_CNT R-Ah 1 0 Table 9-86.
PAGE 781
Factory Configuration (FCFG) www.ti.com 9.2.1.64 AMPCOMP_TH2 Register (Offset = 374h) [reset = X] AMPCOMP_TH2 is shown in Figure 9-85 and described in Table 9-87. Ampltude Compensation Threashold 2 Figure 9-85. AMPCOMP_TH2 Register 31 30 23 29 28 LPMUPDATE_LTH R-1Ah 27 21 20 LPMUPDATE_HTM R-22h 19 13 12 ADC_COMP_AMPTH_LPM R-X 11 5 4 ADC_COMP_AMPTH_HPM R-X 3 22 15 14 7 6 26 25 24 RESERVED R-3h 18 17 16 RESERVED R-3h 10 9 8 RESERVED R-3h 2 1 0 RESERVED R-3h Table 9-87.
PAGE 782
Factory Configuration (FCFG) www.ti.com 9.2.1.65 AMPCOMP_CTRL1 Register (Offset = 378h) [reset = FF183F47h] AMPCOMP_CTRL1 is shown in Figure 9-86 and described in Table 9-88. Amplitude Compensation Control Figure 9-86.
PAGE 783
Factory Configuration (FCFG) www.ti.com 9.2.1.66 ANABYPASS_VALUE2 Register (Offset = 37Ch) [reset = FFFFC3FFh] ANABYPASS_VALUE2 is shown in Figure 9-87 and described in Table 9-89. Analog Bypass Value for OSC Figure 9-87. ANABYPASS_VALUE2 Register 31 30 29 28 27 26 25 15 14 RESERVED R-3FFFFh 13 12 11 10 9 24 23 RESERVED R-3FFFFh 22 21 20 19 18 17 16 8 7 6 5 XOSC_HF_IBIASTHERM R-3FFh 4 3 2 1 0 Table 9-89.
PAGE 784
Factory Configuration (FCFG) www.ti.com 9.2.1.67 CONFIG_MISC_ADC Register (Offset = 380h) [reset = FFFC014Dh] CONFIG_MISC_ADC is shown in Figure 9-88 and described in Table 9-90. Configuration of IFADC in Divide-by-2 Mode Figure 9-88.
PAGE 785
Factory Configuration (FCFG) www.ti.com 9.2.1.68 VOLT_TRIM Register (Offset = 388h) [reset = FFFFFFE0h] VOLT_TRIM is shown in Figure 9-89 and described in Table 9-91. Voltage Trim Figure 9-89. VOLT_TRIM Register 31 30 RESERVED R-7h 29 28 27 26 VDDR_TRIM_HH R-1Fh 25 24 23 22 RESERVED R-7h 21 20 19 18 VDDR_TRIM_H R-1Fh 17 16 15 14 RESERVED R-7h 13 12 11 10 VDDR_TRIM_SLEEP_H R-1Fh 9 8 7 6 RESERVED R-7h 5 4 3 2 TRIMBOD_H R-0h 1 0 Table 9-91.
PAGE 786
Factory Configuration (FCFG) www.ti.com 9.2.1.69 OSC_CONF Register (Offset = 38Ch) [reset = X] OSC_CONF is shown in Figure 9-90 and described in Table 9-92. OSC Configuration Figure 9-90.
PAGE 787
Factory Configuration (FCFG) www.ti.com 9.2.1.70 CAP_TRIM Register (Offset = 394h) [reset = FFFFFFFFh] CAP_TRIM is shown in Figure 9-91 and described in Table 9-93. Capasitor Trim Figure 9-91. CAP_TRIM Register 31 30 29 28 27 26 25 24 23 22 FLUX_CAP_0P28_TRIM R-FFFFh 21 20 19 18 17 16 15 14 13 12 11 10 9 5 4 3 2 1 0 8 7 6 FLUX_CAP_0P4_TRIM R-FFFFh Table 9-93.
PAGE 788
Factory Configuration (FCFG) www.ti.com 9.2.1.71 MISC_OTP_DATA_1 Register (Offset = 398h) [reset = X] MISC_OTP_DATA_1 is shown in Figure 9-92 and described in Table 9-94. Misc OSC Control Figure 9-92.
PAGE 789
Factory Configuration (FCFG) www.ti.com 9.2.1.72 PWD_CURR_20C Register (Offset = 39Ch) [reset = 80BA608h] PWD_CURR_20C is shown in Figure 9-93 and described in Table 9-95. Power Down Current Control 20C Figure 9-93. PWD_CURR_20C Register 31 30 29 28 27 26 DELTA_CACHE_REF R-8h 25 24 23 22 21 15 14 13 12 11 10 DELTA_XOSC_LPM R-A6h 9 8 7 6 5 20 19 18 DELTA_RFMEM_RET R-Bh 4 3 BASELINE R-8h 2 17 16 1 0 Table 9-95.
PAGE 790
Factory Configuration (FCFG) www.ti.com 9.2.1.73 PWD_CURR_35C Register (Offset = 3A0h) [reset = C10A50Ah] PWD_CURR_35C is shown in Figure 9-94 and described in Table 9-96. Power Down Current Control 35C Figure 9-94. PWD_CURR_35C Register 31 30 29 28 27 26 DELTA_CACHE_REF R-Ch 25 24 23 22 21 15 14 13 12 11 10 DELTA_XOSC_LPM R-A5h 9 8 7 6 5 20 19 18 DELTA_RFMEM_RET R-10h 4 3 BASELINE R-Ah 2 17 16 1 0 Table 9-96.
PAGE 791
Factory Configuration (FCFG) www.ti.com 9.2.1.74 PWD_CURR_50C Register (Offset = 3A4h) [reset = 1218A20Dh] PWD_CURR_50C is shown in Figure 9-95 and described in Table 9-97. Power Down Current Control 50C Figure 9-95. PWD_CURR_50C Register 31 30 29 28 27 26 DELTA_CACHE_REF R-12h 25 24 23 22 21 15 14 13 12 11 10 DELTA_XOSC_LPM R-A2h 9 8 7 6 5 20 19 18 DELTA_RFMEM_RET R-18h 4 3 BASELINE R-Dh 2 17 16 1 0 Table 9-97.
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Factory Configuration (FCFG) www.ti.com 9.2.1.75 PWD_CURR_65C Register (Offset = 3A8h) [reset = 1C259C14h] PWD_CURR_65C is shown in Figure 9-96 and described in Table 9-98. Power Down Current Control 65C Figure 9-96. PWD_CURR_65C Register 31 30 29 28 27 26 DELTA_CACHE_REF R-1Ch 25 24 23 22 21 15 14 13 12 11 10 DELTA_XOSC_LPM R-9Ch 9 8 7 6 5 20 19 18 DELTA_RFMEM_RET R-25h 4 3 BASELINE R-14h 2 17 16 1 0 Table 9-98.
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Factory Configuration (FCFG) www.ti.com 9.2.1.76 PWD_CURR_80C Register (Offset = 3ACh) [reset = 2E3B9021h] PWD_CURR_80C is shown in Figure 9-97 and described in Table 9-99. Power Down Current Control 80C Figure 9-97. PWD_CURR_80C Register 31 30 29 28 27 26 DELTA_CACHE_REF R-2Eh 25 24 23 22 21 15 14 13 12 11 10 DELTA_XOSC_LPM R-90h 9 8 7 6 5 20 19 18 DELTA_RFMEM_RET R-3Bh 4 3 BASELINE R-21h 2 17 16 1 0 Table 9-99.
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Factory Configuration (FCFG) www.ti.com 9.2.1.77 PWD_CURR_95C Register (Offset = 3B0h) [reset = 4C627A3Bh] PWD_CURR_95C is shown in Figure 9-98 and described in Table 9-100. Power Down Current Control 95C Figure 9-98. PWD_CURR_95C Register 31 30 29 28 27 26 DELTA_CACHE_REF R-4Ch 25 24 23 22 21 15 14 13 12 11 10 DELTA_XOSC_LPM R-7Ah 9 8 7 6 5 20 19 18 DELTA_RFMEM_RET R-62h 4 3 BASELINE R-3Bh 2 17 16 1 0 Table 9-100.
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Factory Configuration (FCFG) www.ti.com 9.2.1.78 PWD_CURR_110C Register (Offset = 3B4h) [reset = 789E706Bh] PWD_CURR_110C is shown in Figure 9-99 and described in Table 9-101. Power Down Current Control 110C Figure 9-99. PWD_CURR_110C Register 31 30 29 28 27 26 DELTA_CACHE_REF R-78h 25 24 23 22 21 15 14 13 12 11 10 DELTA_XOSC_LPM R-70h 9 8 7 6 5 20 19 18 DELTA_RFMEM_RET R-9Eh 4 3 BASELINE R-6Bh 2 17 16 1 0 Table 9-101.
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Factory Configuration (FCFG) www.ti.com 9.2.1.79 PWD_CURR_125C Register (Offset = 3B8h) [reset = ADE1809Ah] PWD_CURR_125C is shown in Figure 9-100 and described in Table 9-102. Power Down Current Control 125C Figure 9-100. PWD_CURR_125C Register 31 30 29 28 27 26 DELTA_CACHE_REF R-ADh 25 24 23 22 21 15 14 13 12 11 10 DELTA_XOSC_LPM R-80h 9 8 7 6 5 20 19 18 DELTA_RFMEM_RET R-E1h 4 3 BASELINE R-9Ah 2 17 16 1 0 Table 9-102.
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Chapter 10 SWCU117A – February 2015 – Revised March 2015 Cryptography The security core of the CC26xx features an Advanced Encryption Standard (AES) module with 128-bit key support, local key storage, and DMA capability. This chapter provides the description and information for configuring the AES engine. Topic 10.1 10.2 ........................................................................................................................... Page AES Cryptoprocessor Overview ..........................
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AES Cryptoprocessor Overview www.ti.com 10.1 AES Cryptoprocessor Overview The AES security module provides hardware-accelerated data encryption and decryption operations based on a binary key. The module supports a 128-bit key in hardware for both encryption and decryption and uses symmetric algorithm, meaning that the encryption and decryption keys are identical. Encryption converts plain text data to an unintelligible form called cipher text.
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AES Cryptoprocessor Overview www.ti.com 10.1.1.1 Debug Capabilities The AES module provides the following status registers to monitor operations of the engine: • DMA status and port-error status registers • Interrupt status registers in the master control module • Key-store module status register 10.1.1.2 Exception Handling The AES module can detect AHB master bus errors and abort the DMA operation. The AES key-store module can detect key-load errors and does not store the bad key in that case.
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AES Cryptoprocessor Overview www.ti.com NOTE: The CC26xx does not support burst or non-sequential transfers through internal interconnect. The [DMABUSCFG] register must not be changed for proper operation. 10.1.3.3 Interrupts The AES module has two interrupt outputs; both are driven from the master control module and are controlled by the respective registers (see Section 10.1.4.4.3, Software Reset) To enable interrupts for the AES engine, IRQTYPE.
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AES Cryptoprocessor Overview www.ti.com Table 10-1. Detailed Memory Map (continued) Physical Address Register Name Type Reset Value Remark 0x4002 407C DMAPORTERR R 0x0000 0000 Port-error raw-status Section 10.2.1.10 register Link 0x4002 40F8 DMAHWOPT R 0x0000 0202 DMAC-options register 0x4002 40FC DMAHWVER R 0x0101 2ED1 DMAC-version register Section 10.2.1.11 Key-Storage Registers 0x4002 4400 KEYWRITEAREA R/W 0x0000 0000 Writer-area register Section 10.2.1.
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AES Cryptoprocessor Overview www.ti.com Table 10-1. Detailed Memory Map (continued) Physical Address Register Name Type Reset Value Remark 0x4002 47F8 HWOPT R 0x0201 0093 Type and Options Register Link 0x4002 47FC HWVER R 0x9110 8778 Version Register Section 10.2.1.40 Unspecified addresses are reserved and should not be written and ignored on a read. 10.1.4.3 DMA Controller Figure 10-1 shows the DMA Controller and its integration in the AES module. Figure 10-1.
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AES Cryptoprocessor Overview www.ti.com If the address and lengths are 32-bit aligned, the master does only NONSEQ and SINGLE-type transfers with a size of 4 bytes. The DMAC splits channel DMA operation into small DMA transfers. The size of small DMA transfers is determined by the target internal module, and equals to block size of the cryptographic operation.
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AES Cryptoprocessor Overview www.ti.com The AES engine has a 32-bit write interface for input data to be encrypted or decrypted, and a 32-bit read interface for result data and tag. The write interface of the AES module collects 32-bit data into a 128-bit input block (AES block size) and when a full block is received, the AES calculation for the received block is started. When receiving the last word of the last block, the DMAC and master controller generate a "data done" signal to the crypto engine.
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AES Cryptoprocessor Overview www.ti.com 10.1.4.4.1 Algorithm Select This algorithm-selection register configures the internal destination of the DMA controller. 10.1.4.4.1.1 Algorithm Select Table 10-3 summarizes the allowed bit combinations of the [ALGSEL] register. Table 10-3.
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AES Cryptoprocessor Overview www.ti.com The architecture of the AES decryption core is generally the same as the architecture of the encryption core. One difference is that the generation of round keys for decryption requires an initial conversion of the input key (always supplied by the host in the form of an encryption key) to the corresponding decryption key. This conversion is done by performing a dummy encryption operation and storing the final round key as a decryption key.
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AES Cryptoprocessor Overview www.ti.com 10.1.4.5.2 AES Initialization Vector (IV) Registers The AES Initialization Vector registers are used to provide and read the IV from the AES engine. Table 10-6.
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AES Cryptoprocessor Overview www.ti.com When writing a new mode without writing the length registers, the length register values from the previous context is reused. 10.1.4.5.4 Data Input/Output Registers The [AESDATAINx] and [AESDATAOUTx] data registers are typically accessed through DMA and not with host writes and reads. However, for debugging purposes, the Data Input and Output Registers can be accessed through host write and read operations.
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AES Cryptoprocessor Overview www.ti.com 10.1.4.5.5 TAG Registers The TAG registers buffer the TAG from the AES module and can be accessed through DMA or directly with host reads. The TAG registers are shared with the intermediate authentication result registers, but cannot be read until the processing is finished. While processing, a read from these registers returns zeroes. If an operation does not return a TAG, reading from these registers returns an initialization vector (IV).
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AES Cryptoprocessor Overview www.ti.com 10.1.4.6.4 Key Read Area Register The Key Read Area register selects the key store RAM area from where the key needs to be read that is used for an AES operation. The operation starts directly after writing this register. When the operation is finished, the status of the key store read operation is available in the interrupt status register IRQSTAT. Key store read error asserts when a ram area is selected that does not contain a valid written key 10.1.
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AES Cryptoprocessor Overview www.ti.com 10.1.5.2 Performance Table 10-9 shows the performance of the AES module running at 200 MHz for DMA-based cryptographic operations. Table 10-9.
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AES Cryptoprocessor Overview www.ti.com Master clock. NOTE: The [IRQSTAT] register should be checked for possible errors if bus errors can occur in the system, which is typically valid in a debugging phase, or in systems where bus errors can occur during a DMA operation. 10.1.6.2.2 Interrupting DMA Transfers If the host wants to stop a DMA transfer to abort the operation, the host can disable a channel using the [DMACHxCTL] registers.
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AES Cryptoprocessor Overview www.ti.com 10.1.6.3.1 Data Format and Byte Order The following examples show how the data must be submitted to the AES Engine. Because the AHB slave interface is mostly transparent for data (no data modifications), the alignment for the register interface is identical, as described in the following examples. NOTE: The byte in bold type is a first byte of the key or message.
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AES Cryptoprocessor Overview www.ti.com 10.1.6.3.2 Key Store Before any encryption or decryption operation starts, the key store module must have at least one key loaded and available for crypto operations. Keys can only be loaded from external memory using a DMA operation. DMAC channel 0 (inbound) is used for this purpose. 10.1.6.3.2.
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AES Cryptoprocessor Overview www.ti.com 10.1.6.3.3.2 AES-CBC For AES-CBC operations, the following configuration parameters are required: • Key from the key store module • IV from the slave interface • Control register settings (mode, direction, key size) • Length of the data The length field can have any value. If a data stream is finished and the next data stream uses the same key and control, it is allowed to write only the IV and length field with a new value.
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AES Cryptoprocessor Overview www.ti.com 10.1.6.3.3.4 Programming Sequence With DMA Data The following software example in pseudo-code describes the actions that are typically executed by the host software to encrypt (using a basic AES mode) a message, stored in external memory and place an encrypted result into a preallocated area in the external memory.
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AES Cryptoprocessor Overview www.ti.com 10.1.6.3.4 CBC-MAC For CBC-MAC operations, the following configuration parameters are required: • Key from the key store module • IV must be written with zeroes • Control register settings (mode, direction, key size) • Length of the authenticated data (may be non-block size aligned) The input data may end misaligned for CBC-MAC operations. If this is the case, the crypto core internally pads the last input data block. The length field can have any value.
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AES Cryptoprocessor Overview www.ti.com 10.1.6.3.
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AES Cryptoprocessor Overview www.ti.com write DMACH0CTL 0x0000_00001 // enable DMA channel 0 write DMACH0EXTADDR
// base address of the AAD input data in ext.
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AES Cryptoprocessor Overview www.ti.com In this situation, the DMAC disables all channels so that no new transfers are requested, while the error is captured in the status registers. The [DMAPORTERR] register contains information about the active channel when the AHB port error occurred. DMAC indicates the channel completion to the master control module.
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AES Cryptoprocessor Overview www.ti.
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Cryptography Registers www.ti.com 10.1.7.1.3 Formulae and Nomenclature This document contains formulas and nomenclature for different data types.
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Cryptography Registers www.ti.com 10.2.1 CRYPTO Registers Table 10-10 lists the memory-mapped registers for the CRYPTO. All register offset addresses not listed in Table 10-10 should be considered as reserved locations and the register contents should not be modified. Table 10-10. CRYPTO Registers Offset Acronym Register Name 0h DMACH0CTL DMA Channel 0 Control Section 10.2.1.1 Section 4h DMACH0EXTADDR DMA Channel 0 External Address Section 10.2.1.
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Cryptography Registers www.ti.com 10.2.1.1 DMACH0CTL Register (Offset = 0h) [reset = X] DMACH0CTL is shown in Figure 10-3 and described in Table 10-11. DMA Channel 0 Control Figure 10-3. DMACH0CTL Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 PRIO R/W-X 0 EN R/W-X RESERVED R/W-X 23 22 21 20 RESERVED R/W-X 15 14 13 12 RESERVED R/W-X 7 6 5 4 RESERVED R/W-X Table 10-11.
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Cryptography Registers www.ti.com 10.2.1.2 DMACH0EXTADDR Register (Offset = 4h) [reset = X] DMACH0EXTADDR is shown in Figure 10-4 and described in Table 10-12. DMA Channel 0 External Address Figure 10-4. DMACH0EXTADDR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ADDR R/W-X 9 8 7 6 5 4 3 2 1 0 Table 10-12. DMACH0EXTADDR Register Field Descriptions Bit Field Type Reset Description 31-0 ADDR R/W X Channel external address value.
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Cryptography Registers www.ti.com 10.2.1.3 DMACH0LEN Register (Offset = Ch) [reset = X] DMACH0LEN is shown in Figure 10-5 and described in Table 10-13. DMA Channel 0 Length Figure 10-5. DMACH0LEN Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R/W-X 9 8 7 LEN R/W-X 6 5 4 3 2 1 0 Table 10-13. DMACH0LEN Register Field Descriptions Bit 826 Field Type Reset Description 31-16 RESERVED R/W X Software should not rely on the value of a reserved.
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Cryptography Registers www.ti.com 10.2.1.4 DMASTAT Register (Offset = 18h) [reset = X] DMASTAT is shown in Figure 10-6 and described in Table 10-14. DMA Controller Status Figure 10-6. DMASTAT Register 31 30 29 28 27 26 25 24 19 18 17 PORT_ERR R-X 16 RESERVED R-X 11 10 9 8 3 2 1 CH1_ACTIVE R-X 0 CH0_ACTIVE R-X RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 4 RESERVED R-X Table 10-14.
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Cryptography Registers www.ti.com 10.2.1.5 DMASWRESET Register (Offset = 1Ch) [reset = X] DMASWRESET is shown in Figure 10-7 and described in Table 10-15. DMA Controller Software Reset Figure 10-7. DMASWRESET Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RESET zeroToClear-X RESERVED W-X 23 22 21 20 RESERVED W-X 15 14 13 12 RESERVED W-X 7 6 5 4 RESERVED W-X Table 10-15.
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Cryptography Registers www.ti.com 10.2.1.6 DMACH1CTL Register (Offset = 20h) [reset = X] DMACH1CTL is shown in Figure 10-8 and described in Table 10-16. DMA Channel 1 Control Figure 10-8. DMACH1CTL Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 PRIO R/W-X 0 EN R/W-X RESERVED R/W-X 23 22 21 20 RESERVED R/W-X 15 14 13 12 RESERVED R/W-X 7 6 5 4 RESERVED R/W-X Table 10-16.
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Cryptography Registers www.ti.com 10.2.1.7 DMACH1EXTADDR Register (Offset = 24h) [reset = X] DMACH1EXTADDR is shown in Figure 10-9 and described in Table 10-17. DMA Channel 1 External Address Figure 10-9. DMACH1EXTADDR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ADDR R/W-X 9 8 7 6 5 4 3 2 1 0 Table 10-17. DMACH1EXTADDR Register Field Descriptions 830 Bit Field Type Reset Description 31-0 ADDR R/W X Channel external address value.
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Cryptography Registers www.ti.com 10.2.1.8 DMACH1LEN Register (Offset = 2Ch) [reset = X] DMACH1LEN is shown in Figure 10-10 and described in Table 10-18. DMA Channel 1 Length Figure 10-10. DMACH1LEN Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R/W-X 9 8 7 LEN R/W-X 6 5 4 3 2 1 0 Table 10-18. DMACH1LEN Register Field Descriptions Field Type Reset Description 31-16 Bit RESERVED R/W X Software should not rely on the value of a reserved.
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Cryptography Registers www.ti.com 10.2.1.9 DMABUSCFG Register (Offset = 78h) [reset = X] DMABUSCFG is shown in Figure 10-11 and described in Table 10-19. DMA Controller Master Configuration Figure 10-11.
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Cryptography Registers www.ti.com 10.2.1.10 DMAPORTERR Register (Offset = 7Ch) [reset = X] DMAPORTERR is shown in Figure 10-12 and described in Table 10-20. DMA Controller Port Error Figure 10-12. DMAPORTERR Register 31 30 29 28 27 26 25 24 19 18 17 16 10 9 LAST_CH R-X 8 RESERVED R-X 2 1 0 RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 RESERVED R-X 13 6 5 7 12 AHB_ERR R-X 11 4 3 RESERVED R-X RESERVED R-X Table 10-20.
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Cryptography Registers www.ti.com 10.2.1.11 DMAHWVER Register (Offset = FCh) [reset = X] DMAHWVER is shown in Figure 10-13 and described in Table 10-21. DMA Controller Version Figure 10-13. DMAHWVER Register 31 30 29 RESERVED R-X 15 14 13 28 27 26 25 HW_MAJOR_VER R-1h 12 11 10 VER_NUM_COMPL R-2Eh 9 24 23 8 7 22 21 HW_MINOR_VER R-X 6 5 20 19 18 17 HW_PATCH_LVL R-1h 4 3 VER_NUM R-D1h 2 1 16 0 Table 10-21.
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Cryptography Registers www.ti.com 10.2.1.12 KEYWRITEAREA Register (Offset = 400h) [reset = X] KEYWRITEAREA is shown in Figure 10-14 and described in Table 10-22. Key Write Area Figure 10-14.
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Cryptography Registers www.ti.com Table 10-22. KEYWRITEAREA Register Field Descriptions (continued) Bit 836 Field Type Reset Description 2 RAM_AREA2 R/W X Represents an area of 128 bits. Select the key store RAM area(s) where the key(s) needs to be written. Writing to multiple RAM locations is only possible when the selected RAM areas are sequential.
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Cryptography Registers www.ti.com 10.2.1.13 KEYWRITTENAREA Register (Offset = 404h) [reset = X] KEYWRITTENAREA is shown in Figure 10-15 and described in Table 10-23. Key Written Area Status This register shows which areas of the key store RAM contain valid written keys. When a new key needs to be written to the key store, on a location that is already occupied by a valid key, this key area must be cleared first.
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Cryptography Registers www.ti.com Table 10-23. KEYWRITTENAREA Register Field Descriptions (continued) Bit 838 Field Type Reset Description 3 RAM_AREA_WRITTEN3 R/W1C X On read this bit returns the key area written status. This bit can be reset by writing a 1. Note: This register will be reset on a soft reset initiated by writing to DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key store memory.
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Cryptography Registers www.ti.com 10.2.1.14 KEYSIZE Register (Offset = 408h) [reset = X] KEYSIZE is shown in Figure 10-16 and described in Table 10-24. Key Size This register defines the size of the keys that are written with DMA. Figure 10-16. KEYSIZE Register 31 30 29 28 27 26 25 24 23 RESERVED R/W-X 15 14 13 12 11 10 9 8 RESERVED R/W-X 7 22 21 20 19 18 17 16 6 5 4 3 2 1 0 SIZE R/W-1h Table 10-24.
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Cryptography Registers www.ti.com 10.2.1.15 KEYREADAREA Register (Offset = 40Ch) [reset = X] KEYREADAREA is shown in Figure 10-17 and described in Table 10-25. Key Read Area Figure 10-17. KEYREADAREA Register 31 BUSY R-X 30 29 28 23 22 21 20 27 RESERVED R/W-X 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RESERVED R/W-X 15 14 13 12 RESERVED R/W-X 7 6 5 4 RESERVED R/W-X RAM_AREA R/W-8h Table 10-25.
PAGE 841
Cryptography Registers www.ti.com 10.2.1.16 AESKEY2_0 to AESKEY2_3 Register (Offset = 500h to 50Ch) [reset = X] AESKEY2_0 to AESKEY2_3 is shown in Figure 10-18 and described in Table 10-26. Clear AES_KEY2/GHASH Key Figure 10-18. AESKEY2_0 to AESKEY2_3 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 KEY2 W-X 9 8 7 6 5 4 3 2 1 0 Table 10-26. AESKEY2_0 to AESKEY2_3 Register Field Descriptions Bit Field Type Reset Description 31-0 KEY2 W X AESKEY2.
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Cryptography Registers www.ti.com 10.2.1.17 AESKEY3_0 to AESKEY3_3 Register (Offset = 510h to 51Ch) [reset = X] AESKEY3_0 to AESKEY3_3 is shown in Figure 10-19 and described in Table 10-27. Clear AES_KEY3 Figure 10-19. AESKEY3_0 to AESKEY3_3 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 KEY3 W-X 9 8 7 6 5 4 3 2 1 0 Table 10-27. AESKEY3_0 to AESKEY3_3 Register Field Descriptions 842 Bit Field Type Reset Description 31-0 KEY3 W X AESKEY3.
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Cryptography Registers www.ti.com 10.2.1.18 AESIV_0 to AESIV_3 Register (Offset = 540h to 54Ch) [reset = X] AESIV_0 to AESIV_3 is shown in Figure 10-20 and described in Table 10-28. AES Initialization Vector Figure 10-20. AESIV_0 to AESIV_3 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 IV R/W-X 9 8 7 6 5 4 3 2 1 0 Table 10-28.
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Cryptography Registers www.ti.com 10.2.1.19 AESCTL Register (Offset = 550h) [reset = X] AESCTL is shown in Figure 10-21 and described in Table 10-29. AES Input/Output Buffer Control Figure 10-21.
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Cryptography Registers www.ti.com Table 10-29. AESCTL Register Field Descriptions (continued) Bit Field Type Reset Description 15 CBC_MAC R/W X MAC mode enable. The DIR bit must be set to 1 for this mode. Selecting this mode requires writing the AESDATALEN1.LEN_MSW and AESDATALEN0.LEN_LSW registers after all other registers. 14-9 RESERVED R/W X Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
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Cryptography Registers www.ti.com 10.2.1.20 AESDATALEN0 Register (Offset = 554h) [reset = X] AESDATALEN0 is shown in Figure 10-22 and described in Table 10-30. Crypto Data Length LSW Figure 10-22. AESDATALEN0 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 LEN_LSW W-X 9 8 7 6 5 4 3 2 1 0 Table 10-30. AESDATALEN0 Register Field Descriptions Bit 31-0 846 Field Type Reset Description LEN_LSW W X Used to write the Length values to the Crypto peripheral.
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Cryptography Registers www.ti.com 10.2.1.21 AESDATALEN1 Register (Offset = 558h) [reset = X] AESDATALEN1 is shown in Figure 10-23 and described in Table 10-31. Crypto Data Length MSW Figure 10-23. AESDATALEN1 Register 31 30 29 RESERVED W-X 15 14 13 28 27 26 25 24 23 12 11 10 9 8 7 LEN_MSW W-X 22 21 LEN_MSW W-X 6 5 20 19 18 17 16 4 3 2 1 0 Table 10-31.
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Cryptography Registers www.ti.com 10.2.1.22 AESAUTHLEN Register (Offset = 55Ch) [reset = X] AESAUTHLEN is shown in Figure 10-24 and described in Table 10-32. AES Authentication Length Figure 10-24. AESAUTHLEN Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 LEN W-X 9 8 7 6 5 4 3 2 1 0 Table 10-32. AESAUTHLEN Register Field Descriptions 848 Bit Field Type Reset Description 31-0 LEN W X Authentication data length in bytes for combined mode, CCM only.
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Cryptography Registers www.ti.com 10.2.1.23 AESDATAOUT0 Register (Offset = 560h) [reset = X] AESDATAOUT0 is shown in Figure 10-25 and described in Table 10-33. Data Input/Output Figure 10-25. AESDATAOUT0 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DATA R-X 9 8 7 6 5 4 3 2 1 0 Table 10-33. AESDATAOUT0 Register Field Descriptions Bit Field Type Reset Description 31-0 DATA R X Data register 0 for output block data from the Crypto peripheral.
PAGE 850
Cryptography Registers www.ti.com 10.2.1.24 AESDATAIN0 Register (Offset = 560h) [reset = X] AESDATAIN0 is shown in Figure 10-26 and described in Table 10-34. AES Data Input/Output 0 Figure 10-26. AESDATAIN0 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DATA W-X 9 8 7 6 5 4 3 2 1 0 Table 10-34. AESDATAIN0 Register Field Descriptions 850 Bit Field Type Reset Description 31-0 DATA W X Data registers for input block data to the Crypto peripheral.
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Cryptography Registers www.ti.com 10.2.1.25 AESDATAOUT1 Register (Offset = 564h) [reset = X] AESDATAOUT1 is shown in Figure 10-27 and described in Table 10-35. AES Data Input/Output 3 Figure 10-27. AESDATAOUT1 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DATA R-X 9 8 7 6 5 4 3 2 1 0 Table 10-35. AESDATAOUT1 Register Field Descriptions Bit Field Type Reset Description 31-0 DATA R X Data registers for output block data from the Crypto peripheral.
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Cryptography Registers www.ti.com 10.2.1.26 AESDATAIN1 Register (Offset = 564h) [reset = X] AESDATAIN1 is shown in Figure 10-28 and described in Table 10-36. AES Data Input/Output 1 Figure 10-28. AESDATAIN1 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DATA W-X 9 8 7 6 5 4 3 2 1 0 Table 10-36. AESDATAIN1 Register Field Descriptions 852 Bit Field Type Reset Description 31-0 DATA W X Data registers for input block data to the Crypto peripheral.
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Cryptography Registers www.ti.com 10.2.1.27 AESDATAOUT2 Register (Offset = 568h) [reset = X] AESDATAOUT2 is shown in Figure 10-29 and described in Table 10-37. AES Data Input/Output 2 Figure 10-29. AESDATAOUT2 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DATA R-X 9 8 7 6 5 4 3 2 1 0 Table 10-37. AESDATAOUT2 Register Field Descriptions Bit Field Type Reset Description 31-0 DATA R X Data registers for output block data from the Crypto peripheral.
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Cryptography Registers www.ti.com 10.2.1.28 AESDATAIN2 Register (Offset = 568h) [reset = X] AESDATAIN2 is shown in Figure 10-30 and described in Table 10-38. AES Data Input/Output 2 Figure 10-30. AESDATAIN2 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DATA W-X 9 8 7 6 5 4 3 2 1 0 Table 10-38. AESDATAIN2 Register Field Descriptions 854 Bit Field Type Reset Description 31-0 DATA W X Data registers for input block data to the Crypto peripheral.
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Cryptography Registers www.ti.com 10.2.1.29 AESDATAOUT3 Register (Offset = 56Ch) [reset = X] AESDATAOUT3 is shown in Figure 10-31 and described in Table 10-39. AES Data Input/Output 3 Figure 10-31. AESDATAOUT3 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DATA R-X 9 8 7 6 5 4 3 2 1 0 Table 10-39. AESDATAOUT3 Register Field Descriptions Bit Field Type Reset Description 31-0 DATA R X Data registers for output block data from the Crypto peripheral.
PAGE 856
Cryptography Registers www.ti.com 10.2.1.30 AESDATAIN3 Register (Offset = 56Ch) [reset = X] AESDATAIN3 is shown in Figure 10-32 and described in Table 10-40. Data Input/Output Figure 10-32. AESDATAIN3 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DATA W-X 9 8 7 6 5 4 3 2 1 0 Table 10-40. AESDATAIN3 Register Field Descriptions 856 Bit Field Type Reset Description 31-0 DATA W X Data registers for input block data to the Crypto peripheral.
PAGE 857
Cryptography Registers www.ti.com 10.2.1.31 AESTAGOUT_0 to AESTAGOUT_3 Register (Offset = 570h to 57Ch) [reset = X] AESTAGOUT_0 to AESTAGOUT_3 is shown in Figure 10-33 and described in Table 10-41. AES Tag Output Figure 10-33. AESTAGOUT_0 to AESTAGOUT_3 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 TAG R-X 9 8 7 6 5 4 3 2 1 0 Table 10-41.
PAGE 858
Cryptography Registers www.ti.com 10.2.1.32 ALGSEL Register (Offset = 700h) [reset = X] ALGSEL is shown in Figure 10-34 and described in Table 10-42. Master Algorithm Select This register configures the internal destination of the DMA controller. Figure 10-34. ALGSEL Register 31 TAG R/W-X 30 29 28 23 22 21 20 27 RESERVED R/W-X 26 25 24 19 18 17 16 11 10 9 8 3 2 1 AES R/W-X 0 KEY_STORE R/W-X RESERVED R/W-X 15 14 13 12 RESERVED R/W-X 7 6 5 4 RESERVED R/W-X Table 10-42.
PAGE 859
Cryptography Registers www.ti.com 10.2.1.33 DMAPROTCTL Register (Offset = 704h) [reset = X] DMAPROTCTL is shown in Figure 10-35 and described in Table 10-43. Master Protection Control Figure 10-35. DMAPROTCTL Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 RESERVED R/W-X 8 7 RESERVED R/W-X 22 21 20 19 18 17 16 6 5 4 3 2 1 0 EN R/W-X Table 10-43.
PAGE 860
Cryptography Registers www.ti.com 10.2.1.34 SWRESET Register (Offset = 740h) [reset = X] SWRESET is shown in Figure 10-36 and described in Table 10-44. Software Reset Figure 10-36. SWRESET Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RESET R/W1C-X RESERVED R/W-X 23 22 21 20 RESERVED R/W-X 15 14 13 12 RESERVED R/W-X 7 6 5 4 RESERVED R/W-X Table 10-44.
PAGE 861
Cryptography Registers www.ti.com 10.2.1.35 IRQTYPE Register (Offset = 780h) [reset = X] IRQTYPE is shown in Figure 10-37 and described in Table 10-45. Interrupt Configuration Figure 10-37. IRQTYPE Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 RESERVED R/W-X 8 7 RESERVED R/W-X 22 21 20 19 18 17 16 6 5 4 3 2 1 0 IEN R/W-X Table 10-45.
PAGE 862
Cryptography Registers www.ti.com 10.2.1.36 IRQEN Register (Offset = 784h) [reset = X] IRQEN is shown in Figure 10-38 and described in Table 10-46. Interrupt Enable Figure 10-38. IRQEN Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 DMA_IN_DON E R/W-X 0 RESULT_AVAI L R/W-X RESERVED R/W-X 23 22 21 20 RESERVED R/W-X 15 14 13 12 RESERVED R/W-X 7 6 5 4 RESERVED R/W-X Table 10-46.
PAGE 863
Cryptography Registers www.ti.com 10.2.1.37 IRQCLR Register (Offset = 788h) [reset = X] IRQCLR is shown in Figure 10-39 and described in Table 10-47. Interrupt Clear Figure 10-39. IRQCLR Register 31 DMA_BUS_ER R W-X 30 KEY_ST_WR_ ERR W-X 29 KEY_ST_RD_E RR W-X 28 23 22 21 20 27 26 RESERVED 25 24 W-X 19 18 17 16 11 10 9 8 3 2 1 DMA_IN_DON E W-X 0 RESULT_AVAI L W-X RESERVED W-X 15 14 13 12 RESERVED W-X 7 6 5 4 RESERVED W-X Table 10-47.
PAGE 864
Cryptography Registers www.ti.com 10.2.1.38 IRQSET Register (Offset = 78Ch) [reset = X] IRQSET is shown in Figure 10-40 and described in Table 10-48. Interrupt Set Figure 10-40. IRQSET Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 DMA_IN_DON E W-X 0 RESULT_AVAI L W-X RESERVED W-X 23 22 21 20 RESERVED W-X 15 14 13 12 RESERVED W-X 7 6 5 4 RESERVED W-X Table 10-48.
PAGE 865
Cryptography Registers www.ti.com 10.2.1.39 IRQSTAT Register (Offset = 790h) [reset = X] IRQSTAT is shown in Figure 10-41 and described in Table 10-49. Interrupt Status Figure 10-41. IRQSTAT Register 31 DMA_BUS_ER R R-X 30 KEY_ST_WR_ ERR R-X 29 KEY_ST_RD_E RR R-X 28 23 22 21 20 27 26 RESERVED 25 24 R-X 19 18 17 16 11 10 9 8 3 2 1 DMA_IN_DON E R-X 0 RESULT_AVAI L R-X RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 4 RESERVED R-X Table 10-49.
PAGE 866
Cryptography Registers www.ti.com 10.2.1.40 HWVER Register (Offset = 7FCh) [reset = 91118778h] HWVER is shown in Figure 10-42 and described in Table 10-50. CTRL Module Version Figure 10-42. HWVER Register 31 30 29 RESERVED R-9h 15 14 13 28 27 26 25 HW_MAJOR_VER R-1h 12 11 10 VER_NUM_COMPL R-87h 9 24 23 8 7 22 21 HW_MINOR_VER R-1h 6 5 20 19 4 3 VER_NUM R-78h 18 17 HW_PATCH_LVL R-1h 2 1 16 0 Table 10-50.
PAGE 867
Chapter 11 SWCU117A – February 2015 – Revised March 2015 I/O Control This chapter describes the input/output controller (IOC) and the general-purpose inputs/outputs (GPIOs). The IOC design provides a flexible configuration, as most of the peripheral ports can be mapped to any of the physical I/O pads (I/O at die boundary). The CC26xx chameleon series has up to 31 I/O pins configurable as GPIO or to a peripheral function. Topic ...............................................................................
PAGE 868
Introduction www.ti.com 11.1 Introduction The I/O controller configures pins and map peripheral signals to physical pins (DIOx) on the CC26xx package. This chapter explains the IOC implementation and gives a few examples on how to map peripheral functions to pins chosen by the user.
PAGE 869
I/O Mapping and Configuration www.ti.com 11.3 I/O Mapping and Configuration The MCU IOC can map a number of peripheral modules such as GPIO, SSI (SPI), UART, I2C, and I2S to any of the available I/Os. The peripherals AUX and JTAG are limited to specific I/O pins. Each type of peripheral signal has a unique PORTID which can be assigned selected I/O pins (referenced as DIOs). lists of all the available PORTIDs. 11.3.
PAGE 870
I/O Mapping and Configuration www.ti.com 11.3.3 Map 32-kHz System Clock (LF Clock) to DIO/PIN The AON IOC contains the output enable control for the 32-kHz LF system clock output, and the clock signal has its own PORTID called AON_CLK32K (0x7). This makes it easy to output the clock signal to a pin. Map the clock to a chosen DIO, and enable the clock output by setting the [AON_IOC:CLK32KCTL.OE_N] to 0x0.
PAGE 871
Unused I/O Pins www.ti.com 11.6 Unused I/O Pins By default, the I/O driver (output) and input buffer (input) are disabled at power on or reset, and thus the I/O pin can safely be left unconnected (floating). If the I/O pin is tri-stated and connected to a node with a different voltage potential; there might be a small leakage current going through the pin. The same applies to an I/O pin configured as input, where the pin is connected to a voltage source (for example VDD/2).
PAGE 872
I/O Pin Mapping www.ti.com 11.8 I/O Pin Mapping Table 11-2 shows the I/O pin mapping for different package types. Table 11-2.
PAGE 873
Peripheral PORTIDs www.ti.com 11.9 Peripheral PORTIDs Table 11-3 lists the different PORTID signals. Table 11-3.
PAGE 874
I/O Pin www.ti.com Figure 11-2. Generic I/O pin (Simplified) Vio Pullup enable Output enable (OE) Pin (DIOx) Output Pulldown enable Input enable (IE) Input 11.10.2 Pin Configuration The IOC lets software configure the pins based on the application requirements. The software can configure different characteristic settings for any or all of the I/O pins.
PAGE 875
I/O Control Registers www.ti.com 11.
PAGE 876
I/O Control Registers www.ti.com 11.11.1 AON_IOC Registers Table 11-4 lists the memory-mapped registers for the AON_IOC. All register offset addresses not listed in Table 11-4 should be considered as reserved locations and the register contents should not be modified. Table 11-4. AON_IOC Registers 876 Offset Acronym Register Name 0h IOSTRMIN IO Drive Strength Minimum Section 11.11.1.1 4h IOSTRMED IO Drive Strength Medium Section 11.11.1.2 8h IOSTRMAX IO Drive Strength Maximum Section 11.
PAGE 877
I/O Control Registers www.ti.com 11.11.1.1 IOSTRMIN Register (Offset = 0h) [reset = X] IOSTRMIN is shown in Figure 11-3 and described in Table 11-5. Internal. Only to be used through TI provided API. Figure 11-3. IOSTRMIN Register 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 RESERVED R-X 9 8 RESERVED R-X 7 22 21 20 19 18 6 5 4 3 2 17 16 1 0 GRAY_CODE R/W-3h Table 11-5. IOSTRMIN Register Field Descriptions Field Type Reset Description 31-3 Bit RESERVED R X Internal.
PAGE 878
I/O Control Registers www.ti.com 11.11.1.2 IOSTRMED Register (Offset = 4h) [reset = X] IOSTRMED is shown in Figure 11-4 and described in Table 11-6. Internal. Only to be used through TI provided API. Figure 11-4. IOSTRMED Register 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 RESERVED R-X 9 8 RESERVED R-X 7 22 21 20 19 18 6 5 4 3 2 17 16 1 0 GRAY_CODE R/W-6h Table 11-6.
PAGE 879
I/O Control Registers www.ti.com 11.11.1.3 IOSTRMAX Register (Offset = 8h) [reset = X] IOSTRMAX is shown in Figure 11-5 and described in Table 11-7. Internal. Only to be used through TI provided API. Figure 11-5. IOSTRMAX Register 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 RESERVED R-X 9 8 RESERVED R-X 7 22 21 20 19 18 6 5 4 3 2 17 16 1 0 GRAY_CODE R/W-5h Table 11-7. IOSTRMAX Register Field Descriptions Field Type Reset Description 31-3 Bit RESERVED R X Internal.
PAGE 880
I/O Control Registers www.ti.com 11.11.1.4 IOCLATCH Register (Offset = Ch) [reset = X] IOCLATCH is shown in Figure 11-6 and described in Table 11-8. IO Latch Control Controls transparency of all latches holding I/O or configuration state from the MCU IOC Figure 11-6. IOCLATCH Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 RESERVED R-X 8 7 RESERVED R-X 22 21 20 19 18 17 16 6 5 4 3 2 1 0 EN R/W1h Table 11-8.
PAGE 881
I/O Control Registers www.ti.com 11.11.1.5 CLK32KCTL Register (Offset = 10h) [reset = X] CLK32KCTL is shown in Figure 11-7 and described in Table 11-9. SCLK_LF External Output Control Figure 11-7. CLK32KCTL Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 OE_N R/W-1h RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 4 RESERVED R-X Table 11-9.
PAGE 882
I/O Control Registers 882 I/O Control www.ti.
PAGE 883
I/O Control Registers www.ti.com 11.11.2 IOC Registers Table 11-10 lists the memory-mapped registers for the IOC. All register offset addresses not listed in Table 11-10 should be considered as reserved locations and the register contents should not be modified. Table 11-10. IOC Registers Offset Acronym Register Name 0h IOCFG0 Configuration of DIO0 Section 11.11.2.1 Section 4h IOCFG1 Configuration of DIO1 Section 11.11.2.2 8h IOCFG2 Configuration of DIO2 Section 11.11.2.
PAGE 884
I/O Control Registers www.ti.com 11.11.2.1 IOCFG0 Register (Offset = 0h) [reset = X] IOCFG0 is shown in Figure 11-8 and described in Table 11-11. Configuration of DIO0 Figure 11-8.
PAGE 885
I/O Control Registers www.ti.com Table 11-11. IOCFG0 Register Field Descriptions (continued) Bit Field Type Reset Description 15 RESERVED R X Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 14-13 PULL_CTL R/W 3h Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull 12 SLEW_RED R/W X 0: Normal slew rate 1: Enables reduced slew rate in output driver.
PAGE 886
I/O Control Registers www.ti.com Table 11-11.
PAGE 887
I/O Control Registers www.ti.com Table 11-11.
PAGE 888
I/O Control Registers www.ti.com 11.11.2.2 IOCFG1 Register (Offset = 4h) [reset = X] IOCFG1 is shown in Figure 11-9 and described in Table 11-12. Configuration of DIO1 Figure 11-9.
PAGE 889
I/O Control Registers www.ti.com Table 11-12. IOCFG1 Register Field Descriptions (continued) Bit Field Type Reset Description 15 RESERVED R X Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 14-13 PULL_CTL R/W 3h Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull 12 SLEW_RED R/W X 0: Normal slew rate 1: Enables reduced slew rate in output driver.
PAGE 890
I/O Control Registers www.ti.com Table 11-12.
PAGE 891
I/O Control Registers www.ti.com Table 11-12.
PAGE 892
I/O Control Registers www.ti.com 11.11.2.3 IOCFG2 Register (Offset = 8h) [reset = X] IOCFG2 is shown in Figure 11-10 and described in Table 11-13. Configuration of DIO2 Figure 11-10.
PAGE 893
I/O Control Registers www.ti.com Table 11-13. IOCFG2 Register Field Descriptions (continued) Bit Field Type Reset Description 15 RESERVED R X Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 14-13 PULL_CTL R/W 3h Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull 12 SLEW_RED R/W X 0: Normal slew rate 1: Enables reduced slew rate in output driver.
PAGE 894
I/O Control Registers www.ti.com Table 11-13.
PAGE 895
I/O Control Registers www.ti.com Table 11-13.
PAGE 896
I/O Control Registers www.ti.com 11.11.2.4 IOCFG3 Register (Offset = Ch) [reset = X] IOCFG3 is shown in Figure 11-11 and described in Table 11-14. Configuration of DIO3 Figure 11-11.
PAGE 897
I/O Control Registers www.ti.com Table 11-14. IOCFG3 Register Field Descriptions (continued) Bit Field Type Reset Description 15 RESERVED R X Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 14-13 PULL_CTL R/W 3h Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull 12 SLEW_RED R/W X 0: Normal slew rate 1: Enables reduced slew rate in output driver.
PAGE 898
I/O Control Registers www.ti.com Table 11-14.
PAGE 899
I/O Control Registers www.ti.com Table 11-14.
PAGE 900
I/O Control Registers www.ti.com 11.11.2.5 IOCFG4 Register (Offset = 10h) [reset = X] IOCFG4 is shown in Figure 11-12 and described in Table 11-15. Configuration of DIO4 Figure 11-12.
PAGE 901
I/O Control Registers www.ti.com Table 11-15. IOCFG4 Register Field Descriptions (continued) Bit Field Type Reset Description 15 RESERVED R X Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 14-13 PULL_CTL R/W 3h Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull 12 SLEW_RED R/W X 0: Normal slew rate 1: Enables reduced slew rate in output driver.
PAGE 902
I/O Control Registers www.ti.com Table 11-15.
PAGE 903
I/O Control Registers www.ti.com Table 11-15.
PAGE 904
I/O Control Registers www.ti.com 11.11.2.6 IOCFG5 Register (Offset = 14h) [reset = X] IOCFG5 is shown in Figure 11-13 and described in Table 11-16. Configuration of DIO5 Figure 11-13.
PAGE 905
I/O Control Registers www.ti.com Table 11-16. IOCFG5 Register Field Descriptions (continued) Bit Field Type Reset Description 15 RESERVED R X Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 14-13 PULL_CTL R/W 3h Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull 12 SLEW_RED R/W X 0: Normal slew rate 1: Enables reduced slew rate in output driver.
PAGE 906
I/O Control Registers www.ti.com Table 11-16.
PAGE 907
I/O Control Registers www.ti.com Table 11-16.
PAGE 908
I/O Control Registers www.ti.com 11.11.2.7 IOCFG6 Register (Offset = 18h) [reset = X] IOCFG6 is shown in Figure 11-14 and described in Table 11-17. Configuration of DIO6 Figure 11-14.
PAGE 909
I/O Control Registers www.ti.com Table 11-17. IOCFG6 Register Field Descriptions (continued) Bit Field Type Reset Description 15 RESERVED R X Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 14-13 PULL_CTL R/W 3h Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull 12 SLEW_RED R/W X 0: Normal slew rate 1: Enables reduced slew rate in output driver.
PAGE 910
I/O Control Registers www.ti.com Table 11-17.
PAGE 911
I/O Control Registers www.ti.com Table 11-17.
PAGE 912
I/O Control Registers www.ti.com 11.11.2.8 IOCFG7 Register (Offset = 1Ch) [reset = X] IOCFG7 is shown in Figure 11-15 and described in Table 11-18. Configuration of DIO7 Figure 11-15.
PAGE 913
I/O Control Registers www.ti.com Table 11-18. IOCFG7 Register Field Descriptions (continued) Bit Field Type Reset Description 15 RESERVED R X Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 14-13 PULL_CTL R/W 3h Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull 12 SLEW_RED R/W X 0: Normal slew rate 1: Enables reduced slew rate in output driver.
PAGE 914
I/O Control Registers www.ti.com Table 11-18.
PAGE 915
I/O Control Registers www.ti.com Table 11-18.
PAGE 916
I/O Control Registers www.ti.com 11.11.2.9 IOCFG8 Register (Offset = 20h) [reset = X] IOCFG8 is shown in Figure 11-16 and described in Table 11-19. Configuration of DIO8 Figure 11-16.
PAGE 917
I/O Control Registers www.ti.com Table 11-19. IOCFG8 Register Field Descriptions (continued) Bit Field Type Reset Description 15 RESERVED R X Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 14-13 PULL_CTL R/W 3h Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull 12 SLEW_RED R/W X 0: Normal slew rate 1: Enables reduced slew rate in output driver.
PAGE 918
I/O Control Registers www.ti.com Table 11-19.
PAGE 919
I/O Control Registers www.ti.com Table 11-19.
PAGE 920
I/O Control Registers www.ti.com 11.11.2.10 IOCFG9 Register (Offset = 24h) [reset = X] IOCFG9 is shown in Figure 11-17 and described in Table 11-20. Configuration of DIO9 Figure 11-17.
PAGE 921
I/O Control Registers www.ti.com Table 11-20. IOCFG9 Register Field Descriptions (continued) Bit Field Type Reset Description 15 RESERVED R X Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 14-13 PULL_CTL R/W 3h Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull 12 SLEW_RED R/W X 0: Normal slew rate 1: Enables reduced slew rate in output driver.
PAGE 922
I/O Control Registers www.ti.com Table 11-20.
PAGE 923
I/O Control Registers www.ti.com Table 11-20.
PAGE 924
I/O Control Registers www.ti.com 11.11.2.11 IOCFG10 Register (Offset = 28h) [reset = X] IOCFG10 is shown in Figure 11-18 and described in Table 11-21. Configuration of DIO10 Figure 11-18.
PAGE 925
I/O Control Registers www.ti.com Table 11-21. IOCFG10 Register Field Descriptions (continued) Bit Field Type Reset Description 15 RESERVED R X Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 14-13 PULL_CTL R/W 3h Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull 12 SLEW_RED R/W X 0: Normal slew rate 1: Enables reduced slew rate in output driver.
PAGE 926
I/O Control Registers www.ti.com Table 11-21.
PAGE 927
I/O Control Registers www.ti.com Table 11-21.
PAGE 928
I/O Control Registers www.ti.com 11.11.2.12 IOCFG11 Register (Offset = 2Ch) [reset = X] IOCFG11 is shown in Figure 11-19 and described in Table 11-22. Configuration of DIO11 Figure 11-19.
PAGE 929
I/O Control Registers www.ti.com Table 11-22. IOCFG11 Register Field Descriptions (continued) Bit Field Type Reset Description 15 RESERVED R X Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 14-13 PULL_CTL R/W 3h Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull 12 SLEW_RED R/W X 0: Normal slew rate 1: Enables reduced slew rate in output driver.
PAGE 930
I/O Control Registers www.ti.com Table 11-22.
PAGE 931
I/O Control Registers www.ti.com Table 11-22.
PAGE 932
I/O Control Registers www.ti.com 11.11.2.13 IOCFG12 Register (Offset = 30h) [reset = X] IOCFG12 is shown in Figure 11-20 and described in Table 11-23. Configuration of DIO12 Figure 11-20.
PAGE 933
I/O Control Registers www.ti.com Table 11-23. IOCFG12 Register Field Descriptions (continued) Bit Field Type Reset Description 15 RESERVED R X Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 14-13 PULL_CTL R/W 3h Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull 12 SLEW_RED R/W X 0: Normal slew rate 1: Enables reduced slew rate in output driver.
PAGE 934
I/O Control Registers www.ti.com Table 11-23.
PAGE 935
I/O Control Registers www.ti.com Table 11-23.
PAGE 936
I/O Control Registers www.ti.com 11.11.2.14 IOCFG13 Register (Offset = 34h) [reset = X] IOCFG13 is shown in Figure 11-21 and described in Table 11-24. Configuration of DIO13 Figure 11-21.
PAGE 937
I/O Control Registers www.ti.com Table 11-24. IOCFG13 Register Field Descriptions (continued) Bit Field Type Reset Description 15 RESERVED R X Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 14-13 PULL_CTL R/W 3h Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull 12 SLEW_RED R/W X 0: Normal slew rate 1: Enables reduced slew rate in output driver.
PAGE 938
I/O Control Registers www.ti.com Table 11-24.
PAGE 939
I/O Control Registers www.ti.com Table 11-24.
PAGE 940
I/O Control Registers www.ti.com 11.11.2.15 IOCFG14 Register (Offset = 38h) [reset = X] IOCFG14 is shown in Figure 11-22 and described in Table 11-25. Configuration of DIO14 Figure 11-22.
PAGE 941
I/O Control Registers www.ti.com Table 11-25. IOCFG14 Register Field Descriptions (continued) Bit Field Type Reset Description 15 RESERVED R X Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 14-13 PULL_CTL R/W 3h Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull 12 SLEW_RED R/W X 0: Normal slew rate 1: Enables reduced slew rate in output driver.
PAGE 942
I/O Control Registers www.ti.com Table 11-25.
PAGE 943
I/O Control Registers www.ti.com Table 11-25.
PAGE 944
I/O Control Registers www.ti.com 11.11.2.16 IOCFG15 Register (Offset = 3Ch) [reset = X] IOCFG15 is shown in Figure 11-23 and described in Table 11-26. Configuration of DIO15 Figure 11-23.
PAGE 945
I/O Control Registers www.ti.com Table 11-26. IOCFG15 Register Field Descriptions (continued) Bit Field Type Reset Description 15 RESERVED R X Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 14-13 PULL_CTL R/W 3h Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull 12 SLEW_RED R/W X 0: Normal slew rate 1: Enables reduced slew rate in output driver.
PAGE 946
I/O Control Registers www.ti.com Table 11-26.
PAGE 947
I/O Control Registers www.ti.com Table 11-26.
PAGE 948
I/O Control Registers www.ti.com 11.11.2.17 IOCFG16 Register (Offset = 40h) [reset = X] IOCFG16 is shown in Figure 11-24 and described in Table 11-27. Configuration of DIO16 Figure 11-24.
PAGE 949
I/O Control Registers www.ti.com Table 11-27. IOCFG16 Register Field Descriptions (continued) Bit Field Type Reset Description 15 RESERVED R X Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 14-13 PULL_CTL R/W 3h Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull 12 SLEW_RED R/W X 0: Normal slew rate 1: Enables reduced slew rate in output driver.
PAGE 950
I/O Control Registers www.ti.com Table 11-27.
PAGE 951
I/O Control Registers www.ti.com Table 11-27.
PAGE 952
I/O Control Registers www.ti.com 11.11.2.18 IOCFG17 Register (Offset = 44h) [reset = X] IOCFG17 is shown in Figure 11-25 and described in Table 11-28. Configuration of DIO17 Figure 11-25.
PAGE 953
I/O Control Registers www.ti.com Table 11-28. IOCFG17 Register Field Descriptions (continued) Bit Field Type Reset Description 15 RESERVED R X Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 14-13 PULL_CTL R/W 3h Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull 12 SLEW_RED R/W X 0: Normal slew rate 1: Enables reduced slew rate in output driver.
PAGE 954
I/O Control Registers www.ti.com Table 11-28.
PAGE 955
I/O Control Registers www.ti.com Table 11-28.
PAGE 956
I/O Control Registers www.ti.com 11.11.2.19 IOCFG18 Register (Offset = 48h) [reset = X] IOCFG18 is shown in Figure 11-26 and described in Table 11-29. Configuration of DIO18 Figure 11-26.
PAGE 957
I/O Control Registers www.ti.com Table 11-29. IOCFG18 Register Field Descriptions (continued) Bit Field Type Reset Description 15 RESERVED R X Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 14-13 PULL_CTL R/W 3h Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull 12 SLEW_RED R/W X 0: Normal slew rate 1: Enables reduced slew rate in output driver.
PAGE 958
I/O Control Registers www.ti.com Table 11-29.
PAGE 959
I/O Control Registers www.ti.com Table 11-29.
PAGE 960
I/O Control Registers www.ti.com 11.11.2.20 IOCFG19 Register (Offset = 4Ch) [reset = X] IOCFG19 is shown in Figure 11-27 and described in Table 11-30. Configuration of DIO19 Figure 11-27.
PAGE 961
I/O Control Registers www.ti.com Table 11-30. IOCFG19 Register Field Descriptions (continued) Bit Field Type Reset Description 15 RESERVED R X Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 14-13 PULL_CTL R/W 3h Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull 12 SLEW_RED R/W X 0: Normal slew rate 1: Enables reduced slew rate in output driver.
PAGE 962
I/O Control Registers www.ti.com Table 11-30.
PAGE 963
I/O Control Registers www.ti.com Table 11-30.
PAGE 964
I/O Control Registers www.ti.com 11.11.2.21 IOCFG20 Register (Offset = 50h) [reset = X] IOCFG20 is shown in Figure 11-28 and described in Table 11-31. Configuration of DIO20 Figure 11-28.
PAGE 965
I/O Control Registers www.ti.com Table 11-31. IOCFG20 Register Field Descriptions (continued) Bit Field Type Reset Description 15 RESERVED R X Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 14-13 PULL_CTL R/W 3h Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull 12 SLEW_RED R/W X 0: Normal slew rate 1: Enables reduced slew rate in output driver.
PAGE 966
I/O Control Registers www.ti.com Table 11-31.
PAGE 967
I/O Control Registers www.ti.com Table 11-31.
PAGE 968
I/O Control Registers www.ti.com 11.11.2.22 IOCFG21 Register (Offset = 54h) [reset = X] IOCFG21 is shown in Figure 11-29 and described in Table 11-32. Configuration of DIO21 Figure 11-29.
PAGE 969
I/O Control Registers www.ti.com Table 11-32. IOCFG21 Register Field Descriptions (continued) Bit Field Type Reset Description 15 RESERVED R X Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 14-13 PULL_CTL R/W 3h Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull 12 SLEW_RED R/W X 0: Normal slew rate 1: Enables reduced slew rate in output driver.
PAGE 970
I/O Control Registers www.ti.com Table 11-32.
PAGE 971
I/O Control Registers www.ti.com Table 11-32.
PAGE 972
I/O Control Registers www.ti.com 11.11.2.23 IOCFG22 Register (Offset = 58h) [reset = X] IOCFG22 is shown in Figure 11-30 and described in Table 11-33. Configuration of DIO22 Figure 11-30.
PAGE 973
I/O Control Registers www.ti.com Table 11-33. IOCFG22 Register Field Descriptions (continued) Bit Field Type Reset Description 15 RESERVED R X Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 14-13 PULL_CTL R/W 3h Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull 12 SLEW_RED R/W X 0: Normal slew rate 1: Enables reduced slew rate in output driver.
PAGE 974
I/O Control Registers www.ti.com Table 11-33.
PAGE 975
I/O Control Registers www.ti.com Table 11-33.
PAGE 976
I/O Control Registers www.ti.com 11.11.2.24 IOCFG23 Register (Offset = 5Ch) [reset = X] IOCFG23 is shown in Figure 11-31 and described in Table 11-34. Configuration of DIO23 Figure 11-31.
PAGE 977
I/O Control Registers www.ti.com Table 11-34. IOCFG23 Register Field Descriptions (continued) Bit Field Type Reset Description 15 RESERVED R X Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 14-13 PULL_CTL R/W 3h Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull 12 SLEW_RED R/W X 0: Normal slew rate 1: Enables reduced slew rate in output driver.
PAGE 978
I/O Control Registers www.ti.com Table 11-34.
PAGE 979
I/O Control Registers www.ti.com Table 11-34.
PAGE 980
I/O Control Registers www.ti.com 11.11.2.25 IOCFG24 Register (Offset = 60h) [reset = X] IOCFG24 is shown in Figure 11-32 and described in Table 11-35. Configuration of DIO24 Figure 11-32.
PAGE 981
I/O Control Registers www.ti.com Table 11-35. IOCFG24 Register Field Descriptions (continued) Bit Field Type Reset Description 15 RESERVED R X Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 14-13 PULL_CTL R/W 3h Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull 12 SLEW_RED R/W X 0: Normal slew rate 1: Enables reduced slew rate in output driver.
PAGE 982
I/O Control Registers www.ti.com Table 11-35.
PAGE 983
I/O Control Registers www.ti.com Table 11-35.
PAGE 984
I/O Control Registers www.ti.com 11.11.2.26 IOCFG25 Register (Offset = 64h) [reset = X] IOCFG25 is shown in Figure 11-33 and described in Table 11-36. Configuration of DIO25 Figure 11-33.
PAGE 985
I/O Control Registers www.ti.com Table 11-36. IOCFG25 Register Field Descriptions (continued) Bit Field Type Reset Description 15 RESERVED R X Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 14-13 PULL_CTL R/W 3h Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull 12 SLEW_RED R/W X 0: Normal slew rate 1: Enables reduced slew rate in output driver.
PAGE 986
I/O Control Registers www.ti.com Table 11-36.
PAGE 987
I/O Control Registers www.ti.com Table 11-36.
PAGE 988
I/O Control Registers www.ti.com 11.11.2.27 IOCFG26 Register (Offset = 68h) [reset = X] IOCFG26 is shown in Figure 11-34 and described in Table 11-37. Configuration of DIO26 Figure 11-34.
PAGE 989
I/O Control Registers www.ti.com Table 11-37. IOCFG26 Register Field Descriptions (continued) Bit Field Type Reset Description 15 RESERVED R X Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 14-13 PULL_CTL R/W 3h Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull 12 SLEW_RED R/W X 0: Normal slew rate 1: Enables reduced slew rate in output driver.
PAGE 990
I/O Control Registers www.ti.com Table 11-37.
PAGE 991
I/O Control Registers www.ti.com Table 11-37.
PAGE 992
I/O Control Registers www.ti.com 11.11.2.28 IOCFG27 Register (Offset = 6Ch) [reset = X] IOCFG27 is shown in Figure 11-35 and described in Table 11-38. Configuration of DIO27 Figure 11-35.
PAGE 993
I/O Control Registers www.ti.com Table 11-38. IOCFG27 Register Field Descriptions (continued) Bit Field Type Reset Description 15 RESERVED R X Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 14-13 PULL_CTL R/W 3h Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull 12 SLEW_RED R/W X 0: Normal slew rate 1: Enables reduced slew rate in output driver.
PAGE 994
I/O Control Registers www.ti.com Table 11-38.
PAGE 995
I/O Control Registers www.ti.com Table 11-38.
PAGE 996
I/O Control Registers www.ti.com 11.11.2.29 IOCFG28 Register (Offset = 70h) [reset = X] IOCFG28 is shown in Figure 11-36 and described in Table 11-39. Configuration of DIO28 Figure 11-36.
PAGE 997
I/O Control Registers www.ti.com Table 11-39. IOCFG28 Register Field Descriptions (continued) Bit Field Type Reset Description 15 RESERVED R X Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 14-13 PULL_CTL R/W 3h Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull 12 SLEW_RED R/W X 0: Normal slew rate 1: Enables reduced slew rate in output driver.
PAGE 998
I/O Control Registers www.ti.com Table 11-39.
PAGE 999
I/O Control Registers www.ti.com Table 11-39.
PAGE 1000
I/O Control Registers www.ti.com 11.11.2.30 IOCFG29 Register (Offset = 74h) [reset = X] IOCFG29 is shown in Figure 11-37 and described in Table 11-40. Configuration of DIO29 Figure 11-37.
PAGE 1001
I/O Control Registers www.ti.com Table 11-40. IOCFG29 Register Field Descriptions (continued) Bit Field Type Reset Description 15 RESERVED R X Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 14-13 PULL_CTL R/W 3h Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull 12 SLEW_RED R/W X 0: Normal slew rate 1: Enables reduced slew rate in output driver.
PAGE 1002
I/O Control Registers www.ti.com Table 11-40.
PAGE 1003
I/O Control Registers www.ti.com Table 11-40.
PAGE 1004
I/O Control Registers www.ti.com 11.11.2.31 IOCFG30 Register (Offset = 78h) [reset = X] IOCFG30 is shown in Figure 11-38 and described in Table 11-41. Configuration of DIO30 Figure 11-38.
PAGE 1005
I/O Control Registers www.ti.com Table 11-41. IOCFG30 Register Field Descriptions (continued) Bit Field Type Reset Description 15 RESERVED R X Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 14-13 PULL_CTL R/W 3h Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull 12 SLEW_RED R/W X 0: Normal slew rate 1: Enables reduced slew rate in output driver.
PAGE 1006
I/O Control Registers www.ti.com Table 11-41.
PAGE 1007
I/O Control Registers www.ti.com Table 11-41.
PAGE 1008
I/O Control Registers www.ti.com 11.11.2.32 IOCFG31 Register (Offset = 7Ch) [reset = X] IOCFG31 is shown in Figure 11-39 and described in Table 11-42. Configuration of DIO31 Figure 11-39.
PAGE 1009
I/O Control Registers www.ti.com Table 11-42. IOCFG31 Register Field Descriptions (continued) Bit Field Type Reset Description 15 RESERVED R X Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 14-13 PULL_CTL R/W 3h Pull control 1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull 12 SLEW_RED R/W X 0: Normal slew rate 1: Enables reduced slew rate in output driver.
PAGE 1010
I/O Control Registers www.ti.com Table 11-42.
PAGE 1011
I/O Control Registers www.ti.com Table 11-42.
PAGE 1012
I/O Control Registers www.ti.com 11.11.3 GPIO Registers Table 11-43 lists the memory-mapped registers for the GPIO. All register offset addresses not listed in Table 11-43 should be considered as reserved locations and the register contents should not be modified. Table 11-43. GPIO Registers 1012 Offset Acronym Register Name Section 0h DOUT3_0 Data Out 0 to 3 Section 11.11.3.1 4h DOUT7_4 Data Out 4 to 7 Section 11.11.3.2 8h DOUT11_8 Data Out 8 to 11 Section 11.11.3.
PAGE 1013
I/O Control Registers www.ti.com 11.11.3.1 DOUT3_0 Register (Offset = 0h) [reset = X] DOUT3_0 is shown in Figure 11-40 and described in Table 11-44. Data Out 0 to 3 Alias register for byte access to each bit in DOUT31_0 Figure 11-40. DOUT3_0 Register 31 30 29 28 RESERVED R-X 27 26 25 24 DIO3 W-X 23 22 21 20 RESERVED R-X 19 18 17 16 DIO2 W-X 15 14 13 12 RESERVED R-X 11 10 9 8 DIO1 W-X 7 6 5 4 RESERVED R-X 3 2 1 0 DIO0 W-X Table 11-44.
PAGE 1014
I/O Control Registers www.ti.com 11.11.3.2 DOUT7_4 Register (Offset = 4h) [reset = X] DOUT7_4 is shown in Figure 11-41 and described in Table 11-45. Data Out 4 to 7 Alias register for byte access to each bit in DOUT31_0 Figure 11-41. DOUT7_4 Register 31 30 29 28 RESERVED R-X 27 26 25 24 DIO7 W-X 23 22 21 20 RESERVED R-X 19 18 17 16 DIO6 W-X 15 14 13 12 RESERVED R-X 11 10 9 8 DIO5 W-X 7 6 5 4 RESERVED R-X 3 2 1 0 DIO4 W-X Table 11-45.
PAGE 1015
I/O Control Registers www.ti.com 11.11.3.3 DOUT11_8 Register (Offset = 8h) [reset = X] DOUT11_8 is shown in Figure 11-42 and described in Table 11-46. Data Out 8 to 11 Alias register for byte access to each bit in DOUT31_0 Figure 11-42. DOUT11_8 Register 31 30 29 28 RESERVED R-X 27 26 25 24 DIO11 W-X 23 22 21 20 RESERVED R-X 19 18 17 16 DIO10 W-X 15 14 13 12 RESERVED R-X 11 10 9 8 DIO9 W-X 7 6 5 4 RESERVED R-X 3 2 1 0 DIO8 W-X Table 11-46.
PAGE 1016
I/O Control Registers www.ti.com 11.11.3.4 DOUT15_12 Register (Offset = Ch) [reset = X] DOUT15_12 is shown in Figure 11-43 and described in Table 11-47. Data Out 12 to 15 Alias register for byte access to each bit in DOUT31_0 Figure 11-43. DOUT15_12 Register 31 30 29 28 RESERVED R-X 27 26 25 24 DIO15 W-X 23 22 21 20 RESERVED R-X 19 18 17 16 DIO14 W-X 15 14 13 12 RESERVED R-X 11 10 9 8 DIO13 W-X 7 6 5 4 RESERVED R-X 3 2 1 0 DIO12 W-X Table 11-47.
PAGE 1017
I/O Control Registers www.ti.com 11.11.3.5 DOUT19_16 Register (Offset = 10h) [reset = X] DOUT19_16 is shown in Figure 11-44 and described in Table 11-48. Data Out 16 to 19 Alias register for byte access to each bit in DOUT31_0 Figure 11-44. DOUT19_16 Register 31 30 29 28 RESERVED R-X 27 26 25 24 DIO19 W-X 23 22 21 20 RESERVED R-X 19 18 17 16 DIO18 W-X 15 14 13 12 RESERVED R-X 11 10 9 8 DIO17 W-X 7 6 5 4 RESERVED R-X 3 2 1 0 DIO16 W-X Table 11-48.
PAGE 1018
I/O Control Registers www.ti.com 11.11.3.6 DOUT23_20 Register (Offset = 14h) [reset = X] DOUT23_20 is shown in Figure 11-45 and described in Table 11-49. Data Out 20 to 23 Alias register for byte access to each bit in DOUT31_0 Figure 11-45. DOUT23_20 Register 31 30 29 28 RESERVED R-X 27 26 25 24 DIO23 W-X 23 22 21 20 RESERVED R-X 19 18 17 16 DIO22 W-X 15 14 13 12 RESERVED R-X 11 10 9 8 DIO21 W-X 7 6 5 4 RESERVED R-X 3 2 1 0 DIO20 W-X Table 11-49.
PAGE 1019
I/O Control Registers www.ti.com 11.11.3.7 DOUT27_24 Register (Offset = 18h) [reset = X] DOUT27_24 is shown in Figure 11-46 and described in Table 11-50. Data Out 24 to 27 Alias register for byte access to each bit in DOUT31_0 Figure 11-46. DOUT27_24 Register 31 30 29 28 RESERVED R-X 27 26 25 24 DIO27 W-X 23 22 21 20 RESERVED R-X 19 18 17 16 DIO26 W-X 15 14 13 12 RESERVED R-X 11 10 9 8 DIO25 W-X 7 6 5 4 RESERVED R-X 3 2 1 0 DIO24 W-X Table 11-50.
PAGE 1020
I/O Control Registers www.ti.com 11.11.3.8 DOUT31_28 Register (Offset = 1Ch) [reset = X] DOUT31_28 is shown in Figure 11-47 and described in Table 11-51. Data Out 28 to 31 Alias register for byte access to each bit in DOUT31_0 Figure 11-47. DOUT31_28 Register 31 30 29 28 RESERVED R-X 27 26 25 24 DIO31 W-X 23 22 21 20 RESERVED R-X 19 18 17 16 DIO30 W-X 15 14 13 12 RESERVED R-X 11 10 9 8 DIO29 W-X 7 6 5 4 RESERVED R-X 3 2 1 0 DIO28 W-X Table 11-51.
PAGE 1021
I/O Control Registers www.ti.com 11.11.3.9 DOUT31_0 Register (Offset = 80h) [reset = X] DOUT31_0 is shown in Figure 11-48 and described in Table 11-52. Data Output for DIO 0 to 31 Figure 11-48.
PAGE 1022
I/O Control Registers www.ti.com Table 11-52.
PAGE 1023
I/O Control Registers www.ti.com 11.11.3.10 DOUTSET31_0 Register (Offset = 90h) [reset = X] DOUTSET31_0 is shown in Figure 11-49 and described in Table 11-53. Data Out Set Writing 1 to a bit position sets the corresponding bit in the DOUT31_0 register Figure 11-49.
PAGE 1024
I/O Control Registers www.ti.com Table 11-53.
PAGE 1025
I/O Control Registers www.ti.com 11.11.3.11 DOUTCLR31_0 Register (Offset = A0h) [reset = X] DOUTCLR31_0 is shown in Figure 11-50 and described in Table 11-54. Data Out Clear Writing 1 to a bit position clears the corresponding bit in the DOUT31_0 register Figure 11-50.
PAGE 1026
I/O Control Registers www.ti.com Table 11-54.
PAGE 1027
I/O Control Registers www.ti.com 11.11.3.12 DOUTTGL31_0 Register (Offset = B0h) [reset = X] DOUTTGL31_0 is shown in Figure 11-51 and described in Table 11-55. Data Out Toggle Writing 1 to a bit position will invert the corresponding DIO output. Figure 11-51.
PAGE 1028
I/O Control Registers www.ti.com Table 11-55.
PAGE 1029
I/O Control Registers www.ti.com 11.11.3.13 DIN31_0 Register (Offset = C0h) [reset = X] DIN31_0 is shown in Figure 11-52 and described in Table 11-56. Data Input from DIO 0 to 31 Figure 11-52.
PAGE 1030
I/O Control Registers www.ti.com Table 11-56.
PAGE 1031
I/O Control Registers www.ti.com 11.11.3.14 DOE31_0 Register (Offset = D0h) [reset = X] DOE31_0 is shown in Figure 11-53 and described in Table 11-57. Data Output Enable for DIO 0 to 31 Figure 11-53.
PAGE 1032
I/O Control Registers www.ti.com Table 11-57.
PAGE 1033
I/O Control Registers www.ti.com 11.11.3.15 EVFLAGS31_0 Register (Offset = E0h) [reset = X] EVFLAGS31_0 is shown in Figure 11-54 and described in Table 11-58. Event Register for DIO 0 to 31 Reading this registers will return 1 for triggered event and 0 for nontriggered events. Writing a 1 to a bit field will clear the event. The configuration of events is done inside MCU IOC, e.g. events for DIO #0 is configured in IOC:IOCFG0.EDGE_DET and IOC:IOCFG0.EDGE_IRQ_EN. Figure 11-54.
PAGE 1034
I/O Control Registers www.ti.com Table 11-58.
PAGE 1035
Chapter 12 SWCU117A – February 2015 – Revised March 2015 Micro Direct Memory Access (µDMA) This chapter describes the direct memory access (DMA) controller, known as μDMA. Topic 12.1 12.2 12.3 12.4 12.5 ........................................................................................................................... μDMA Introduction .......................................................................................... Block Diagram ...........................................................
PAGE 1036
μDMA Introduction www.ti.com 12.1 μDMA Introduction The CC26xx microcontroller includes a direct memory access (DMA) controller, known as μDMA. The μDMA controller provides a way to offload data transfer tasks from the Cortex®-M3 processor, allowing for more efficient use of the processor and the available bus bandwidth. The μDMA controller can perform transfers between memory and peripherals.
PAGE 1037
Functional Description www.ti.com Figure 12-1.
PAGE 1038
Functional Description www.ti.com Table 12-1.
PAGE 1039
Functional Description www.ti.com 12.3.2 Priority The μDMA controller assigns priority to each channel based on the channel number and the priority level bit for the channel. Channel 0 has the highest priority, and as the channel number increases, the priority of a channel decreases. Each channel has a priority-level bit to provide two levels of priority: default priority and high priority.
PAGE 1040
Functional Description www.ti.com 12.3.4.1 Single Request When a single request is detected (not a burst request), the μDMA controller transfers one item and then stops to wait for another request. NOTE: Channels 8, 13, 14, and 15 do not respond to a single request because waitonreq is tied low. 12.3.4.2 Burst Request When a burst request is detected, the μDMA controller transfers the number of items that is the lesser of the arbitration size or the number of items remaining in the transfer.
PAGE 1041
Functional Description www.ti.com Table 12-4 describes an individual control-structure entry in the control table. Each entry is aligned on a 16-byte boundary. The entry contains four long words: the source end pointer, the destination end pointer, the control word, and an unused entry. The inclusive end pointers point to the ending address of the transfer. If the source or destination is nonincrementing (as for a peripheral register), then the pointer should point to the transfer address. Table 12-4.
PAGE 1042
Functional Description www.ti.com 12.3.6.3 Auto Mode Auto mode is similar to basic mode, except that when a transfer request is received, the transfer completes, even if the μDMA request is removed. This mode is suitable for software-triggered transfers. Generally, auto mode is not used with a peripheral. The μDMA controller sets the mode for that channel to stop when all the items have been transferred using auto mode. 12.3.6.
PAGE 1043
Functional Description www.ti.com Figure 12-2.
PAGE 1044
Functional Description www.ti.com In memory scatter-gather mode, the primary control structure is used to program the alternate control structure from a table in memory. The table is set up by the processor software and contains a list of control structures, each containing the source and destination end pointers, and the control word for a specific transfer. The mode of each control word must be set to memory scatter-gather mode.
PAGE 1045
Functional Description www.ti.com Figure 12-3.
PAGE 1046
Functional Description www.ti.com Figure 12-4. Memory Scatter-Gather, μDMA Copy Sequence Task list in memory Buffers in memory µDMA control table in memory SRC A SRC SRC B PRI Copied DST Task A Task B SRC C SRC ALT Copied DST Task C DEST A DEST B DEST C Using the primary control structure of the channel, the µDMA controller copies task A configuration to the alternate control structure of the channel.
PAGE 1047
Functional Description www.ti.com 12.3.6.6 Peripheral Scatter-Gather Mode Peripheral scatter-gather mode is similar to memory scatter-gather mode, except that the transfers are controlled by a peripheral making a μDMA request. When the μDMA controller detects a request from the peripheral, the μDMA controller uses the primary control structure to copy one entry from the list to the alternate control structure, and then performs the transfer.
PAGE 1048
Functional Description www.ti.com Figure 12-5. Peripheral Scatter-Gather, Setup, and Configuration 1 2 3 Source buffer in memory Task list in memory Channel control table in memory 4 words (SRC A) SRC A DST ITEMS=4 16 Words (SRC B) SRC Unused DST SRC ITEMS=12 DST B Task A ITEMS=16 Channel primary control structure Task B Unused SRC DST ITEMS=1 Task C SRC DST Unused Channel alternate control structure ITEMS=n 1 Word (SRC C) C Peripheral data register DEST NOTES: 1.
PAGE 1049
Functional Description www.ti.com Figure 12-6. Peripheral Scatter-Gather, μDMA Copy Sequence Task list in memory Buffers in memory µDMA control table in memory SRC A SRC SRC B PRI Copied DST Task A Task B SRC C SRC ALT Copied DST Task C Using the primary control structure of the channel, the µDMA controller copies task A configuration to the alternate control structure of the channel.
PAGE 1050
Functional Description www.ti.com 12.3.7 Transfer Size and Increments The μDMA controller supports transfer data sizes of 8, 16, or 32 bits. The source and destination data size must be the same for any given transfer. The source and destination address can be automatically incremented by bytes, half-words, words, or set to no increment.
PAGE 1051
Functional Description www.ti.com 12.3.10 Interrupts and Errors The μDMA controller generates a completion interrupt on the interrupt vector of the peripheral when a μDMA transfer completes. Therefore, if μDMA is used to transfer data for a peripheral and interrupts are used, then the interrupt handler for that peripheral must be designed to handle the μDMA transfer completion interrupt.
PAGE 1052
Initialization and Configuration www.ti.com 12.4.2 Configuring a Memory-to-Memory Transfer μDMA channels 0, 18, 19, and 20 are dedicated for software-initiated transfers. This specific example uses channel 0. No attributes must be set for a software-based transfer. The attributes are cleared by default, but are explicitly cleared as shown in the following sections. 12.4.2.
PAGE 1053
µDMA Registers www.ti.com 12.5.1 UDMA Registers Table 12-7 lists the memory-mapped registers for the UDMA. All register offset addresses not listed in Table 12-7 should be considered as reserved locations and the register contents should not be modified. Table 12-7. UDMA Registers Offset Acronym Register Name 0h STATUS Status Section 12.5.1.1 Section 4h CFG Configuration Section 12.5.1.2 8h CTRL Channel Control Data Base Pointer Section 12.5.1.
PAGE 1054
µDMA Registers www.ti.com 12.5.1.1 STATUS Register (Offset = 0h) [reset = X] STATUS is shown in Figure 12-7 and described in Table 12-8. Status Figure 12-7. STATUS Register 31 30 29 28 27 26 TEST R-X 25 24 RESERVED R-X 23 22 RESERVED R-X 21 20 19 18 TOTALCHANNELS R-1Fh 17 16 15 14 13 12 11 10 9 8 3 2 RESERVED 1 STATE R-X R-X 0 MASTERENAB LE R-X RESERVED R-X 7 6 5 4 Table 12-8.
PAGE 1055
µDMA Registers www.ti.com 12.5.1.2 CFG Register (Offset = 4h) [reset = X] CFG is shown in Figure 12-8 and described in Table 12-9. Configuration Figure 12-8. CFG Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 2 1 0 MASTERENAB LE W-X RESERVED W-X 23 22 21 20 RESERVED W-X 15 14 13 12 RESERVED W-X 7 6 PRTOCTRL 5 4 3 RESERVED W-X W-X Table 12-9.
PAGE 1056
µDMA Registers www.ti.com 12.5.1.3 CTRL Register (Offset = 8h) [reset = X] CTRL is shown in Figure 12-9 and described in Table 12-10. Channel Control Data Base Pointer Figure 12-9. CTRL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 BASEPTR R/W-X 9 8 7 6 5 4 3 RESERVED R/W-X 2 1 0 Table 12-10.
PAGE 1057
µDMA Registers www.ti.com 12.5.1.4 ALTCTRL Register (Offset = Ch) [reset = 200h] ALTCTRL is shown in Figure 12-10 and described in Table 12-11. Channel Alternate Control Data Base Pointer Figure 12-10. ALTCTRL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 BASEPTR R-200h 9 8 7 6 5 4 3 2 1 0 Table 12-11.
PAGE 1058
µDMA Registers www.ti.com 12.5.1.5 WAITONREQ Register (Offset = 10h) [reset = FFFF1EFFh] WAITONREQ is shown in Figure 12-11 and described in Table 12-12. Channel Wait On Request Status Figure 12-11. WAITONREQ Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 CHNLSTATUS R-FFFF1EFFh 9 8 7 6 5 4 3 2 1 0 Table 12-12.
PAGE 1059
µDMA Registers www.ti.com 12.5.1.6 SOFTREQ Register (Offset = 14h) [reset = X] SOFTREQ is shown in Figure 12-12 and described in Table 12-13. Channel Software Request Figure 12-12. SOFTREQ Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 CHNLS W-X 9 8 7 6 5 4 3 2 1 0 Table 12-13.
PAGE 1060
µDMA Registers www.ti.com 12.5.1.7 SETBURST Register (Offset = 18h) [reset = X] SETBURST is shown in Figure 12-13 and described in Table 12-14. Channel Set UseBurst Figure 12-13. SETBURST Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 CHNLS R/W-X 9 8 7 6 5 4 3 2 1 0 Table 12-14.
PAGE 1061
µDMA Registers www.ti.com 12.5.1.8 CLEARBURST Register (Offset = 1Ch) [reset = X] CLEARBURST is shown in Figure 12-14 and described in Table 12-15. Channel Clear UseBurst Figure 12-14. CLEARBURST Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 CHNLS W-X 9 8 7 6 5 4 3 2 1 0 Table 12-15. CLEARBURST Register Field Descriptions Bit 31-0 Field Type Reset Description CHNLS W X Set the appropriate bit to enable single transfer requests.
PAGE 1062
µDMA Registers www.ti.com 12.5.1.9 SETREQMASK Register (Offset = 20h) [reset = X] SETREQMASK is shown in Figure 12-15 and described in Table 12-16. Channel Set Request Mask Figure 12-15. SETREQMASK Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 CHNLS R/W-X 9 8 7 6 5 4 3 2 1 0 Table 12-16.
PAGE 1063
µDMA Registers www.ti.com 12.5.1.10 CLEARREQMASK Register (Offset = 24h) [reset = X] CLEARREQMASK is shown in Figure 12-16 and described in Table 12-17. Clear Channel Request Mask Figure 12-16. CLEARREQMASK Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 CHNLS W-X 9 8 7 6 5 4 3 2 1 0 Table 12-17. CLEARREQMASK Register Field Descriptions Bit 31-0 Field Type Reset Description CHNLS W X Set the appropriate bit to enable DMA request for the channel.
PAGE 1064
µDMA Registers www.ti.com 12.5.1.11 SETCHANNELEN Register (Offset = 28h) [reset = X] SETCHANNELEN is shown in Figure 12-17 and described in Table 12-18. Set Channel Enable Figure 12-17. SETCHANNELEN Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 CHNLS R/W-X 9 8 7 6 5 4 3 2 1 0 Table 12-18.
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µDMA Registers www.ti.com 12.5.1.12 CLEARCHANNELEN Register (Offset = 2Ch) [reset = X] CLEARCHANNELEN is shown in Figure 12-18 and described in Table 12-19. Clear Channel Enable Figure 12-18. CLEARCHANNELEN Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 CHNLS W-X 9 8 7 6 5 4 3 2 1 0 Table 12-19. CLEARCHANNELEN Register Field Descriptions Bit 31-0 Field Type Reset Description CHNLS W X Set the appropriate bit to disable the corresponding uDMA channel.
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µDMA Registers www.ti.com 12.5.1.13 SETCHNLPRIALT Register (Offset = 30h) [reset = X] SETCHNLPRIALT is shown in Figure 12-19 and described in Table 12-20. Channel Set Primary-Alternate Figure 12-19. SETCHNLPRIALT Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 CHNLS R/W-X 9 8 7 6 5 4 3 2 1 0 Table 12-20.
PAGE 1067
µDMA Registers www.ti.com 12.5.1.14 CLEARCHNLPRIALT Register (Offset = 34h) [reset = X] CLEARCHNLPRIALT is shown in Figure 12-20 and described in Table 12-21. Channel Clear Primary-Alternate Figure 12-20. CLEARCHNLPRIALT Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 CHNLS W-X 9 8 7 6 5 4 3 2 1 0 Table 12-21.
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µDMA Registers www.ti.com 12.5.1.15 SETCHNLPRIORITY Register (Offset = 38h) [reset = X] SETCHNLPRIORITY is shown in Figure 12-21 and described in Table 12-22. Set Channel Priority Figure 12-21. SETCHNLPRIORITY Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 CHNLS R/W-X 9 8 7 6 5 4 3 2 1 0 Table 12-22.
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µDMA Registers www.ti.com 12.5.1.16 CLEARCHNLPRIORITY Register (Offset = 3Ch) [reset = X] CLEARCHNLPRIORITY is shown in Figure 12-22 and described in Table 12-23. Clear Channel Priority Figure 12-22. CLEARCHNLPRIORITY Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 CHNLS W-X 9 8 7 6 5 4 3 2 1 0 Table 12-23.
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µDMA Registers www.ti.com 12.5.1.17 ERROR Register (Offset = 4Ch) [reset = X] ERROR is shown in Figure 12-23 and described in Table 12-24. Error Status and Clear Figure 12-23. ERROR Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 STATUS R/W-X RESERVED W-X 23 22 21 20 RESERVED W-X 15 14 13 12 RESERVED W-X 7 6 5 4 RESERVED W-X Table 12-24.
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µDMA Registers www.ti.com 12.5.1.18 REQDONE Register (Offset = 504h) [reset = X] REQDONE is shown in Figure 12-24 and described in Table 12-25. Channel Request Done Figure 12-24. REQDONE Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 CHNLS R/W-X 9 8 7 6 5 4 3 2 1 0 Table 12-25. REQDONE Register Field Descriptions Bit 31-0 Field Type Reset Description CHNLS R/W X Reflects the uDMA done status for the given channel, channel [Ch]. It's a sticky done bit.
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µDMA Registers www.ti.com 12.5.1.19 DONEMASK Register (Offset = 520h) [reset = X] DONEMASK is shown in Figure 12-25 and described in Table 12-26. Channel Request Done Mask Figure 12-25. DONEMASK Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 CHNLS R/W-X 9 8 7 6 5 4 3 2 1 0 Table 12-26.
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Chapter 13 SWCU117A – February 2015 – Revised March 2015 Timers This chapter describes the general-purpose timers. Topic 13.1 13.2 13.3 13.4 13.5 ........................................................................................................................... General-Purpose Timers .................................................................................. Block Diagram ................................................................................................
PAGE 1074
General-Purpose Timers www.ti.com 13.1 General-Purpose Timers Programmable timers can be used to count or time external events that drive the timer input pins. The CC26xx General-Purpose Timer Module (GPTM) provides two 16-bit timers (referred to as timer A and timer B) that can be configured to operate independently as timers, or concatenated to operate as one 32bit timer. The GPT is one timing resource available on the CC26xx microcontroller.
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Functional Description www.ti.com Figure 13-1.
PAGE 1076
Functional Description www.ti.com Table 13-1.
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Functional Description www.ti.com 13.3.2.1 One-Shot or Periodic Timer Mode The selection of one-shot or periodic mode is determined by the value written to the TnMR field of the GPTM Timer n Mode (GPT_TnMR) register. The timer is configured to count up or down using the TnCDIR bit in the [GPT_TnMR] register. When software sets the TnEN bit in the GPTM Control [GPTIMER_CTL] register, the timer begins counting up from 0x0, or down from its preloaded value.
PAGE 1078
Functional Description www.ti.com Table 13-2. 16-Bit Timer With Prescaler Configurations (1) Prescale (8-bit value) # of Timer Clocks (Tc) (1) Maximum Time Units 00000000 1 2.7 ms 00000001 2 5.4 ms 00000010 3 8.1 ms ------------ – – – 11111101 254 685.8 ms 11111110 255 688.5 ms 11111111 256 691.2 ms Tc is the clock period. 13.3.2.
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Functional Description www.ti.com Figure 13-2 shows how Input Edge-Count mode works. In this case, the timer start value is set to GPT_TnILR =0x000A, and the match value is set to GPT_TnMATCHR =0x0006 so that four edge events are counted. The counter is configured to detect both edges of the input signal. Note that the last two edges are not counted, because the timer automatically clears the TnEN bit after the current count matches the value in the [GPT_TnMATCHR] register. Figure 13-2.
PAGE 1080
Functional Description www.ti.com Mask [GPT_IMR] register, the GPTM also sets the CnEMIS bit in the GPTM Masked Interrupt Status [GPT_MIS] register. In this mode, the [GPT_TnR] register holds the time at which the selected input event occurred, while the [GPT_TnV] and [GPT_TnPV] registers hold the free-running timer value and the freerunning prescaler value. These registers can be read to determine the time that elapsed between the interrupt assertion and the entry into the ISR.
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Functional Description www.ti.com When software writes the TnEN bit in the [GPT_CTL] register, the counter begins counting down until it reaches the 0x0 state. Alternatively, if the TnWOT bit is set in the [GPT_TnMR] register, once the TnEN bit is set, the timer waits for a trigger to begin counting.
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Functional Description www.ti.com Figure 13-5. CCP Output, GPT_TnMATCHR > GPT_TnILR GPTMnMATCHR CounterValue GPTMnILR CCP CCP set if GPTMnMATCHR ≠ GPTMnILR Figure 13-6 shows how the CCP output operates when the PLO and MRSU bits are set and the [GPT_TnMATCHR] register value is the same as the [GPT_TnILR] register value. In this situation, if the PLO bit is 0, the CCP signal goes high when the [GPT_TnILR] register value is loaded, and the match would be essentially ignored. Figure 13-6.
PAGE 1083
Functional Description www.ti.com 13.3.3 Wait-for-Trigger Mode Wait-for-trigger mode allows daisy-chaining of the timer modules such that once configured, a single timer can initiate multiple timing events using the timer triggers. Wait-for-trigger mode is enabled by setting the TnWOT bit in the [GPT_TnMR] register. When the TnWOT bit is set, timer N+1 does not begin counting until the timer in the previous position in the daisy-chain (timer N) reaches its time-out event.
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Functional Description www.ti.com 13.3.5 Accessing Concatenated 16- and 32-Bit GPTM Register Values The GPTM is placed into concatenated mode by writing a 0x0 or a 0x1 to the GPTMCFG bit field in the GPTM Configuration [GPT_CFG] register. In both configurations, certain 16- and 32-bit GPTM registers are concatenated to form pseudo 32-bit registers.
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Initialization and Configuration www.ti.com In one-shot mode, the timer stops counting after the time-out event. To re-enable the timer, repeat the sequence. A timer configured in periodic mode reloads the timer and continues counting after the time-out event. 13.4.2 Input Edge-Count Mode A timer is configured to Input Edge-Count mode by the following sequence: 1. Ensure the timer is disabled (the TAEN bit is cleared) before making any changes. 2.
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Initialization and Configuration www.ti.com 13.4.4 PWM Mode A timer is configured to PWM mode using the following sequence: 1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes. 2. Write the GPTM Configuration [GPT_CFG] register with a value of 0x0000 0004. 3. In the GPTM Timer Mode [GPT_TnMR] register, write the TnCMR field to 0x1 and the TnMR field to 0x2. 4.
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General-Purpose Timer Registers www.ti.com 13.5.1 GPT Registers Table 13-7 lists the memory-mapped registers for the GPT. All register offset addresses not listed in Table 13-7 should be considered as reserved locations and the register contents should not be modified. Table 13-7. GPT Registers Offset Acronym Register Name 0h CFG Configuration Section 13.5.1.1 Section 4h TAMR Timer A Mode Section 13.5.1.2 8h TBMR Timer B Mode Section 13.5.1.3 Ch CTL Control Section 13.5.1.
PAGE 1088
General-Purpose Timer Registers www.ti.com 13.5.1.1 CFG Register (Offset = 0h) [reset = X] CFG is shown in Figure 13-9 and described in Table 13-8. Configuration Figure 13-9. CFG Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 1 0 CFG R/W-X Table 13-8. CFG Register Field Descriptions Field Type Reset Description 31-3 Bit RESERVED R X Software should not rely on the value of a reserved.
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General-Purpose Timer Registers www.ti.com 13.5.1.2 TAMR Register (Offset = 4h) [reset = X] TAMR is shown in Figure 13-10 and described in Table 13-9. Timer A Mode Figure 13-10. TAMR Register 31 30 29 28 27 26 25 24 19 18 17 16 8 TAILD R/W-X RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 TCACT R/W-X 13 12 TACINTD R/W-X 11 TAPLO R/W-X 10 TAMRSU R/W-X 9 TAPWMIE R/W-X 7 TASNAPS R/W-X 6 TAWOT R/W-X 5 TAMIE R/W-X 4 TACDIR R/W-X 3 TAAMS R/W-X 2 TACM R/W-X 1 0 TAMR R/W-X Table 13-9.
PAGE 1090
General-Purpose Timer Registers www.ti.com Table 13-9. TAMR Register Field Descriptions (continued) 1090 Bit Field Type Reset Description 8 TAILD R/W X GPT Timer A PWM Interval Load Write 0h = Update the TAR register with the value in the TAILR register on the next clock cycle. If the pre-scaler is used, update the TAPS register with the value in the TAPR register on the next clock cycle. 1h = Update the TAR register with the value in the TAILR register on the next timeout.
PAGE 1091
General-Purpose Timer Registers www.ti.com 13.5.1.3 TBMR Register (Offset = 8h) [reset = X] TBMR is shown in Figure 13-11 and described in Table 13-10. Timer B Mode Figure 13-11.
PAGE 1092
General-Purpose Timer Registers www.ti.com Table 13-10. TBMR Register Field Descriptions (continued) 1092 Bit Field Type Reset Description 8 TBILD R/W X GPT Timer B PWM Interval Load Write 0h = Update the TBR register with the value in the TBILR register on the next clock cycle. If the pre-scaler is used, update the TBPS register with the value in the TBPR register on the next clock cycle. 1h = Update the TBR register with the value in the TBILR register on the next timeout.
PAGE 1093
General-Purpose Timer Registers www.ti.com 13.5.1.4 CTL Register (Offset = Ch) [reset = X] CTL is shown in Figure 13-12 and described in Table 13-11. Control Figure 13-12.
PAGE 1094
General-Purpose Timer Registers www.ti.com Table 13-11. CTL Register Field Descriptions (continued) Bit Field Type Reset Description RTCEN R/W X GPT RTC Enable 0h = RTC counting is disabled. 1h = RTC counting is enabled. 3-2 TAEVENT R/W X GPT Timer A Event Mode 0h = Positive edge 1h = Negative edge 3h = Both edges 1 TASTALL R/W X GPT Timer A Stall Enable 0h = Timer A continues counting while the processor is halted by the debugger.
PAGE 1095
General-Purpose Timer Registers www.ti.com 13.5.1.5 SYNC Register (Offset = 10h) [reset = X] SYNC is shown in Figure 13-13 and described in Table 13-12. Synch Register Figure 13-13. SYNC Register 31 30 29 28 27 26 25 15 14 13 12 11 RESERVED R-X 10 9 24 23 RESERVED R-X 8 22 21 20 19 18 17 16 6 5 4 3 2 1 0 7 SYNC3 W-X SYNC2 W-X SYNC1 W-X SYNC0 W-X Table 13-12.
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General-Purpose Timer Registers www.ti.com 13.5.1.6 IMR Register (Offset = 18h) [reset = X] IMR is shown in Figure 13-14 and described in Table 13-13. Interrupt Mask This register is used to enable the interrupts. Associated registers: RIS, MIS, ICLR Figure 13-14.
PAGE 1097
General-Purpose Timer Registers www.ti.com Table 13-13. IMR Register Field Descriptions (continued) Bit Field Type Reset Description 5 DMAAIM R/W X Enabling this bit will make the RIS.DMAARIS interrupt propagate to MIS.DMAAMIS 0h = Disable Interrupt 1h = Enable Interrupt 4 TAMIM R/W X Enabling this bit will make the RIS.TAMRIS interrupt propagate to MIS.TAMMIS 0h = Disable Interrupt 1h = Enable Interrupt 3 RTCIM R/W X Enabling this bit will make the RIS.
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General-Purpose Timer Registers www.ti.com 13.5.1.7 RIS Register (Offset = 1Ch) [reset = X] RIS is shown in Figure 13-15 and described in Table 13-14. Raw Interrupt Status Associated registers: IMR, MIS, ICLR Figure 13-15.
PAGE 1099
General-Purpose Timer Registers www.ti.com Table 13-14. RIS Register Field Descriptions (continued) Bit Field Type Reset Description 3 RTCRIS R X GPT RTC Raw Interrupt 0: The RTC event has not occured 1: The RTC event has occured 2 CAERIS R X GPT Timer A Capture Mode Event Raw Interrupt 0: The event has not occured. 1: The event has occured.
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General-Purpose Timer Registers www.ti.com 13.5.1.8 MIS Register (Offset = 20h) [reset = X] MIS is shown in Figure 13-16 and described in Table 13-15. Masked Interrupt Status Values are result of bitwise AND operation between RIS and IMR Assosciated clear register: ICLR Figure 13-16.
PAGE 1101
General-Purpose Timer Registers www.ti.com Table 13-15. MIS Register Field Descriptions (continued) Bit 0 Field Type Reset Description TATOMIS R X 0: No interrupt or interrupt not enabled 1: RIS.TATORIS = 1 && IMR.
PAGE 1102
General-Purpose Timer Registers www.ti.com 13.5.1.9 ICLR Register (Offset = 24h) [reset = X] ICLR is shown in Figure 13-17 and described in Table 13-16. Interrupt Clear This register is used to clear status bits in the RIS and MIS registers Figure 13-17.
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General-Purpose Timer Registers www.ti.com 13.5.1.10 TAILR Register (Offset = 28h) [reset = FFFFFFFFh] TAILR is shown in Figure 13-18 and described in Table 13-17. Timer A Interval Load Register Figure 13-18. TAILR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 TAILR R/W-FFFFFFFFh 9 8 7 6 5 4 3 2 1 0 Table 13-17.
PAGE 1104
General-Purpose Timer Registers www.ti.com 13.5.1.11 TBILR Register (Offset = 2Ch) [reset = FFFFh] TBILR is shown in Figure 13-19 and described in Table 13-18. Timer B Interval Load Register Figure 13-19. TBILR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 TBILR R/W-FFFFh 9 8 7 6 5 4 3 2 1 0 Table 13-18.
PAGE 1105
General-Purpose Timer Registers www.ti.com 13.5.1.12 TAMATCHR Register (Offset = 30h) [reset = FFFFFFFFh] TAMATCHR is shown in Figure 13-20 and described in Table 13-19. Timer A Match Register This register is loaded with a match value. Interrupts can be generated when the timer value is equal to the value in this register in one-shot or periodic mode. In Edge-Count mode, this register along with TAILR, determines how many edge events are counted.
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General-Purpose Timer Registers www.ti.com 13.5.1.13 TBMATCHR Register (Offset = 34h) [reset = FFFFh] TBMATCHR is shown in Figure 13-21 and described in Table 13-20. Timer B Match Register When a GPT is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of TAMATCHR. Reads from this register return the current match value of Timer B and writes are ignored. In a 16-bit mode, bits 15:0 are used for the match value.
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General-Purpose Timer Registers www.ti.com 13.5.1.14 TAPR Register (Offset = 38h) [reset = X] TAPR is shown in Figure 13-22 and described in Table 13-21. Timer A Pre-scale This register allows software to extend the range of the timers when they are used individually. When in one-shot or periodic down count modes, this register acts as a true prescaler for the timer counter. When acting as a true prescaler, the prescaler counts down to 0 before the value in TAR and TAV registers are incremented.
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General-Purpose Timer Registers www.ti.com 13.5.1.15 TBPR Register (Offset = 3Ch) [reset = X] TBPR is shown in Figure 13-23 and described in Table 13-22. Timer B Pre-scale This register allows software to extend the range of the timers when they are used individually. When in one-shot or periodic down count modes, this register acts as a true prescaler for the timer counter. When acting as a true prescaler, the prescaler counts down to 0 before the value in TBR and TBV registers are incremented.
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General-Purpose Timer Registers www.ti.com 13.5.1.16 TAPMR Register (Offset = 40h) [reset = X] TAPMR is shown in Figure 13-24 and described in Table 13-23. Timer A Pre-scale Match This register allows software to extend the range of the TAMATCHR when used individually. Figure 13-24. TAPMR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 TAPSMR R/W-X 1 0 Table 13-23.
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General-Purpose Timer Registers www.ti.com 13.5.1.17 TBPMR Register (Offset = 44h) [reset = X] TBPMR is shown in Figure 13-25 and described in Table 13-24. Timer B Pre-scale Match This register allows software to extend the range of the TBMATCHR when used individually. Figure 13-25. TBPMR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 TBPSMR R/W-X 1 0 Table 13-24.
PAGE 1111
General-Purpose Timer Registers www.ti.com 13.5.1.18 TAR Register (Offset = 48h) [reset = FFFFFFFFh] TAR is shown in Figure 13-26 and described in Table 13-25. Timer A Register Figure 13-26. TAR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 TAR R-FFFFFFFFh 9 8 7 6 5 4 3 2 1 0 Table 13-25.
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General-Purpose Timer Registers www.ti.com 13.5.1.19 TBR Register (Offset = 4Ch) [reset = FFFFh] TBR is shown in Figure 13-27 and described in Table 13-26. Timer B Register Figure 13-27. TBR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 TBR R-FFFFh 9 8 7 6 5 4 3 2 1 0 Table 13-26.
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General-Purpose Timer Registers www.ti.com 13.5.1.20 TAV Register (Offset = 50h) [reset = FFFFFFFFh] TAV is shown in Figure 13-28 and described in Table 13-27. Timer A Value This register shows the current value of the free running 16-bit Timer A. In the 32-bit mode Figure 13-28. TAV Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 TAV R/W-FFFFFFFFh 9 8 7 6 5 4 3 2 1 0 Table 13-27.
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General-Purpose Timer Registers www.ti.com 13.5.1.21 TBV Register (Offset = 54h) [reset = FFFFh] TBV is shown in Figure 13-29 and described in Table 13-28. Timer B Value This register shows the current value of the free running 16-bit Timer B. Note: When the alternate timer clock (TIMCLK) is enabled; a read of a timer value will return the current count 1. Figure 13-29. TBV Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 TBV R/W-FFFFh 9 8 7 6 5 4 3 2 1 0 Table 13-28.
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General-Purpose Timer Registers www.ti.com 13.5.1.22 RTCPD Register (Offset = 58h) [reset = X] RTCPD is shown in Figure 13-30 and described in Table 13-29. RTC Pre-divide Value This register shows the current value of the RTC pre-divider in RTC mode. Note: When the alternate timer clock (TIMCLK) is enabled; a read of a timer value will return the current count 1. Figure 13-30.
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General-Purpose Timer Registers www.ti.com 13.5.1.23 TAPS Register (Offset = 5Ch) [reset = X] TAPS is shown in Figure 13-31 and described in Table 13-30. Timer A Pre-scale Snap-shot This register shows the current value of the Timer A pre-scaler in the 16-bit mode. Note: When the alternate timer clock (TIMCLK) is enabled; a read of a timer value will return the current count -1. Figure 13-31.
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General-Purpose Timer Registers www.ti.com 13.5.1.24 TBPS Register (Offset = 60h) [reset = X] TBPS is shown in Figure 13-32 and described in Table 13-31. Timer A Pre-scale Snap-shot This register shows the current value of the Timer B pre-scaler in the 16-bit mode. Note: When the alternate timer clock (TIMCLK) is enabled; a read of a timer value will return the current count -1. Figure 13-32.
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General-Purpose Timer Registers www.ti.com 13.5.1.25 TAPV Register (Offset = 64h) [reset = X] TAPV is shown in Figure 13-33 and described in Table 13-32. Timer A Pre-scale Value This register shows the current value of the Timer A free running pre-scaler in the 16-bit mode. Note: When the alternate timer clock (TIMCLK) is enabled; a read of a timer value will return the current count 1. Figure 13-33.
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General-Purpose Timer Registers www.ti.com 13.5.1.26 TBPV Register (Offset = 68h) [reset = X] TBPV is shown in Figure 13-34 and described in Table 13-33. Timer B Pre-scale Value This register shows the current value of the Timer B free running pre-scaler in the 16-bit mode. Note: When the alternate timer clock (TIMCLK) is enabled; a read of a timer value will return the current count-1. Figure 13-34.
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General-Purpose Timer Registers www.ti.com 13.5.1.27 DMAEV Register (Offset = 6Ch) [reset = X] DMAEV is shown in Figure 13-35 and described in Table 13-34. DMA Event This register allows software to enable/disable GPT DMA trigger events. Figure 13-35.
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General-Purpose Timer Registers www.ti.com 13.5.1.28 ADCEV Register (Offset = 70h) [reset = X] ADCEV is shown in Figure 13-36 and described in Table 13-35. ADC Event This register allows software to enable/disable GPT ADC trigger events. Figure 13-36.
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General-Purpose Timer Registers www.ti.com 13.5.1.29 VERSION Register (Offset = FB0h) [reset = 400h] VERSION is shown in Figure 13-37 and described in Table 13-36. Peripheral Version This register provides information regarding the GPT version Figure 13-37. VERSION Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 VERSION R-400h 9 8 7 6 5 4 3 2 1 0 Table 13-36.
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General-Purpose Timer Registers www.ti.com 13.5.1.30 ANDCCP Register (Offset = FB4h) [reset = X] ANDCCP is shown in Figure 13-38 and described in Table 13-37. Combined CCP Output This register is used to logically AND CCP output pairs for each timer Figure 13-38. ANDCCP Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CCP_AND_EN R/W-X RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 4 RESERVED R-X Table 13-37.
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Chapter 14 SWCU117A – February 2015 – Revised March 2015 Real-Time Clock This chapter describes the functionality and design of the always-on, real-time clock (AON RTC) for the CC26xx platform. Topic 14.1 14.2 14.3 14.4 1124 ........................................................................................................................... Introduction ................................................................................................... Functional Specifications.....................
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Introduction www.ti.com 14.1 Introduction This section describes the functionality and design of the always-on, real-time clock (AON RTC) for the CC26xx platform. The AON RTC implements a second and subsecond counter with support for softwarecompensation of ppm-offsets, with three match and one compare register. A special mechanism is in place to support power down of the MCU domain while the AON RTC continues to operate.
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Functional Specifications www.ti.com Figure 14-1. AON RTC Channels AON RTC Module Registers DELAY counter CLEAR CH0_EVENT CH0 32 kHz I/O border rtc_cnt[53:22] CH1_EVENT CAPTURE Programable event CH1 I/O border Event fabric DELAY counter CLEAR 32 kHz rtc_cnt[53:22] DELAY counter CLEAR CH2_CLEAR CH2_EVENT AUX rtc_cnt[53:22] 32 kHz Main counter rtc_cnt[69:0] CH2 32 kHz subsecinc rtc_upd (16 kHz) DIV 2 14.2.
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RTC Registers www.ti.com The [AON_RTC:EVFLAGS] register has a fast-clear feature. When written to 1, the MCU intermediately clears the EVFLAGS bit field. This process enables the MCU to clear the source quickly if the status is used as an interrupt or event. Due to synchronization, the actual flag in the RTC is not cleared until 1 or 2 clock cycles later. For this reason, a new event will be masked for up to two 32-kHz LF periods. 14.3.
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Real-Time Clock Registers www.ti.com 14.4.1 AON_RTC Registers Table 14-1 lists the memory-mapped registers for the AON_RTC. All register offset addresses not listed in Table 14-1 should be considered as reserved locations and the register contents should not be modified. Table 14-1. AON_RTC Registers Offset 1128 Acronym Register Name 0h CTL Control Section 14.4.1.1 Section 4h EVFLAGS Event Flags - RTC Status Section 14.4.1.2 8h SEC Second Counter Value, Integer Part Section 14.4.1.
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Real-Time Clock Registers www.ti.com 14.4.1.1 CTL Register (Offset = 0h) [reset = X] CTL is shown in Figure 14-2 and described in Table 14-2. Control This register contains various bitfields for configuration of RTC Figure 14-2.
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Real-Time Clock Registers www.ti.com Table 14-2. CTL Register Field Descriptions (continued) Bit 1130 Field Type Reset Description 2 RTC_4KHZ_EN R/W X RTC_4KHZ is a 4 KHz reference output, tapped from SUBSEC:VALUE bit 19 which is used by AUX timer. 0: RTC_4KHZ signal is forced to 0 1: RTC_4KHZ is enabled ( provied that RTC is enabled EN) 1 RTC_UPD_EN R/W X RTC_UPD is a 16 KHz signal used to sync up the radio timer.
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Real-Time Clock Registers www.ti.com 14.4.1.2 EVFLAGS Register (Offset = 4h) [reset = X] EVFLAGS is shown in Figure 14-3 and described in Table 14-3. Event Flags - RTC Status This register contains event flags from the 3 RTC channels. Each flag will be cleared when writing a '1' to the corresponding bitfield. Figure 14-3.
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Real-Time Clock Registers www.ti.com 14.4.1.3 SEC Register (Offset = 8h) [reset = X] SEC is shown in Figure 14-4 and described in Table 14-4. Second Counter Value, Integer Part Figure 14-4. SEC Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 VALUE R/W-X 9 8 7 6 5 4 3 2 1 0 Table 14-4. SEC Register Field Descriptions Bit 31-0 1132 Field Type Reset Description VALUE R/W X Unsigned integer representing Real Time Clock in seconds.
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Real-Time Clock Registers www.ti.com 14.4.1.4 SUBSEC Register (Offset = Ch) [reset = X] SUBSEC is shown in Figure 14-5 and described in Table 14-5. Second Counter Value, Fractional Part Figure 14-5. SUBSEC Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 VALUE R/W-X 9 8 7 6 5 4 3 2 1 0 Table 14-5.
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Real-Time Clock Registers www.ti.com 14.4.1.5 SUBSECINC Register (Offset = 10h) [reset = X] SUBSECINC is shown in Figure 14-6 and described in Table 14-6. Subseconds Increment Value added to SUBSEC.VALUE on every **SCLK_LF **clock cycle. Figure 14-6. SUBSECINC Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED VALUEINC R-X R-800000h 9 8 7 6 5 4 3 2 1 0 Table 14-6.
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Real-Time Clock Registers www.ti.com 14.4.1.6 CHCTL Register (Offset = 14h) [reset = X] CHCTL is shown in Figure 14-7 and described in Table 14-7. Channel Configuration Figure 14-7. CHCTL Register 31 30 29 28 27 26 25 24 20 19 18 CH2_CONT_E N R/W-X 17 RESERVED 16 CH2_EN R-X R/W-X 12 11 10 9 CH1_CAPT_E N R/W-X 8 CH1_EN 4 RESERVED R-X 3 2 1 0 CH0_EN R/W-X RESERVED R-X 23 22 15 14 21 RESERVED R-X 13 RESERVED R-X 7 6 5 R/W-X Table 14-7.
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Real-Time Clock Registers www.ti.com 14.4.1.7 CH0CMP Register (Offset = 18h) [reset = X] CH0CMP is shown in Figure 14-8 and described in Table 14-8. Channel 0 Compare Value Figure 14-8. CH0CMP Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 VALUE R/W-X 9 8 7 6 5 4 3 2 1 0 Table 14-8. CH0CMP Register Field Descriptions Bit 31-0 1136 Field Type Reset Description VALUE R/W X RTC Channel 0 compare value.
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Real-Time Clock Registers www.ti.com 14.4.1.8 CH1CMP Register (Offset = 1Ch) [reset = X] CH1CMP is shown in Figure 14-9 and described in Table 14-9. Channel 1 Compare Value Figure 14-9. CH1CMP Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 VALUE R/W-X 9 8 7 6 5 4 3 2 1 0 Table 14-9. CH1CMP Register Field Descriptions Bit 31-0 Field Type Reset Description VALUE R/W X RTC Channel 1 compare value.
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Real-Time Clock Registers www.ti.com 14.4.1.9 CH2CMP Register (Offset = 20h) [reset = X] CH2CMP is shown in Figure 14-10 and described in Table 14-10. Channel 2 Compare Value Figure 14-10. CH2CMP Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 VALUE R/W-X 9 8 7 6 5 4 3 2 1 0 Table 14-10. CH2CMP Register Field Descriptions Bit 31-0 1138 Field Type Reset Description VALUE R/W X RTC Channel 2 compare value.
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Real-Time Clock Registers www.ti.com 14.4.1.10 CH2CMPINC Register (Offset = 24h) [reset = X] CH2CMPINC is shown in Figure 14-11 and described in Table 14-11. Channel 2 Compare Value Auto-increment This register is primarily used to generate periodical wake-up for the AUX_SCE module, through the [AUX_EVCTL.EVSTAT0.AON_RTC] event. Figure 14-11. CH2CMPINC Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 VALUE R/W-X 9 8 7 6 5 4 3 2 1 0 Table 14-11.
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Real-Time Clock Registers www.ti.com 14.4.1.11 CH1CAPT Register (Offset = 28h) [reset = X] CH1CAPT is shown in Figure 14-12 and described in Table 14-12. Channel 1 Capture Value If CHCTL.CH1_EN = 1and CHCTL.CH1_CAPT_EN = 1, capture occurs on each rising edge of the event selected in AON_EVENT:RTCSEL. Figure 14-12. CH1CAPT Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 SEC R-X 9 8 7 6 SUBSEC R-X 5 4 3 2 1 0 Table 14-12.
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Real-Time Clock Registers www.ti.com 14.4.1.12 SYNC Register (Offset = 2Ch) [reset = X] SYNC is shown in Figure 14-13 and described in Table 14-13. AON Synchronization This register is used for synchronizing between MCU and entire AON domain. Figure 14-13. SYNC Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 WBUSY R/W-X RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 4 RESERVED R-X Table 14-13.
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Chapter 15 SWCU117A – February 2015 – Revised March 2015 Watchdog Timer The watchdog timer (WDT) is used to regain control when the system has failed due to a software error or to the failure of an external device to respond in the expected way. The WDT can generate a nonmaskable interrupt (NMI), a regular interrupt, or a reset when a time-out value is reached.
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WDT Introduction www.ti.com 15.
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WDT Initialization and Configuration www.ti.com Figure 15-1. WDT Block Diagram [WDT:LOAD] Control /Interrupt generation 32±Bit down counter [WDT:CTL] Interrupt/NMI [WDT:ICR] [WDT:RIS] 0x 00000000 [WDT:MIS] INFRASTRUCTURE clock [WDT:LOCK] [WDT:VALUE] Comparator 15.3 WDT Initialization and Configuration To use the WDT, its peripheral clock must be enabled. The WDT is running off the infrastructure clock sourced by the MCU PRCM module. The WDT is then configured using the following sequence: 1.
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Watchdog Timer Registers www.ti.com 15.4.1 WDT Registers Table 15-1 lists the memory-mapped registers for the WDT. All register offset addresses not listed in Table 15-1 should be considered as reserved locations and the register contents should not be modified. Table 15-1. WDT Registers Offset Acronym Register Name 0h LOAD Configuration Section 15.4.1.1 Section 4h VALUE Current Count Value Section 15.4.1.2 8h CTL Control Section 15.4.1.3 Ch ICR Interrupt Clear Section 15.4.1.
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Watchdog Timer Registers www.ti.com 15.4.1.1 LOAD Register (Offset = 0h) [reset = FFFFFFFFh] LOAD is shown in Figure 15-2 and described in Table 15-2. Configuration Figure 15-2. LOAD Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 WDTLOAD R/W-FFFFFFFFh 9 8 7 6 5 4 3 2 1 0 Table 15-2. LOAD Register Field Descriptions Bit 31-0 1146 Field Type Reset WDTLOAD R/W FFFFFFFFh This register is the 32-bit interval value used by the 32-bit counter.
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Watchdog Timer Registers www.ti.com 15.4.1.2 VALUE Register (Offset = 4h) [reset = FFFFFFFFh] VALUE is shown in Figure 15-3 and described in Table 15-3. Current Count Value Figure 15-3. VALUE Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 WDTVALUE R-FFFFFFFFh 9 8 7 6 5 4 3 2 1 0 Table 15-3. VALUE Register Field Descriptions Bit 31-0 Field Type Reset WDTVALUE R FFFFFFFFh This register contains the current count value of the timer.
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Watchdog Timer Registers www.ti.com 15.4.1.3 CTL Register (Offset = 8h) [reset = X] CTL is shown in Figure 15-4 and described in Table 15-4. Control Figure 15-4. CTL Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 INTTYPE R/W-X 1 RESEN R/W-X 0 INTEN R/W-X RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 RESERVED R-X 4 Table 15-4.
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Watchdog Timer Registers www.ti.com 15.4.1.4 ICR Register (Offset = Ch) [reset = X] ICR is shown in Figure 15-5 and described in Table 15-5. Interrupt Clear Figure 15-5. ICR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 WDTICR W-X 9 8 7 6 5 4 3 2 1 0 Table 15-5. ICR Register Field Descriptions Bit 31-0 Field Type Reset Description WDTICR W X This register is the interrupt clear register.
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Watchdog Timer Registers www.ti.com 15.4.1.5 RIS Register (Offset = 10h) [reset = X] RIS is shown in Figure 15-6 and described in Table 15-6. Raw Interrupt Status Figure 15-6. RIS Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 WDTRIS R-X RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 4 RESERVED R-X Table 15-6.
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Watchdog Timer Registers www.ti.com 15.4.1.6 MIS Register (Offset = 14h) [reset = X] MIS is shown in Figure 15-7 and described in Table 15-7. Masked Interrupt Status Figure 15-7. MIS Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 WDTMIS R-X RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 4 RESERVED R-X Table 15-7.
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Watchdog Timer Registers www.ti.com 15.4.1.7 TEST Register (Offset = 418h) [reset = X] TEST is shown in Figure 15-8 and described in Table 15-8. Test Mode Figure 15-8. TEST Register 31 30 29 28 27 26 25 24 19 18 17 16 RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 11 10 9 8 STALL R/W-X 7 6 5 4 RESERVED R-X 3 2 1 0 TEST_EN R/W-X Table 15-8.
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Watchdog Timer Registers www.ti.com 15.4.1.8 INT_CAUS Register (Offset = 41Ch) [reset = X] INT_CAUS is shown in Figure 15-9 and described in Table 15-9. Interrupt Cause Test Mode ITERNAL_NOTE: This register shows the status of Reset and Interrupt when test mode is enabled, TEST.TEST_EN Figure 15-9.
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Watchdog Timer Registers www.ti.com 15.4.1.9 LOCK Register (Offset = C00h) [reset = X] LOCK is shown in Figure 15-10 and described in Table 15-10. Lock Figure 15-10. LOCK Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 WDTLOCK R/W-X 9 8 7 6 5 4 3 2 1 0 Table 15-10. LOCK Register Field Descriptions Bit 31-0 1154 Field Type Reset Description WDTLOCK R/W X WDT Lock: A write of the value 0x1ACC.E551 unlocks the watchdog registers for write access.
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Chapter 16 SWCU117A – February 2015 – Revised March 2015 Random Number Generator The true random number generator (TRNG) module provides a true, nondeterministic noise source for the purpose of generating keys, initialization vectors (IVs), and other random number requirements. The TRNG is built on 24 ring oscillators that create unpredictable output to feed a complex nonlinear combinatorial circuit. That post-processing of the output data is required to obtain cryptographically secure random data.
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Overview www.ti.com 16.1 Overview The TRNG has the following features: • • • • • • • • The TRNG is based on 24 ring oscillators (shot noise) to create entropy. To generate this entropy the system needs a minimum of 28 system clock cycles (for reference) to produce the first random output. Then ithe TRNG takes a minimum of 26 system clock cycles to produce each subsequent 64 bits random number.
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TRNG Software Reset www.ti.com • nondeterministic. Each FRO has an error detection circuit that checks for repeating patterns coming out of the FRO. If a repeating pattern is detected, the FRO is suspect of having locked onto the sampling clock, which drastically reduces the amount of entropy generated by that FRO (this is signaled as a FRO error event).
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TRNG Operation Description www.ti.com The [TRNG:ALARMCNT] register, together with the [TRNG:ALARMMASK] and [TRNG:ALARMSTOP] registers, can be used by the host to determine if the FRO/sample cycle locking is a problem. Lock detection in functional mode is performed using the sampled outputs of the individual FROs. A FRO alarm event is declared when a repeating pattern (of up to four samples length) is detected continuously for the number of samples defined by the [TRNG:ALARMCNT:ALARM_THR].
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TRNG Operation Description www.ti.com If the clock is stopped, the TRNG can not be accessed and a bus fault will be generated (within the Interconnect). If an application that no longer needs the TRNG must go into deep sleep mode without waiting, the application can write 0 in the [TRNG:CTL:TRNG_EN] bit, and the input system clock can be switched off. If [TRNF:CTL:TRNG_EN] is set to 0 and the input clock is switched off.
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TRNG Low-level Programing Guide www.ti.com 16.6 TRNG Low-level Programing Guide This section covers the low-level hardware programming sequences for configuration and usage of the module. 16.6.1 Initialization 16.6.1.1 Interfacing Modules This section identifies the requirements of initializing the interfacing modules when the TRNG is to be used for the first time after a device reset. Table 16-2 lists the Initialization of Interfacing Modules. Table 16-2.
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TRNG Low-level Programing Guide www.ti.com 16.6.1.3 TRNG Operating Modes This section presents the flow for different operating modes of the TRNG module. 16.6.1.3.1 Polling Mode In polling mode, both monitored and unmonitored modes are covered. Figure 16-2 shows the TRNG polling mode. Figure 16-2.
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Random Number Generator www.ti.com 16.6.1.3.2 Interrupt Mode The Interrupt Mode section covers the event servicing of the module. Only the unmonitored mode is covered. Table 16-4 lists the TRNG interrupt mode steps, while Figure 16-3 shows the interrupt service routine flow. Table 16-4. TRNG Interrupt Mode Step Register / Bit-field Value Enable interrupt generation when data is ready (available) in the output registers.
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Random Number Generator www.ti.com 16.7.1 TRNG Registers Table 16-5 lists the memory-mapped registers for the TRNG. All register offset addresses not listed in Table 16-5 should be considered as reserved locations and the register contents should not be modified. Table 16-5. TRNG Registers Offset Acronym Register Name 0h OUT0 Random Number Lower Word Readout Value Section 16.7.1.1 Section 4h OUT1 Random Number Upper Word Readout Value Section 16.7.1.
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Random Number Generator www.ti.com 16.7.1.1 OUT0 Register (Offset = 0h) [reset = X] OUT0 is shown in Figure 16-4 and described in Table 16-6. Random Number Lower Word Readout Value Figure 16-4. OUT0 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 VALUE_31_0 R-X 9 8 7 6 5 4 3 2 1 0 Table 16-6. OUT0 Register Field Descriptions Bit 31-0 1164 Field Type Reset Description VALUE_31_0 R X LSW of 64- bit random value. New value ready when IRQFLAGSTAT.RDY = 1.
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Random Number Generator www.ti.com 16.7.1.2 OUT1 Register (Offset = 4h) [reset = X] OUT1 is shown in Figure 16-5 and described in Table 16-7. Random Number Upper Word Readout Value Figure 16-5. OUT1 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 VALUE_63_32 R-X 9 8 7 6 5 4 3 2 1 0 Table 16-7. OUT1 Register Field Descriptions Bit 31-0 Field Type Reset Description VALUE_63_32 R X MSW of 64-bit random value. New value ready when IRQFLAGSTAT.RDY = 1.
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Random Number Generator www.ti.com 16.7.1.3 IRQFLAGSTAT Register (Offset = 8h) [reset = X] IRQFLAGSTAT is shown in Figure 16-6 and described in Table 16-8. Interrupt Status Figure 16-6. IRQFLAGSTAT Register 31 NEED_CLOCK R-X 30 29 28 23 22 21 20 27 RESERVED R-X 26 25 24 19 18 17 16 11 10 9 8 3 2 1 SHUTDOWN_ OVF R-X 0 RDY RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 4 RESERVED R-X R-X Table 16-8.
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Random Number Generator www.ti.com 16.7.1.4 IRQFLAGMASK Register (Offset = Ch) [reset = X] IRQFLAGMASK is shown in Figure 16-7 and described in Table 16-9. Interrupt Mask Figure 16-7. IRQFLAGMASK Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 SHUTDOWN_ OVF R/W-X 0 RDY RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 4 RESERVED R-X R/W-X Table 16-9.
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Random Number Generator www.ti.com 16.7.1.5 IRQFLAGCLR Register (Offset = 10h) [reset = X] IRQFLAGCLR is shown in Figure 16-8 and described in Table 16-10. Interrupt Flag Clear Figure 16-8. IRQFLAGCLR Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 SHUTDOWN_ OVF W-X 0 RDY RESERVED W-X 23 22 21 20 RESERVED W-X 15 14 13 12 RESERVED W-X 7 6 5 4 RESERVED W-X W-X Table 16-10.
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Random Number Generator www.ti.com 16.7.1.6 CTL Register (Offset = 14h) [reset = X] CTL is shown in Figure 16-9 and described in Table 16-11. Control Figure 16-9. CTL Register 31 30 29 28 27 STARTUP_CYCLES R/W-X 26 25 24 23 22 21 20 19 STARTUP_CYCLES R/W-X 18 17 16 15 14 13 RESERVED R-X 12 10 TRNG_EN R/W-X 9 5 RESERVED R-X 4 2 NO_LFSR_FB R/W-X 1 TEST_MODE R/W-X 7 6 11 3 8 RESERVED R-X 0 RESERVED R/W-X Table 16-11.
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Random Number Generator www.ti.com 16.7.1.7 CFG0 Register (Offset = 18h) [reset = X] CFG0 is shown in Figure 16-10 and described in Table 16-12. Configuration 0 Figure 16-10. CFG0 Register 31 30 29 28 27 26 25 15 14 13 RESERVED R-X 12 11 10 9 SMPL_DIV R/W-X 24 23 22 MAX_REFILL_CYCLES R/W-X 8 7 6 21 5 20 19 18 17 16 4 3 2 MIN_REFILL_CYCLES R/W-X 1 0 Table 16-12.
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Random Number Generator www.ti.com 16.7.1.8 ALARMCNT Register (Offset = 1Ch) [reset = X] ALARMCNT is shown in Figure 16-11 and described in Table 16-13. Alarm Control Figure 16-11. ALARMCNT Register 31 30 29 28 27 26 SHUTDOWN_CNT R/W-X 25 24 23 22 RESERVED R-X 21 20 19 18 SHUTDOWN_THR R/W-X 17 16 15 14 13 12 11 10 9 8 3 2 1 0 RESERVED R-X RESERVED R-X 7 6 5 4 ALARM_THR R/W-FFh Table 16-13.
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Random Number Generator www.ti.com 16.7.1.9 FROEN Register (Offset = 20h) [reset = X] FROEN is shown in Figure 16-12 and described in Table 16-14. FRO Enable Figure 16-12. FROEN Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED FRO_MASK R-X R/W-FFFFFFh 9 8 7 6 5 4 3 2 1 0 Table 16-14. FROEN Register Field Descriptions Field Type Reset Description 31-24 Bit RESERVED R X Software should not rely on the value of a reserved.
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Random Number Generator www.ti.com 16.7.1.10 FRODETUNE Register (Offset = 24h) [reset = X] FRODETUNE is shown in Figure 16-13 and described in Table 16-15. FRO De-tune Bit Figure 16-13. FRODETUNE Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED FRO_MASK R-X R/W-X 9 8 7 6 5 4 3 2 1 0 Table 16-15. FRODETUNE Register Field Descriptions Field Type Reset Description 31-24 Bit RESERVED R X Software should not rely on the value of a reserved.
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Random Number Generator www.ti.com 16.7.1.11 ALARMMASK Register (Offset = 28h) [reset = X] ALARMMASK is shown in Figure 16-14 and described in Table 16-16. Alarm Event Figure 16-14. ALARMMASK Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED FRO_MASK R/W-X R/W-X 9 8 7 6 5 4 3 2 1 0 Table 16-16. ALARMMASK Register Field Descriptions Field Type Reset Description 31-24 Bit RESERVED R/W X Software should not rely on the value of a reserved.
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Random Number Generator www.ti.com 16.7.1.12 ALARMSTOP Register (Offset = 2Ch) [reset = X] ALARMSTOP is shown in Figure 16-15 and described in Table 16-17. Alarm Shutdown Figure 16-15. ALARMSTOP Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED FRO_FLAGS R-X R/W-X 9 8 7 6 5 4 3 2 1 0 Table 16-17. ALARMSTOP Register Field Descriptions Field Type Reset Description 31-24 Bit RESERVED R X Software should not rely on the value of a reserved.
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Random Number Generator www.ti.com 16.7.1.13 LFSR0 Register (Offset = 30h) [reset = X] LFSR0 is shown in Figure 16-16 and described in Table 16-18. LFSR Readout Value Figure 16-16. LFSR0 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 LFSR_31_0 R/W-X 9 8 7 6 5 4 3 2 1 0 Table 16-18. LFSR0 Register Field Descriptions Bit 31-0 1176 Field Type Reset Description LFSR_31_0 R/W X Bits [31:0] of the main entropy accumulation LFSR.
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Random Number Generator www.ti.com 16.7.1.14 LFSR1 Register (Offset = 34h) [reset = X] LFSR1 is shown in Figure 16-17 and described in Table 16-19. LFSR Readout Value Figure 16-17. LFSR1 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 LFSR_63_32 R/W-X 9 8 7 6 5 4 3 2 1 0 Table 16-19. LFSR1 Register Field Descriptions Bit 31-0 Field Type Reset Description LFSR_63_32 R/W X Bits [63:32] of the main entropy accumulation LFSR.
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Random Number Generator www.ti.com 16.7.1.15 LFSR2 Register (Offset = 38h) [reset = X] LFSR2 is shown in Figure 16-18 and described in Table 16-20. LFSR Readout Value Figure 16-18. LFSR2 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 RESERVED LFSR_80_64 R/W-X R/W-X 5 4 3 2 1 0 Table 16-20. LFSR2 Register Field Descriptions Field Type Reset Description 31-17 Bit RESERVED R/W X Software should not rely on the value of a reserved.
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Random Number Generator www.ti.com 16.7.1.16 HWOPT Register (Offset = 78h) [reset = X] HWOPT is shown in Figure 16-19 and described in Table 16-21. TRNG Engine Options Information Figure 16-19. HWOPT Register 31 30 29 28 27 26 15 14 13 RESERVED R-X 12 11 10 25 24 23 RESERVED R-X 9 8 NR_OF_FROS R-18h 7 22 21 20 19 18 17 16 6 5 4 3 2 RESERVED R-X 1 0 Table 16-21.
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Random Number Generator www.ti.com 16.7.1.17 HWVER0 Register (Offset = 7Ch) [reset = X] HWVER0 is shown in Figure 16-20 and described in Table 16-22. HW Version 0 EIP Number And Core Revision Figure 16-20. HWVER0 Register 31 30 29 RESERVED R-X 15 14 13 28 27 26 25 HW_MAJOR_VER R-2h 12 11 EIP_NUM_COMPL R-B4h 10 9 24 23 8 7 22 21 HW_MINOR_VER R-X 6 5 20 19 4 3 EIP_NUM R-4Bh 18 17 HW_PATCH_LVL R-X 2 1 16 0 Table 16-22.
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Random Number Generator www.ti.com 16.7.1.18 IRQSTATMASK Register (Offset = 1FD8h) [reset = X] IRQSTATMASK is shown in Figure 16-21 and described in Table 16-23. Interrupt Status After Masking Figure 16-21. IRQSTATMASK Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 SHUTDOWN_ OVF R-X 0 RDY RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 4 RESERVED R-X R-X Table 16-23.
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Random Number Generator www.ti.com 16.7.1.19 HWVER1 Register (Offset = 1FE0h) [reset = X] HWVER1 is shown in Figure 16-22 and described in Table 16-24. HW Version 1 TRNG Revision Number Figure 16-22. HWVER1 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 REV R-20h 2 1 0 Table 16-24. HWVER1 Register Field Descriptions Field Type Reset Description 31-8 Bit RESERVED R X Software should not rely on the value of a reserved.
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Random Number Generator www.ti.com 16.7.1.20 IRQSET Register (Offset = 1FECh) [reset = X] IRQSET is shown in Figure 16-23 and described in Table 16-25. Interrupt Set Figure 16-23. IRQSET Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RDY R/W-X 9 8 7 6 5 4 3 2 1 0 Table 16-25. IRQSET Register Field Descriptions Bit Field Type Reset Description 31-0 RDY R/W X Software should not rely on the value of a reserved.
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Random Number Generator www.ti.com 16.7.1.21 SWRESET Register (Offset = 1FF0h) [reset = X] SWRESET is shown in Figure 16-24 and described in Table 16-26. SW Reset Control Figure 16-24. SWRESET Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RESET R/W-X RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 4 RESERVED R-X Table 16-26.
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Random Number Generator www.ti.com 16.7.1.22 IRQSTAT Register (Offset = 1FF8h) [reset = X] IRQSTAT is shown in Figure 16-25 and described in Table 16-27. Interrupt Status Figure 16-25. IRQSTAT Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 STAT R-X RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 4 RESERVED R-X Table 16-27.
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Chapter 17 SWCU117A – February 2015 – Revised March 2015 AUX – Sensor Controller with Digital and Analog Peripherals This chapter describes the functionality of the AUX subsystem on the CC26xx platform. Topic 17.1 17.2 17.3 17.4 17.5 17.6 17.7 17.8 1186 ........................................................................................................................... Introduction ................................................................................................... Memory Mapping ..
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Introduction www.ti.com 17.1 Introduction AUX is a collective description of all analog peripherals (ADC, comparators, and current source) and the digital modules in the AUX power domain (AUX_PD) such as the sensor controller, timers, time-to-digital converter, and others. AUX_PD is located within the AON voltage domain of the device. The sensor controller has the ability to do its own power and clock management of AUX_PD, independently of the MCU domain.
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Introduction www.ti.com 17.1.1 AUX Hardware Overview Figure 17-1.
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Memory Mapping www.ti.com If the source of the illegal operation is the MCU system, the arbiter returns a Bus Fault. If the source of the illegal access is the sensor controller, the arbiter suspends the sensor controller by setting [AUX_SCE:CTL:SUSPEND], and the flag [AUX_SCE:CPUSTAT:BUS_ERROR] is set. The event bus in AUX routes events between AUX peripherals, as well as to and from the MCU and AON event fabric.
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Memory Mapping www.ti.com Table 17-2.
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IO Mapping www.ti.com Table 17-2.
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Modules • • • • • • • • www.ti.
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Modules www.ti.com 17.4.1.5 Instruction Set The sensor controller instruction set is compact, powerful, and highly regular. The sensor controller is based on the traditional RISC concept of having all operands in the registers, or in an immediate field embedded directly in the instruction opcode. Data memory can only be accessed using load and store operations, while I/O ports can be accessed using input and output instructions as well as special bit-manipulation instructions.
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Modules www.ti.com Table 17-4. Input and Output Instructions (continued) Syntax Description Operation Z N C V out Rd,(Rs) Output indirect reg[rs] = Rd - - - - For instructions using direct peripheral register addressing, an 8-bit address is embedded in the instruction supporting direct access to 256 I/O ports in the range 0 to 255. Using the prefix instruction, the direct I/O address can be extended to 16. 16-bit addressing of I/O is also possible using indirect addressing. 17.4.1.5.
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Modules www.ti.com Table 17-6. Arithmetic and Logical Instructions (continued) Syntax Description Operation Z N C V xor Rd,Rs XOR register Rd ^= Rs x x 0 0 tst Rd,Rs Test register Rd & Rs x x 0 0 Absolute register Rd = Rd > 0 ? Rd : - x Rd x x x neg Rd Negate register Rd = -Rd x x x x not Rd Invert register Rd = ~Rd x x 0 0 Monadic instructions abs Rd For instructions using an immediate operand, an 8-bit immediate is embedded in the instruction word.
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Modules www.ti.com 17.4.1.5.6 Flow Control The sensor controller has support for several powerful flow-control instructions, leading to efficient execution of control flows. 17.4.1.5.6.1 Non-Loop Flow Control Table 17-8 shows all the non-loop flow-control instructions. Table 17-8.
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Modules www.ti.com The branch- event instructions bev0 and bev1 perform conditional branching, depending on event inputs provided directly to the sensor controller from its event input. These are the same events as for the wev0 and wev1 instructions, and are described in Section 17.4.2.1.2, Sensor Controller Events. This branching allows efficient control processing, based on external events.
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Modules www.ti.com Table 17-11. Power Management Instructions Syntax Description Operation Z N C V wev0 #ev Wait event 0 Stop clock until events[ev] == 0 - - - - wev1 #ev Wait event 1 Stop clock until events[ev] == 1 - - - - sleep sleep Stop clock until wakeup, then pc = 2*vector - - - - When a i or wev1 instruction is executed, the sensor controller stops the clock until the selected event is deasserted (0) or asserted (1), respectively.
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Modules www.ti.com The instructions being prefixed has two implications: • The two uppermost bits, 9 and 8, of a 10-bit immediate or direct address embedded in an instruction are ignored, as they are replaced by bits from the prefix register. • No sign extension of an embedded immediate is performed for instructions that would normally do so, as the uppermost bits are provided by the prefix register. 17.4.1.5.
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Modules www.ti.com 17.4.1.7 Running a Program To execute a program on the sensor controller, the program image must first be uploaded to the AUX RAM by the system CPU or DMA. The sensor controller will be halted from reset, and will not receive clock.
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Modules www.ti.com All events triggering actions internally in AUX are described in detail in the corresponding module chapter. There are also events used to wake up AUX, which are described in Section 17.5.3. 17.4.2.1.1 Software-Defined Events There are three software-defined events in AUX that can trigger actions in the AON or MCU domain. These can, for example, be set by the sensor controller to wake up the MCU domain and trigger an interrupt in the system CPU.
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Modules www.ti.com Table 17-15.
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Modules www.ti.com 17.4.3 AUX Timers 17.4.4 Time-to-Digital Converter The high-precision time-to-digital converter (TDC) peripheral measures time between two individually selected start and stop events with high accuracy. The TDC counts on both clock edges, running effectively up to a speed of 96 MHz. The TDC is controlled by a state machine running on the AUX_PD system clock. Typical use cases for TDC are: as part of a system doing capacitive sensing, clock calibration, or pulse counting. 17.4.4.
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Modules www.ti.com If more than one period of a signal is to be measured, the number of stop events to ignore before stopping the measurement must be configured in [AUX_TDC:TRIGCNTLOAD], and the stop counter must be enabled in [AUX_TDC:TRIGCNTCFG]. 17.4.4.2.2 Saturation The TDC can be configured in [AUX_TDC:SATCFG] to saturate and stop the measurement if the counter values are larger than a configurable saturation limit.
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Modules www.ti.com 17.4.8 Analog MUX Between the analog I/Os and the modules connected to them, there are a set of muxes used to connect various inputs to the module. These muxes are configured through the AUX ADI. These I/Os are mapped to the analog-capable sensor controller pins (AUX IO 0 to 7). The muxes can connect peripherals to both analog I/Os and some internal signals. The supported connections are shown Table 17-19. Table 17-19.
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Modules www.ti.com The ADC is powered by VDDR internally, so the capacitive-input sampling stage will scale down the input signal down within the reference range. The user can disable input scaling, but this requires that the maximum input signal voltage to the ADC input is always lower than VDDR, to avoid permanent damage to the ADC. When scaling is enabled (default), the internal fixed reference will seem to be 4.3 V. If input scaling is disabled, the reference will be 1.47 V.
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Modules www.ti.com The source and start polarity is configured in the [AUX_ANAIF:ADCCTL] register. For software triggered sampling, set the start source to an unused value and write to [AUX_ANAIF:ADCTRIG]. 17.4.9.5 FIFO The ADC FIFO is a 4-element large FIFO, storing the result of ADC conversions. ADC samples can be read from the FIFO register [AUX_ANAIF:ADCFIFO]. When a sample is read, it is popped from the FIFO and can be stored by the user.
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Modules www.ti.com 6. Enable the ADC analog core [AUX_ADI:ADC0.EN] and reference [AUX_ADI_ADCREF0.EN]. 7. Release the ADC core from reset: [AUX_ADI:ADC0.RESET_N]. 17.4.9.8.3 Sampling 1. Set the start polarity to rising, and start source to manual (for example, 0x9): [AUX_ANAIF:ADCCTL] 2. Write to the start trigger register [AUX_ANAIF:ADCTRIG]. 3. Wait until the FIFO is no longer empty [AUX_ANAIF:ADCFIFOSTAT], and read the measurement from the FIFO [AUX_ANAIF:ADCFIFO]. 17.4.10 Comparators 17.4.
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Power Management www.ti.com When AUX_PD is in active mode, the device is prevented from entering Standby or Shutdown power modes, as AUX_PD is requesting system resources from the supply system. 17.5.2.2 Power Down Power down is requested when AUX has been disconnected from the system BUS. In power down mode, AUX_PD is on and the sensor controller can still execute programs. The AUX domain receives a clock defined in [AON_WUC:AUXCLK:PWR_DWN_SRC].
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Power Management • www.ti.com Wakeup source programmed in [AON_EVENT:AUXWUSEL] (including RTC channel 2). To clear an AUX wakeup source, the sensor controller or system CPU must clear it through writing to [AUX_WUC:WUEVCLR]. A power-down request should not be done before the flag is read as 0. RTC channel 2 and software events from AON have dedicated clear bits. Any wakeup I/O events on pins routed to AUX will be cleared by writing to [AUX_WUC:WUEVCLR:AON_PROG_WU].
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Clock Management www.ti.com 17.6.1.2 Power Down When AUX is in power down mode, the domain receives a power-down clock, configured in [AON_WUC:AUXCLK:PWR_DWN_SRC]. The options are: Clock Source Description NONE The AUX system receives no system clock. The sensor controller will not run, and any accesses to AUX from the system CPU will return a bus fault. Any peripherals that can run on an asynchronous clock (such as timers and the TDC) will continue to run.
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AUX – Sensor Controller Registers www.ti.com 17.8.1 AUX_AIODIO Registers Table 17-20 lists the memory-mapped registers for the AUX_AIODIO. All register offset addresses not listed in Table 17-20 should be considered as reserved locations and the register contents should not be modified. Table 17-20. AUX_AIODIO Registers Offset 1212 Acronym Register Name Section 0h GPIODOUT General Purpose Input/Output Data Out Section 17.8.1.1 4h IOMODE Input Output Mode Section 17.8.1.
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AUX – Sensor Controller Registers www.ti.com 17.8.1.1 GPIODOUT Register (Offset = 0h) [reset = X] GPIODOUT is shown in Figure 17-3 and described in Table 17-21. General Purpose Input/Output Data Out This register is used to set data on the pads assigned to AUX Figure 17-3. GPIODOUT Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 IO7_0 R/W-X 2 1 0 Table 17-21.
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AUX – Sensor Controller Registers www.ti.com 17.8.1.2 IOMODE Register (Offset = 4h) [reset = X] IOMODE is shown in Figure 17-4 and described in Table 17-22. Input Output Mode Controls pull-up pull-down and output mode for the IO pins assigned to AUX Figure 17-4. IOMODE Register 31 30 29 14 IO7 R/W-X 13 15 28 27 26 25 12 IO6 R/W-X 11 10 IO5 R/W-X 9 24 23 RESERVED R-X 8 IO4 R/W-X 22 21 20 19 18 17 16 6 5 4 3 2 1 0 7 IO3 R/W-X IO2 R/W-X IO1 R/W-X IO0 R/W-X Table 17-22.
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AUX – Sensor Controller Registers www.ti.com Table 17-22. IOMODE Register Field Descriptions (continued) Bit Field Type Reset Description 7-6 IO3 R/W X Selects mode for AUXIO3 (for AIODIO0) or AUXIO11 (for AIODIO1). 0h = Output 1h = Digital input with GPIODIE bit 3 = 1 Analog input/output with GPIODIE bit 3 = 0 2h = Open-drain: The pin is driven low when the corresponding GPIODOUT bit is 0, and otherwise tri-stated or pulled depending on the corresponding IOC configuration.
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AUX – Sensor Controller Registers www.ti.com 17.8.1.3 GPIODIN Register (Offset = 8h) [reset = X] GPIODIN is shown in Figure 17-5 and described in Table 17-23. General Purpose Input Output Data In Figure 17-5. GPIODIN Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 IO7_0 R-X 2 1 0 Table 17-23. GPIODIN Register Field Descriptions Field Type Reset Description 31-8 Bit RESERVED R X Software should not rely on the value of a reserved.
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AUX – Sensor Controller Registers www.ti.com 17.8.1.4 GPIODOUTSET Register (Offset = Ch) [reset = X] GPIODOUTSET is shown in Figure 17-6 and described in Table 17-24. General Purpose Input Output Data Out Set Strobes for setting output data register bits Figure 17-6. GPIODOUTSET Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 IO7_0 R/W-X 2 1 0 Table 17-24.
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AUX – Sensor Controller Registers www.ti.com 17.8.1.5 GPIODOUTCLR Register (Offset = 10h) [reset = X] GPIODOUTCLR is shown in Figure 17-7 and described in Table 17-25. General Purpose Input Output Data Out Clear Strobes for clearing output data register bits Figure 17-7. GPIODOUTCLR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 IO7_0 R/W-X 2 1 0 Table 17-25.
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AUX – Sensor Controller Registers www.ti.com 17.8.1.6 GPIODOUTTGL Register (Offset = 14h) [reset = X] GPIODOUTTGL is shown in Figure 17-8 and described in Table 17-26. General Purpose Input Output Data Out Toggle Strobes for toggling output data register bits Figure 17-8. GPIODOUTTGL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 IO7_0 R/W-X 2 1 0 Table 17-26.
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AUX – Sensor Controller Registers www.ti.com 17.8.1.7 GPIODIE Register (Offset = 18h) [reset = X] GPIODIE is shown in Figure 17-9 and described in Table 17-27. General Purpose Input Output Input Enable Figure 17-9. GPIODIE Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 IO7_0 R/W-X 2 1 0 Table 17-27.
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AUX – Sensor Controller Registers www.ti.com 17.8.2 AUX_TDC Registers Table 17-28 lists the memory-mapped registers for the AUX_TDC. All register offset addresses not listed in Table 17-28 should be considered as reserved locations and the register contents should not be modified. Table 17-28. AUX_TDC Registers Offset Acronym Register Name Section 0h CTL Control Section 17.8.2.1 4h STAT Status Section 17.8.2.2 8h RESULT Result Section 17.8.2.
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AUX – Sensor Controller Registers www.ti.com 17.8.2.1 CTL Register (Offset = 0h) [reset = X] CTL is shown in Figure 17-10 and described in Table 17-29. Control Figure 17-10. CTL Register 31 30 29 28 27 26 25 24 23 RESERVED R-X 15 14 13 12 11 10 9 8 RESERVED R-X 7 22 21 20 19 18 17 6 5 4 3 2 1 16 0 CMD W-X Table 17-29. CTL Register Field Descriptions Field Type Reset Description 31-2 Bit RESERVED R X Software should not rely on the value of a reserved.
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AUX – Sensor Controller Registers www.ti.com 17.8.2.2 STAT Register (Offset = 4h) [reset = X] STAT is shown in Figure 17-11 and described in Table 17-30. Status Figure 17-11. STAT Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 2 1 0 RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 SAT R-X 6 DONE R-X 5 4 3 STATE R-6h Table 17-30.
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AUX – Sensor Controller Registers www.ti.com 17.8.2.3 RESULT Register (Offset = 8h) [reset = X] RESULT is shown in Figure 17-12 and described in Table 17-31. Result Result of last TDC conversion Figure 17-12. RESULT Register 31 30 29 15 14 13 28 27 RESERVED R-X 12 11 26 25 24 23 22 21 20 VALUE R-2h 19 18 17 16 10 9 8 7 6 5 4 3 2 1 0 VALUE R-2h Table 17-31.
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AUX – Sensor Controller Registers www.ti.com 17.8.2.4 SATCFG Register (Offset = Ch) [reset = X] SATCFG is shown in Figure 17-13 and described in Table 17-32. Saturation Configuration Figure 17-13. SATCFG Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 RESERVED R-X 24 23 RESERVED R-X 8 7 22 21 20 19 18 17 16 6 5 4 3 2 1 LIMIT R/W-Fh 0 Table 17-32.
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AUX – Sensor Controller Registers www.ti.com 17.8.2.5 TRIGSRC Register (Offset = 10h) [reset = X] TRIGSRC is shown in Figure 17-14 and described in Table 17-33. Trigger Source TDC start/stop trigger source selection Figure 17-14. TRIGSRC Register 31 30 29 28 27 26 25 24 19 18 17 16 RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 STOP_POL R/W-X 12 11 10 STOP_SRC R/W-X 9 8 6 5 START_POL R/W-X 4 3 2 START_SRC R/W-X 1 0 RESERVED R-X 7 RESERVED R-X Table 17-33.
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AUX – Sensor Controller Registers www.ti.com Table 17-33. TRIGSRC Register Field Descriptions (continued) Field Type Reset Description 12-8 Bit STOP_SRC R/W X Selects the asynchronous stop signal Note! Must not be changed if STAT.
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AUX – Sensor Controller Registers www.ti.com Table 17-33. TRIGSRC Register Field Descriptions (continued) 1228 Bit Field Type Reset Description 4-0 START_SRC R/W X Selects the asynchronous start signal Note! Must not be changed if STAT.
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AUX – Sensor Controller Registers www.ti.com 17.8.2.6 TRIGCNT Register (Offset = 14h) [reset = X] TRIGCNT is shown in Figure 17-15 and described in Table 17-34. Trigger Counter Stop counter status/control of TDC Figure 17-15. TRIGCNT Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 CNT R/W-X 6 5 4 3 2 1 0 Table 17-34.
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AUX – Sensor Controller Registers www.ti.com 17.8.2.7 TRIGCNTLOAD Register (Offset = 18h) [reset = X] TRIGCNTLOAD is shown in Figure 17-16 and described in Table 17-35. Trigger Counter Load Stop counter control of TDC Figure 17-16. TRIGCNTLOAD Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 CNT R/W-X 6 5 4 3 2 1 0 Table 17-35.
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AUX – Sensor Controller Registers www.ti.com 17.8.2.8 TRIGCNTCFG Register (Offset = 1Ch) [reset = X] TRIGCNTCFG is shown in Figure 17-17 and described in Table 17-36. Trigger Counter Configuration Figure 17-17. TRIGCNTCFG Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 RESERVED R-X 8 7 RESERVED R-X 22 21 20 19 18 17 16 6 5 4 3 2 1 0 EN R/W-X Table 17-36.
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AUX – Sensor Controller Registers www.ti.com 17.8.2.9 PRECTL Register (Offset = 20h) [reset = X] PRECTL is shown in Figure 17-18 and described in Table 17-37. Prescaler Control The prescaler can be used to count events that are faster than the AUX clock speed. It can be used standalone or as a start/stop source for the TDC by configuring TRIGSRC.START_SRC and TRIGSRC.STOP_SRC to TDC_PRE.
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AUX – Sensor Controller Registers www.ti.com Table 17-37.
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AUX – Sensor Controller Registers www.ti.com 17.8.2.10 PRECNT Register (Offset = 24h) [reset = X] PRECNT is shown in Figure 17-19 and described in Table 17-38. Prescaler Counter Value of prescaler counter Figure 17-19. PRECNT Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 CNT R/W-X 6 5 4 3 2 1 0 Table 17-38.
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AUX – Sensor Controller Registers www.ti.com 17.8.3 AUX_EVCTL Registers Table 17-39 lists the memory-mapped registers for the AUX_EVCTL. All register offset addresses not listed in Table 17-39 should be considered as reserved locations and the register contents should not be modified. Table 17-39. AUX_EVCTL Registers Offset Acronym Register Name Section 0h VECCFG0 Vector Configuration 0 Section 17.8.3.1 4h VECCFG1 Vector Configuration 1 Section 17.8.3.
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AUX – Sensor Controller Registers www.ti.com 17.8.3.1 VECCFG0 Register (Offset = 0h) [reset = X] VECCFG0 is shown in Figure 17-20 and described in Table 17-40. Vector Configuration 0 AUX_SCE event vectors 0 and 1 configuration Figure 17-20.
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AUX – Sensor Controller Registers www.ti.com Table 17-40. VECCFG0 Register Field Descriptions (continued) Bit Field Type Reset Description VEC1_EV R/W X Selects vector 1 trigger source event.
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AUX – Sensor Controller Registers www.ti.com Table 17-40. VECCFG0 Register Field Descriptions (continued) 1238 Bit Field Type Reset Description 4-0 VEC0_EV R/W X Selects vector 0 trigger source event.
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AUX – Sensor Controller Registers www.ti.com 17.8.3.2 VECCFG1 Register (Offset = 4h) [reset = X] VECCFG1 is shown in Figure 17-21 and described in Table 17-41. Vector Configuration 1 AUX_SCE event vectors 2 and 3 configuration Figure 17-21.
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AUX – Sensor Controller Registers www.ti.com Table 17-41. VECCFG1 Register Field Descriptions (continued) Bit Field Type Reset Description VEC3_EV R/W X Selects vector 3 trigger source event.
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AUX – Sensor Controller Registers www.ti.com Table 17-41. VECCFG1 Register Field Descriptions (continued) Bit Field Type Reset Description 4-0 VEC2_EV R/W X Selects vector 2 trigger source event.
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AUX – Sensor Controller Registers www.ti.com 17.8.3.3 SCEWEVSEL Register (Offset = 8h) [reset = X] SCEWEVSEL is shown in Figure 17-22 and described in Table 17-42. Sensor Controller Engine Wait Event Selection Event selection for the AUX_SCE WEV0, WEV1, BEV0 and BEV1 instructions Figure 17-22. SCEWEVSEL Register 31 30 29 28 27 15 14 13 12 11 26 25 10 9 RESERVED R-X 24 23 RESERVED R-X 8 7 22 21 20 19 18 17 16 6 5 4 3 2 WEV7_EV R/W-X 1 0 Table 17-42.
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AUX – Sensor Controller Registers www.ti.com 17.8.3.4 EVTOAONFLAGS Register (Offset = Ch) [reset = X] EVTOAONFLAGS is shown in Figure 17-23 and described in Table 17-43. Events To AON Domain Flags AUX event flags going to/through the AON domain These events may be used to wake up the MCU domain. The flags may be cleared by writing 0 to these bits or writing 1 to the corresponding bits in EVTOAONFLAGSCLR. Figure 17-23.
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AUX – Sensor Controller Registers www.ti.com 17.8.3.5 EVTOAONPOL Register (Offset = 10h) [reset = X] EVTOAONPOL is shown in Figure 17-24 and described in Table 17-44. Events To AON Domain Polarity AUX event source polarity for the event flags going to/through the AON domain Note the inverse polarity (0 = high, 1 = low). Figure 17-24.
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AUX – Sensor Controller Registers www.ti.com 17.8.3.6 DMACTL Register (Offset = 14h) [reset = X] DMACTL is shown in Figure 17-25 and described in Table 17-45. Direct Memory Access Control Figure 17-25. DMACTL Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 REQ_MODE R/W-X 1 EN R/W-X 0 SEL R/W-X RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 RESERVED R-X 4 Table 17-45.
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AUX – Sensor Controller Registers www.ti.com 17.8.3.7 SWEVSET Register (Offset = 18h) [reset = X] SWEVSET is shown in Figure 17-26 and described in Table 17-46. Software Event Set Strobes for setting software events from the AUX domain to the AON/MCU Domains The use of these events is software-defined. Figure 17-26.
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AUX – Sensor Controller Registers www.ti.com 17.8.3.8 EVSTAT0 Register (Offset = 1Ch) [reset = X] EVSTAT0 is shown in Figure 17-27 and described in Table 17-47. Event Status 0 Current event source levels, 15:0 Figure 17-27.
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AUX – Sensor Controller Registers www.ti.com 17.8.3.9 EVSTAT1 Register (Offset = 20h) [reset = X] EVSTAT1 is shown in Figure 17-28 and described in Table 17-48. Event Status 1 Current event source levels, 31:16 Figure 17-28.
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AUX – Sensor Controller Registers www.ti.com 17.8.3.10 EVTOMCUPOL Register (Offset = 24h) [reset = X] EVTOMCUPOL is shown in Figure 17-29 and described in Table 17-49. Event To MCU Domain Polarity AUX event source polarity for the event flags to the MCU domain Note the inverse polarity (0 = high, 1 = low). Figure 17-29.
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AUX – Sensor Controller Registers www.ti.com Table 17-49. EVTOMCUPOL Register Field Descriptions (continued) Bit 1250 Field Type Reset Description 3 TDC_DONE R/W X Selects the event source level that sets EVTOMCUFLAGS.TDC_DONE. 0h = High level 1h = Low level 2 AUX_COMPB R/W X Selects the event source level that sets EVTOMCUFLAGS.AUX_COMPB. 0h = High level 1h = Low level 1 AUX_COMPA R/W X Selects the event source level that sets EVTOMCUFLAGS.AUX_COMPA.
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AUX – Sensor Controller Registers www.ti.com 17.8.3.11 EVTOMCUFLAGS Register (Offset = 28h) [reset = X] EVTOMCUFLAGS is shown in Figure 17-30 and described in Table 17-50. Events to MCU Domain Flags AUX event flags going to the MCU domain The flags may be cleared by writing 0 to these bits or writing 1 to the corresponding bits in EVTOMCUFLAGSCLR. Figure 17-30.
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AUX – Sensor Controller Registers www.ti.com 17.8.3.12 COMBEVTOMCUMASK Register (Offset = 2Ch) [reset = X] COMBEVTOMCUMASK is shown in Figure 17-31 and described in Table 17-51. Combined Event To MCU Domain Mask Selects which of the flags In EVTOMCUFLAGS that contribute to the AUX_COMB event to the MCU domain The AUX_COMB event is asserted as long as one or more of the included event flags are set. Figure 17-31.
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AUX – Sensor Controller Registers www.ti.com 17.8.3.13 VECFLAGS Register (Offset = 34h) [reset = X] VECFLAGS is shown in Figure 17-32 and described in Table 17-52. Vector Flags If a vector flag has been set and AUX_SCE is sleeping, it will wake up and execute the vector. If multiple vectors have been set, the one with the lowest index will execute first, and the next after returning to sleep. During execution of a vector, the flag must be cleared, by writing a 1 to the corresponding bit in VECFLAGSCLR.
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AUX – Sensor Controller Registers www.ti.com 17.8.3.14 EVTOMCUFLAGSCLR Register (Offset = 38h) [reset = X] EVTOMCUFLAGSCLR is shown in Figure 17-33 and described in Table 17-53. Events To MCU Domain Flags Clear Strobes for clearing flags in EVTOMCUFLAGS. Figure 17-33.
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AUX – Sensor Controller Registers www.ti.com 17.8.3.15 EVTOAONFLAGSCLR Register (Offset = 3Ch) [reset = X] EVTOAONFLAGSCLR is shown in Figure 17-34 and described in Table 17-54. Events To AON Domain Clear Strobes for clearing flags in EVTOAONFLAGS. Figure 17-34.
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AUX – Sensor Controller Registers www.ti.com 17.8.3.16 VECFLAGSCLR Register (Offset = 40h) [reset = X] VECFLAGSCLR is shown in Figure 17-35 and described in Table 17-55. Vector Flags Clear Strobes for clearing flags in VECFLAGS. Figure 17-35. VECFLAGSCLR Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 VEC3 W-X 2 VEC2 W-X 1 VEC1 W-X 0 VEC0 W-X RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 4 RESERVED R-X Table 17-55.
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AUX – Sensor Controller Registers www.ti.com 17.8.4 AON_WUC Registers Table 17-56 lists the memory-mapped registers for the AON_WUC. All register offset addresses not listed in Table 17-56 should be considered as reserved locations and the register contents should not be modified. Table 17-56. AON_WUC Registers Offset Acronym Register Name Section 0h MCUCLK MCU Clock Management Section 17.8.4.1 4h AUXCLK AUX Clock Management Section 17.8.4.2 8h MCUCFG MCU Configuration Section 17.8.4.
PAGE 1258
AUX – Sensor Controller Registers www.ti.com 17.8.4.1 MCUCLK Register (Offset = 0h) [reset = X] MCUCLK is shown in Figure 17-36 and described in Table 17-57. MCU Clock Management This register contains bitfields related to the MCU clock. Figure 17-36. MCUCLK Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 RCOSC_HF_C AL_DONE R/W-X RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 RESERVED 4 R-X 1 0 PWR_DWN_SRC R/W-X Table 17-57.
PAGE 1259
AUX – Sensor Controller Registers www.ti.com 17.8.4.2 AUXCLK Register (Offset = 4h) [reset = X] AUXCLK is shown in Figure 17-37 and described in Table 17-58. AUX Clock Management This register contains bitfields that are relevant for setting up the clock to the AUX domain. Figure 17-37.
PAGE 1260
AUX – Sensor Controller Registers www.ti.com 17.8.4.3 MCUCFG Register (Offset = 8h) [reset = X] MCUCFG is shown in Figure 17-38 and described in Table 17-59. MCU Configuration This register contains power management related bitfields for the MCU domain. Figure 17-38.
PAGE 1261
AUX – Sensor Controller Registers www.ti.com 17.8.4.4 AUXCFG Register (Offset = Ch) [reset = X] AUXCFG is shown in Figure 17-39 and described in Table 17-60. AUX Configuration This register contains power management related signals for the AUX domain. Figure 17-39. AUXCFG Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RAM_RET_EN R/W-1h RESERVED R/W-X 23 22 21 20 RESERVED R/W-X 15 14 13 12 RESERVED R/W-X 7 6 5 4 RESERVED R/W-X Table 17-60.
PAGE 1262
AUX – Sensor Controller Registers www.ti.com 17.8.4.5 AUXCTL Register (Offset = 10h) [reset = X] AUXCTL is shown in Figure 17-40 and described in Table 17-61. AUX Control This register contains events and control signals for the AUX domain. Figure 17-40.
PAGE 1263
AUX – Sensor Controller Registers www.ti.com 17.8.4.6 PWRSTAT Register (Offset = 14h) [reset = X] PWRSTAT is shown in Figure 17-41 and described in Table 17-62. Power Status This register is used to monitor various power management related signals in AON. Most signals are for test, calibration and debug purpose only, and others can be used to detect that AUX or JTAG domains are powered up. Figure 17-41.
PAGE 1264
AUX – Sensor Controller Registers www.ti.com 17.8.4.7 SHUTDOWN Register (Offset = 18h) [reset = X] SHUTDOWN is shown in Figure 17-42 and described in Table 17-63. Shutdown Control This register contains bitfields required for entering shutdown mode Figure 17-42. SHUTDOWN Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 RESERVED R/W-X 8 7 RESERVED R/W-X 22 21 20 19 18 17 16 6 5 4 3 2 1 0 EN R/W-X Table 17-63.
PAGE 1265
AUX – Sensor Controller Registers www.ti.com 17.8.4.8 CTL0 Register (Offset = 20h) [reset = X] CTL0 is shown in Figure 17-43 and described in Table 17-64. Control 0 This register contains various chip level control and debug bitfields. Figure 17-43.
PAGE 1266
AUX – Sensor Controller Registers www.ti.com 17.8.4.9 CTL1 Register (Offset = 24h) [reset = X] CTL1 is shown in Figure 17-44 and described in Table 17-65. Control 1 This register contains various chip level control and debug bitfields. Figure 17-44. CTL1 Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 MCU_RESET_ SRC R/W1C-X 0 MCU_WARM_ RESET R/W1C-X RESERVED R/W-X 23 22 21 20 RESERVED R/W-X 15 14 13 12 RESERVED R/W-X 7 6 5 4 RESERVED R/W-X Table 17-65.
PAGE 1267
AUX – Sensor Controller Registers www.ti.com 17.8.4.10 RECHARGECFG Register (Offset = 30h) [reset = X] RECHARGECFG is shown in Figure 17-45 and described in Table 17-66. Recharge Controller Configuration This register sets all relevant patameters for controlling the recharge algorithm. Figure 17-45.
PAGE 1268
AUX – Sensor Controller Registers www.ti.com Table 17-66. RECHARGECFG Register Field Descriptions (continued) 1268 Bit Field Type Reset Description 2-0 PER_E R/W X Number of 32 KHz clocks between activation of recharge controller For recharge algorithm, PERIOD is the initial period when entering powerdown mode.
PAGE 1269
AUX – Sensor Controller Registers www.ti.com 17.8.4.11 RECHARGESTAT Register (Offset = 34h) [reset = X] RECHARGESTAT is shown in Figure 17-46 and described in Table 17-67. Recharge Controller Status This register controls various status registers which are updated during recharge. The register is mostly intended for test and debug. Figure 17-46.
PAGE 1270
AUX – Sensor Controller Registers www.ti.com 17.8.4.12 OSCCFG Register (Offset = 38h) [reset = X] OSCCFG is shown in Figure 17-47 and described in Table 17-68. Oscillator Configuration This register sets the period for Amplitude compensation requests sent to the oscillator control system. The amplitude compensations is only applicable when XOSC_HF is running in low power mode. Figure 17-47.
PAGE 1271
AUX – Sensor Controller Registers www.ti.com 17.8.4.13 JTAGCFG Register (Offset = 40h) [reset = X] JTAGCFG is shown in Figure 17-48 and described in Table 17-69. JTAG Configuration This register contains control for configuration of the JTAG domain,- hereunder access permissions for each TAP. Figure 17-48.
PAGE 1272
AUX – Sensor Controller Registers www.ti.com 17.8.4.14 JTAGUSERCODE Register (Offset = 44h) [reset = B99A02Fh] JTAGUSERCODE is shown in Figure 17-49 and described in Table 17-70. JTAG USERCODE Boot code copies the JTAG USERCODE to this register from where it is forwarded to the debug subsystem. Figure 17-49. JTAGUSERCODE Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 USER_CODE R/W-B99A02Fh 9 8 7 6 5 4 3 2 1 0 Table 17-70.
PAGE 1273
AUX – Sensor Controller Registers www.ti.com 17.8.5 AUX_TIMER Registers Table 17-71 lists the memory-mapped registers for the AUX_TIMER. All register offset addresses not listed in Table 17-71 should be considered as reserved locations and the register contents should not be modified. Table 17-71. AUX_TIMER Registers Offset Acronym Register Name Section 0h T0CFG Timer 0 Configuration Section 17.8.5.1 4h T1CFG Timer 1 Configuration Section 17.8.5.2 8h T0CTL Timer 0 Control Section 17.8.5.
PAGE 1274
AUX – Sensor Controller Registers www.ti.com 17.8.5.1 T0CFG Register (Offset = 0h) [reset = X] T0CFG is shown in Figure 17-50 and described in Table 17-72. Timer 0 Configuration Figure 17-50. T0CFG Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 TICK_SRC 9 8 1 MODE R/W-X 0 RELOAD R/W-X RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 RESERVED R-X 7 13 TICK_SRC_PO L R/W-X 12 5 4 6 R/W-X PRE R/W-X 3 2 RESERVED R-X Table 17-72.
PAGE 1275
AUX – Sensor Controller Registers www.ti.com Table 17-72.
PAGE 1276
AUX – Sensor Controller Registers www.ti.com 17.8.5.2 T1CFG Register (Offset = 4h) [reset = X] T1CFG is shown in Figure 17-51 and described in Table 17-73. Timer 1 Configuration Figure 17-51. T1CFG Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 TICK_SRC 9 8 1 MODE R/W-X 0 RELOAD R/W-X RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 RESERVED R-X 7 13 TICK_SRC_PO L R/W-X 12 5 4 6 R/W-X PRE R/W-X 3 2 RESERVED R-X Table 17-73.
PAGE 1277
AUX – Sensor Controller Registers www.ti.com Table 17-73.
PAGE 1278
AUX – Sensor Controller Registers www.ti.com 17.8.5.3 T0CTL Register (Offset = 8h) [reset = X] T0CTL is shown in Figure 17-52 and described in Table 17-74. Timer 0 Control Run control/status for timer 0 Figure 17-52. T0CTL Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 RESERVED R-X 8 7 RESERVED R-X 22 21 20 19 18 17 16 6 5 4 3 2 1 0 EN R/W-X Table 17-74.
PAGE 1279
AUX – Sensor Controller Registers www.ti.com 17.8.5.4 T0TARGET Register (Offset = Ch) [reset = X] T0TARGET is shown in Figure 17-53 and described in Table 17-75. Timer 0 Target Target counter value for timer 0 Figure 17-53. T0TARGET Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 VALUE R/W-X 6 5 4 3 2 1 0 Table 17-75.
PAGE 1280
AUX – Sensor Controller Registers www.ti.com 17.8.5.5 T1TARGET Register (Offset = 10h) [reset = X] T1TARGET is shown in Figure 17-54 and described in Table 17-76. Timer 1 Target Target Counter Value Timer 1 Figure 17-54. T1TARGET Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 VALUE R/W-X 2 1 0 Table 17-76.
PAGE 1281
AUX – Sensor Controller Registers www.ti.com 17.8.5.6 T1CTL Register (Offset = 14h) [reset = X] T1CTL is shown in Figure 17-55 and described in Table 17-77. Timer 1 Control Run Control/Status For Timer 1 Figure 17-55. T1CTL Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 RESERVED R-X 8 7 RESERVED R-X 22 21 20 19 18 17 16 6 5 4 3 2 1 0 EN R/W-X Table 17-77.
PAGE 1282
AUX – Sensor Controller Registers www.ti.com 17.8.6 AUX_SMPH Registers Table 17-78 lists the memory-mapped registers for the AUX_SMPH. All register offset addresses not listed in Table 17-78 should be considered as reserved locations and the register contents should not be modified. Table 17-78. AUX_SMPH Registers Offset 1282 Acronym Register Name Section 0h SMPH0 Semaphore 0 Section 17.8.6.1 4h SMPH1 Semaphore 1 Section 17.8.6.2 8h SMPH2 Semaphore 2 Section 17.8.6.
PAGE 1283
AUX – Sensor Controller Registers www.ti.com 17.8.6.1 SMPH0 Register (Offset = 0h) [reset = X] SMPH0 is shown in Figure 17-56 and described in Table 17-79. Semaphore 0 Figure 17-56. SMPH0 Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 STAT R/W-1h RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 4 RESERVED R-X Table 17-79.
PAGE 1284
AUX – Sensor Controller Registers www.ti.com 17.8.6.2 SMPH1 Register (Offset = 4h) [reset = X] SMPH1 is shown in Figure 17-57 and described in Table 17-80. Semaphore 1 Figure 17-57. SMPH1 Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 STAT R/W-1h RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 4 RESERVED R-X Table 17-80.
PAGE 1285
AUX – Sensor Controller Registers www.ti.com 17.8.6.3 SMPH2 Register (Offset = 8h) [reset = X] SMPH2 is shown in Figure 17-58 and described in Table 17-81. Semaphore 2 Figure 17-58. SMPH2 Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 STAT R/W-1h RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 4 RESERVED R-X Table 17-81.
PAGE 1286
AUX – Sensor Controller Registers www.ti.com 17.8.6.4 SMPH3 Register (Offset = Ch) [reset = X] SMPH3 is shown in Figure 17-59 and described in Table 17-82. Semaphore 3 Figure 17-59. SMPH3 Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 STAT R/W-1h RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 4 RESERVED R-X Table 17-82.
PAGE 1287
AUX – Sensor Controller Registers www.ti.com 17.8.6.5 SMPH4 Register (Offset = 10h) [reset = X] SMPH4 is shown in Figure 17-60 and described in Table 17-83. Semaphore 4 Figure 17-60. SMPH4 Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 STAT R/W-1h RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 4 RESERVED R-X Table 17-83.
PAGE 1288
AUX – Sensor Controller Registers www.ti.com 17.8.6.6 SMPH5 Register (Offset = 14h) [reset = X] SMPH5 is shown in Figure 17-61 and described in Table 17-84. Semaphore 5 Figure 17-61. SMPH5 Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 STAT R/W-1h RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 4 RESERVED R-X Table 17-84.
PAGE 1289
AUX – Sensor Controller Registers www.ti.com 17.8.6.7 SMPH6 Register (Offset = 18h) [reset = X] SMPH6 is shown in Figure 17-62 and described in Table 17-85. Semaphore 6 Figure 17-62. SMPH6 Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 STAT R/W-1h RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 4 RESERVED R-X Table 17-85.
PAGE 1290
AUX – Sensor Controller Registers www.ti.com 17.8.6.8 SMPH7 Register (Offset = 1Ch) [reset = X] SMPH7 is shown in Figure 17-63 and described in Table 17-86. Semaphore 7 Figure 17-63. SMPH7 Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 STAT R/W-1h RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 4 RESERVED R-X Table 17-86.
PAGE 1291
AUX – Sensor Controller Registers www.ti.com 17.8.6.9 AUTOTAKE Register (Offset = 20h) [reset = X] AUTOTAKE is shown in Figure 17-64 and described in Table 17-87. Sticky Request For Single Semaphore Figure 17-64. AUTOTAKE Register 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 RESERVED R-X 9 8 RESERVED R-X 7 22 21 20 19 18 17 16 6 5 4 3 2 1 SMPH_ID R/W-X 0 Table 17-87.
PAGE 1292
AUX – Sensor Controller Registers www.ti.com 17.8.7 AUX_ANAIF Registers Table 17-88 lists the memory-mapped registers for the AUX_ANAIF. All register offset addresses not listed in Table 17-88 should be considered as reserved locations and the register contents should not be modified. Table 17-88. AUX_ANAIF Registers 1292 Offset Acronym Register Name 10h ADCCTL ADC Control Section 17.8.7.1 14h ADCFIFOSTAT ADC FIFO Status Section 17.8.7.2 18h ADCFIFO ADC FIFO Section 17.8.7.
PAGE 1293
AUX – Sensor Controller Registers www.ti.com 17.8.7.1 ADCCTL Register (Offset = 10h) [reset = X] ADCCTL is shown in Figure 17-65 and described in Table 17-89. ADC Control Figure 17-65. ADCCTL Register 31 30 29 28 27 26 25 24 19 18 17 16 8 RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 START_POL R/W-X 12 11 10 START_SRC R/W-X 9 6 5 4 3 2 1 RESERVED R-X 7 RESERVED R-X 0 CMD R/W-X Table 17-89.
PAGE 1294
AUX – Sensor Controller Registers www.ti.com Table 17-89. ADCCTL Register Field Descriptions (continued) Field Type Reset Description 12-8 Bit START_SRC R/W X Selected source for ADC conversion start event. The start source selected by this field is OR'ed with any trigger coming from writes to ADCTRIG.START. If it is desired to only trigger ADC conversions by writes to ADCTRIG.
PAGE 1295
AUX – Sensor Controller Registers www.ti.com 17.8.7.2 ADCFIFOSTAT Register (Offset = 14h) [reset = X] ADCFIFOSTAT is shown in Figure 17-66 and described in Table 17-90. ADC FIFO Status FIFO can hold up to four ADC samples Figure 17-66. ADCFIFOSTAT Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 UNDERFLOW R-X 2 FULL R-X 1 ALMOST_FULL R-X 0 EMPTY R-1h RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 RESERVED R-X 5 4 OVERFLOW R-X Table 17-90.
PAGE 1296
AUX – Sensor Controller Registers www.ti.com 17.8.7.3 ADCFIFO Register (Offset = 18h) [reset = X] ADCFIFO is shown in Figure 17-67 and described in Table 17-91. ADC FIFO Figure 17-67. ADCFIFO Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 DATA R/W-X 4 3 2 1 0 Table 17-91. ADCFIFO Register Field Descriptions Field Type Reset Description 31-12 Bit RESERVED R X Software should not rely on the value of a reserved.
PAGE 1297
AUX – Sensor Controller Registers www.ti.com 17.8.7.4 ADCTRIG Register (Offset = 1Ch) [reset = X] ADCTRIG is shown in Figure 17-68 and described in Table 17-92. ADC Trigger Figure 17-68. ADCTRIG Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 START W-X RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 4 RESERVED R-X Table 17-92.
PAGE 1298
AUX – Sensor Controller Registers www.ti.com 17.8.7.5 ISRCCTL Register (Offset = 20h) [reset = X] ISRCCTL is shown in Figure 17-69 and described in Table 17-93. Current Source Control Figure 17-69. ISRCCTL Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RESET_N R/W-1h RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 4 RESERVED R-X Table 17-93.
PAGE 1299
AUX – Sensor Controller Registers www.ti.com 17.8.8 ADI_4_AUX Registers Table 17-94 lists the memory-mapped registers for the ADI_4_AUX. All register offset addresses not listed in Table 17-94 should be considered as reserved locations and the register contents should not be modified. Table 17-94. ADI_4_AUX Registers Offset Acronym Register Name 0h MUX0 Multiplexer 0 Section 17.8.8.1 1h MUX1 Multiplexer 1 Section 17.8.8.2 2h MUX2 Multiplexer 2 Section 17.8.8.
PAGE 1300
AUX – Sensor Controller Registers www.ti.com 17.8.8.1 MUX0 Register (Offset = 0h) [reset = X] MUX0 is shown in Figure 17-70 and described in Table 17-95. Internal. Only to be used through TI provided API. Figure 17-70. MUX0 Register 7 6 5 4 3 2 COMPA_IN R/W-X 1 0 COMPA_REF R/W-X Table 17-95. MUX0 Register Field Descriptions Bit Field Type Reset Description 7-4 COMPA_IN R/W X Internal. Only to be used through TI provided API. 0h = Internal.
PAGE 1301
AUX – Sensor Controller Registers www.ti.com 17.8.8.2 MUX1 Register (Offset = 1h) [reset = X] MUX1 is shown in Figure 17-71 and described in Table 17-96. Internal. Only to be used through TI provided API. Figure 17-71. MUX1 Register 7 6 5 4 3 2 1 0 COMPA_IN R/W-X Table 17-96. MUX1 Register Field Descriptions Bit Field Type Reset Description 7-0 COMPA_IN R/W X Internal. Only to be used through TI provided API. 0h = Internal. Only to be used through TI provided API. 1h = Internal.
PAGE 1302
AUX – Sensor Controller Registers www.ti.com 17.8.8.3 MUX2 Register (Offset = 2h) [reset = X] MUX2 is shown in Figure 17-72 and described in Table 17-97. Internal. Only to be used through TI provided API. Figure 17-72. MUX2 Register 7 6 5 ADCCOMPB_IN R/W-X 4 3 2 1 COMPB_REF R/W-X 0 Table 17-97. MUX2 Register Field Descriptions 1302 Bit Field Type Reset Description 7-3 ADCCOMPB_IN R/W X Internal. Only to be used through TI provided API. 0h = Internal.
PAGE 1303
AUX – Sensor Controller Registers www.ti.com 17.8.8.4 MUX3 Register (Offset = 3h) [reset = X] MUX3 is shown in Figure 17-73 and described in Table 17-98. Internal. Only to be used through TI provided API. Figure 17-73. MUX3 Register 7 6 5 4 3 ADCCOMPB_IN R/W-X 2 1 0 Table 17-98. MUX3 Register Field Descriptions Bit Field Type Reset Description 7-0 ADCCOMPB_IN R/W X Internal. Only to be used through TI provided API. 0h = Internal. Only to be used through TI provided API. 1h = Internal.
PAGE 1304
AUX – Sensor Controller Registers www.ti.com 17.8.8.5 ISRC Register (Offset = 4h) [reset = X] ISRC is shown in Figure 17-74 and described in Table 17-99. Current Source Strength and trim control for current source Figure 17-74. ISRC Register 7 6 5 4 3 2 TRIM R/W-X 1 RESERVED R/W-X 0 EN R/W-X Table 17-99. ISRC Register Field Descriptions 1304 Bit Field Type Reset Description 7-2 TRIM R/W X Adjust current from current source. Output currents may be combined to get desired total current.
PAGE 1305
AUX – Sensor Controller Registers www.ti.com 17.8.8.6 COMP Register (Offset = 5h) [reset = X] COMP is shown in Figure 17-75 and described in Table 17-100. Comparator Control COMPA and COMPB comparators Figure 17-75. COMP Register 7 COMPA_REF_ RES_EN R/W-X 6 COMPA_REF_ CURR_EN R/W-X 5 4 COMPB_TRIM 3 2 COMPB_EN 1 RESERVED 0 COMPA_EN R/W-X R/W-X R/W-X R/W-X Table 17-100.
PAGE 1306
AUX – Sensor Controller Registers www.ti.com 17.8.8.7 MUX4 Register (Offset = 7h) [reset = X] MUX4 is shown in Figure 17-76 and described in Table 17-101. Internal. Only to be used through TI provided API. Figure 17-76. MUX4 Register 7 6 5 4 3 2 1 0 COMPA_REF R/W-X Table 17-101. MUX4 Register Field Descriptions 1306 Bit Field Type Reset Description 7-0 COMPA_REF R/W X Internal. Only to be used through TI provided API. 0h = Internal. Only to be used through TI provided API.
PAGE 1307
AUX – Sensor Controller Registers www.ti.com 17.8.8.8 ADC0 Register (Offset = 8h) [reset = X] ADC0 is shown in Figure 17-77 and described in Table 17-102. ADC Control 0 Figure 17-77. ADC0 Register 7 SMPL_MODE R/W-X 6 5 4 SMPL_CYCLE_EXP R/W-X 3 2 RESERVED R/W-X 1 RESET_N R/W-X 0 EN R/W-X Table 17-102. ADC0 Register Field Descriptions Bit Field Type Reset Description SMPL_MODE R/W X ADC Sampling mode: 0: Synchronous mode 1: Asynchronous mode The ADC does a sample-and-hold before conversion.
PAGE 1308
AUX – Sensor Controller Registers www.ti.com 17.8.8.9 ADC1 Register (Offset = 9h) [reset = X] ADC1 is shown in Figure 17-78 and described in Table 17-103. ADC Control 1 Figure 17-78. ADC1 Register 7 6 5 4 3 2 1 0 RESERVED R/W-X Table 17-103. ADC1 Register Field Descriptions 1308 Bit Field Type Reset Description 7-0 RESERVED R/W X Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
PAGE 1309
AUX – Sensor Controller Registers www.ti.com 17.8.8.10 ADCREF0 Register (Offset = Ah) [reset = X] ADCREF0 is shown in Figure 17-79 and described in Table 17-104. ADC Reference 0 Control reference used by the ADC Figure 17-79. ADCREF0 Register 7 RESERVED R/W-X 6 REF_ON_IDLE R/W-X 5 4 RESERVED R/W-X 3 SRC R/W-X 2 1 RESERVED R/W-X 0 EN R/W-X Table 17-104. ADCREF0 Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W X Software should not rely on the value of a reserved.
PAGE 1310
AUX – Sensor Controller Registers www.ti.com 17.8.8.11 ADCREF1 Register (Offset = Bh) [reset = X] ADCREF1 is shown in Figure 17-80 and described in Table 17-105. ADC Reference 1 Control reference used by the ADC Figure 17-80. ADCREF1 Register 7 6 5 4 3 RESERVED R/W-X 2 1 0 VTRIM R/W-X Table 17-105. ADCREF1 Register Field Descriptions 1310 Bit Field Type Reset Description 7-6 RESERVED R/W X Software should not rely on the value of a reserved.
PAGE 1311
Chapter 18 SWCU117A – February 2015 – Revised March 2015 Battery Monitor and Temperature Sensor This chapter describes the CC26xx battery monitor and temperature sensor. Topic 18.1 18.2 18.3 ........................................................................................................................... Page Introduction ................................................................................................... 1312 Functional Description ..............................................
PAGE 1312
Introduction www.ti.com 18.1 Introduction The battery monitor is a small block automatically enabled at boot which monitors both the VDDS supply voltage and the temperature through an on-chip temperature sensor. The battery monitor provides voltage and temperature information to several modules, including the flash and the radio, to ensure correct operation and lowest power consumption. It is thus not recommended to modify any settings in the battery monitor or turn if off. 18.
PAGE 1313
BATMON Registers www.ti.com 18.3.1 AON_BATMON Registers Table 18-1 lists the memory-mapped registers for the AON_BATMON. All register offset addresses not listed in Table 18-1 should be considered as reserved locations and the register contents should not be modified. Table 18-1. AON_BATMON Registers Offset Acronym Register Name 0h CTL Control Section 18.3.1.1 4h MEASCFG Measurement Periode Configuration Section 18.3.1.2 Ch TEMPP0 Temperature Calculation Parameter 0 Section 18.3.1.
PAGE 1314
BATMON Registers www.ti.com 18.3.1.1 CTL Register (Offset = 0h) [reset = X] CTL is shown in Figure 18-1 and described in Table 18-2. Internal. Only to be used through TI provided API. Figure 18-1. CTL Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 CALC_EN R/W-X 0 MEAS_EN R/W-X RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 4 RESERVED R-X Table 18-2.
PAGE 1315
BATMON Registers www.ti.com 18.3.1.2 MEASCFG Register (Offset = 4h) [reset = X] MEASCFG is shown in Figure 18-2 and described in Table 18-3. Internal. Only to be used through TI provided API. Figure 18-2. MEASCFG Register 31 30 29 28 27 26 25 24 23 RESERVED R-X 15 14 13 12 11 10 9 8 RESERVED R-X 7 22 21 20 19 18 17 16 6 5 4 3 2 1 0 PER R/W-X Table 18-3. MEASCFG Register Field Descriptions Field Type Reset Description 31-2 Bit RESERVED R X Internal.
PAGE 1316
BATMON Registers www.ti.com 18.3.1.3 TEMPP0 Register (Offset = Ch) [reset = X] TEMPP0 is shown in Figure 18-3 and described in Table 18-4. Internal. Only to be used through TI provided API. Figure 18-3. TEMPP0 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 CFG R/W-X 2 1 0 Table 18-4. TEMPP0 Register Field Descriptions Field Type Reset Description 31-8 Bit RESERVED R X Internal. Only to be used through TI provided API.
PAGE 1317
BATMON Registers www.ti.com 18.3.1.4 TEMPP1 Register (Offset = 10h) [reset = X] TEMPP1 is shown in Figure 18-4 and described in Table 18-5. Internal. Only to be used through TI provided API. Figure 18-4. TEMPP1 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 CFG R/W-X 1 0 Table 18-5. TEMPP1 Register Field Descriptions Field Type Reset Description 31-6 Bit RESERVED R X Internal. Only to be used through TI provided API.
PAGE 1318
BATMON Registers www.ti.com 18.3.1.5 TEMPP2 Register (Offset = 14h) [reset = X] TEMPP2 is shown in Figure 18-5 and described in Table 18-6. Internal. Only to be used through TI provided API. Figure 18-5. TEMPP2 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 1 CFG R/W-X 0 Table 18-6. TEMPP2 Register Field Descriptions Field Type Reset Description 31-5 Bit RESERVED R X Internal. Only to be used through TI provided API.
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BATMON Registers www.ti.com 18.3.1.6 BATMONP0 Register (Offset = 18h) [reset = X] BATMONP0 is shown in Figure 18-6 and described in Table 18-7. Internal. Only to be used through TI provided API. Figure 18-6. BATMONP0 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 CFG R/W-X 1 0 Table 18-7. BATMONP0 Register Field Descriptions Field Type Reset Description 31-6 Bit RESERVED R X Internal. Only to be used through TI provided API.
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BATMON Registers www.ti.com 18.3.1.7 BATMONP1 Register (Offset = 1Ch) [reset = X] BATMONP1 is shown in Figure 18-7 and described in Table 18-8. Internal. Only to be used through TI provided API. Figure 18-7. BATMONP1 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 CFG R/W-X 1 0 Table 18-8. BATMONP1 Register Field Descriptions Field Type Reset Description 31-6 Bit RESERVED R X Internal. Only to be used through TI provided API.
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BATMON Registers www.ti.com 18.3.1.8 IOSTRP0 Register (Offset = 20h) [reset = X] IOSTRP0 is shown in Figure 18-8 and described in Table 18-9. Internal. Only to be used through TI provided API. Figure 18-8. IOSTRP0 Register 31 30 29 28 27 26 25 15 14 13 12 11 10 RESERVED R-X 9 24 23 RESERVED R-X 8 7 22 21 20 19 18 17 16 6 5 4 3 2 1 0 CFG2 R/W-2h CFG1 R/W-8h Table 18-9. IOSTRP0 Register Field Descriptions Field Type Reset Description 31-6 Bit RESERVED R X Internal.
PAGE 1322
BATMON Registers www.ti.com 18.3.1.9 FLASHPUMPP0 Register (Offset = 24h) [reset = X] FLASHPUMPP0 is shown in Figure 18-9 and described in Table 18-10. Internal. Only to be used through TI provided API. Figure 18-9. FLASHPUMPP0 Register 31 30 29 28 27 26 25 24 19 18 17 16 9 8 FALLB R/W-X 1 0 RESERVED R-X 23 22 21 20 RESERVED R-X 15 7 14 13 12 RESERVED R-X 11 10 6 5 LOWLIM R/W-X 4 OVR R/W-X 3 2 HIGHLIM R/W-X CFG R/W-X Table 18-10.
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BATMON Registers www.ti.com 18.3.1.10 BAT Register (Offset = 28h) [reset = X] BAT is shown in Figure 18-10 and described in Table 18-11. Last Measured Battery Voltage This register may be read while BATUPD.STAT = 1 Figure 18-10. BAT Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 RESERVED INT R-X R-X 7 6 5 4 3 FRAC R-X 2 1 0 Table 18-11.
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BATMON Registers www.ti.com 18.3.1.11 BATUPD Register (Offset = 2Ch) [reset = X] BATUPD is shown in Figure 18-11 and described in Table 18-12. Battery Update Indicates BAT Updates Figure 18-11. BATUPD Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 STAT R/W1C-X RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 4 RESERVED R-X Table 18-12.
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BATMON Registers www.ti.com 18.3.1.12 TEMP Register (Offset = 30h) [reset = X] TEMP is shown in Figure 18-12 and described in Table 18-13. Temperature Last Measured Temperature in Degrees Celsius This register may be read while TEMPUPD.STAT = 1. Figure 18-12. TEMP Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED INT R-X R-X 9 8 7 6 5 4 3 2 RESERVED R-X 1 0 Table 18-13.
PAGE 1326
BATMON Registers www.ti.com 18.3.1.13 TEMPUPD Register (Offset = 34h) [reset = X] TEMPUPD is shown in Figure 18-13 and described in Table 18-14. Temperature Update Indicates TEMP Updates Figure 18-13. TEMPUPD Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 STAT R/W1C-X RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 4 RESERVED R-X Table 18-14.
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Chapter 19 SWCU117A – February 2015 – Revised March 2015 Universal Asynchronous Receivers and Transmitters (UARTS) Topic 19.1 19.2 19.3 19.4 19.5 19.6 19.7 ........................................................................................................................... Universal Asynchronous Receiver/Transmitter ................................................... Block Diagram ................................................................................................ Signal Description...
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Universal Asynchronous Receiver/Transmitter www.ti.com 19.
PAGE 1329
Block Diagram www.ti.com 19.2 Block Diagram Figure 19-1 shows the UART module block diagram. Figure 19-1.
PAGE 1330
Functional Description www.ti.com 19.4.1 Transmit and Receive Logic The transmit logic performs parallel-to-serial conversion on the data read from the TX FIFO. The control logic outputs the serial bit stream, beginning with a start bit and followed by the data bits (LSB first), parity bit, and the stop bits according to the programmed configuration in the control registers. See Figure 19-2 for details.
PAGE 1331
Functional Description www.ti.com The start bit is valid and recognized if the UARTRXD signal is still low on the eighth cycle of the baud rate clock otherwise the start bit is ignored. After a valid start bit is detected, successive data bits are sampled on every sixteenth cycle of the baud rate clock. The parity bit is then checked if parity mode is enabled. Data length and parity are defined in the [UART_LCRH] register.
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Functional Description www.ti.com 19.4.5 FIFO Operation The UART has two 16-entry FIFOs; one for transmit and one for receive. Both FIFOs are accessed through the UART Data [UART_DR] register. Read operations of the [UART_DR] register return a 12-bit value consisting of 8 data bits and 4 error flags, while write operations place 8-bit data in the TX FIFO. Out of reset, both FIFOs are disabled and act as 1-byte-deep holding registers.
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Functional Description www.ti.com • • • • TX: The transmit interrupt changes state when one of the following events occurs: – If the FIFOs are enabled and the transmit FIFO is equal to or lower than the programmed trigger level, then the transmit interrupt is asserted high. The transmit interrupt is cleared by writing data to the transmit FIFO until it becomes greater than the trigger level, or by clearing the interrupt.
PAGE 1334
Initialization and Configuration www.ti.com Figure 19-3. µDMA Example UART DMA active CH1 DMA RX Clear DMA active CH2 DMA TX Clear DMA Channel 2 SREQ DMA Event UART0_TX_DMASREQ DMA Channel 2 REQ UART0_TX_DMABREQ DMA Channel 1 SREQ UART0_TX_DMASREQ DMA Channel 1 REQ UART0_TX_DMABREQ UART DMA Controller DMA Channel 14 REQ UART Interrupt CPU DMA done CH2 DMA done CH1 UART Interrupt Controller 19.
PAGE 1335
UARTS Registers www.ti.com To enable and initialize the UART, use the following steps: 1.
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UARTS Registers www.ti.com 19.7.1 UART Registers Table 19-3 lists the memory-mapped registers for the UART. All register offset addresses not listed in Table 19-3 should be considered as reserved locations and the register contents should not be modified. Table 19-3. UART Registers Offset 1336 Acronym Register Name 0h DR Data Section 19.7.1.1 Section 4h RSR Status Section 19.7.1.2 4h ECR Error Clear Section 19.7.1.3 18h FR Flag Section 19.7.1.
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UARTS Registers www.ti.com 19.7.1.1 DR Register (Offset = 0h) [reset = X] DR is shown in Figure 19-4 and described in Table 19-4. Data For words to be transmitted: - if the FIFOs are enabled (LCRH.FEN = 1), data written to this location is pushed onto the transmit FIFO - if the FIFOs are not enabled (LCRH.FEN = 0), data is stored in the transmitter holding register (the bottom word of the transmit FIFO). The write operation initiates transmission from the UART.
PAGE 1338
UARTS Registers www.ti.com 19.7.1.2 RSR Register (Offset = 4h) [reset = X] RSR is shown in Figure 19-5 and described in Table 19-5. Status This register is mapped to the same address as ECR register. Reads from this address are associated with RSR register and return the receive status. Writes to this address are associated with ECR register and clear the receive status flags (framing, parity, break, and overrun errors).
PAGE 1339
UARTS Registers www.ti.com 19.7.1.3 ECR Register (Offset = 4h) [reset = X] ECR is shown in Figure 19-6 and described in Table 19-6. Error Clear This register is mapped to the same address as RSR register. Reads from this address are associated with RSR register and return the receive status. Writes to this address are associated with ECR register and clear the receive status flags (framing, parity, break, and overrun errors). Figure 19-6.
PAGE 1340
UARTS Registers www.ti.com 19.7.1.4 FR Register (Offset = 18h) [reset = X] FR is shown in Figure 19-7 and described in Table 19-7. Flag Reads from this register return the UART flags. Figure 19-7. FR Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 BUSY R-X 2 1 0 CTS R-0h RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 TXFE R-1h 6 RXFF R-X 5 TXFF R-X 4 RXFE R-1h RESERVED R-X Table 19-7.
PAGE 1341
UARTS Registers www.ti.com 19.7.1.5 IBRD Register (Offset = 24h) [reset = X] IBRD is shown in Figure 19-8 and described in Table 19-8. Integer Baud-Rate Divisor If this register is modified while trasmission or reception is on-going, the baudrate will not be updated until transmission or reception of the current character is complete. Figure 19-8. IBRD Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R/W-X 9 8 7 DIVINT R/W-X 6 5 4 3 2 1 0 Table 19-8.
PAGE 1342
UARTS Registers www.ti.com 19.7.1.6 FBRD Register (Offset = 28h) [reset = X] FBRD is shown in Figure 19-9 and described in Table 19-9. Fractional Baud-Rate Divisor If this register is modified while trasmission or reception is on-going, the baudrate will not be updated until transmission or reception of the current character is complete. Figure 19-9.
PAGE 1343
UARTS Registers www.ti.com 19.7.1.7 LCRH Register (Offset = 2Ch) [reset = X] LCRH is shown in Figure 19-10 and described in Table 19-10. Line Control Figure 19-10. LCRH Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 STP2 R/W-X 2 EPS R/W-X 1 PEN R/W-X 0 BRK R/W-X RESERVED R/W-X 23 22 21 20 RESERVED R/W-X 15 14 13 12 RESERVED R/W-X 7 SPS R/W-X 6 5 4 FEN R/W-X WLEN R/W-X Table 19-10.
PAGE 1344
UARTS Registers www.ti.com 19.7.1.8 CTL Register (Offset = 30h) [reset = X] CTL is shown in Figure 19-11 and described in Table 19-11. Control Figure 19-11. CTL Register 31 30 29 28 27 26 25 24 19 18 17 16 11 RTS R/W-X 10 RESERVED R/W-X 9 RXE R/W-1h 8 TXE R/W-1h 3 2 1 0 UARTEN R/W-X RESERVED R-X 23 22 21 20 RESERVED R-X 15 CTSEN R/W-X 14 RTSEN R/W-X 13 7 LBE R/W-X 6 5 12 RESERVED R/W-X 4 RESERVED R/W-X Table 19-11.
PAGE 1345
UARTS Registers www.ti.com 19.7.1.9 IFLS Register (Offset = 34h) [reset = X] IFLS is shown in Figure 19-12 and described in Table 19-12. Interrupt FIFO Level Select Figure 19-12. IFLS Register 31 30 29 28 27 26 25 15 14 13 12 11 10 RESERVED R/W-X 9 24 23 RESERVED R/W-X 8 7 22 21 20 19 18 17 16 6 5 4 RXSEL R/W-2h 3 2 1 TXSEL R/W-2h 0 Table 19-12.
PAGE 1346
UARTS Registers www.ti.com 19.7.1.10 IMSC Register (Offset = 38h) [reset = X] IMSC is shown in Figure 19-13 and described in Table 19-13. Interrupt Mask Set/Clear Figure 19-13. IMSC Register 31 30 29 28 27 26 25 24 19 18 17 16 10 OEIM R/W-X 9 BEIM R/W-X 8 PEIM R/W-X 2 1 CTSMIM R/W-X 0 RESERVED R/W-X RESERVED R/W-X 23 22 21 20 RESERVED R/W-X 15 14 13 RESERVED R/W-X 12 11 7 FEIM R/W-X 6 RTIM R/W-X 5 TXIM R/W-X 4 RXIM R/W-X 3 RESERVED R/W-X Table 19-13.
PAGE 1347
UARTS Registers www.ti.com Table 19-13. IMSC Register Field Descriptions (continued) Bit Field Type Reset Description 4 RXIM R/W X Receive interrupt mask. A read returns the current mask for UART's receive interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.RXMIS. A write of 0 clears the mask which means MIS.RXMIS will not reflect the interrupt. RESERVED R/W X Software should not rely on the value of a reserved.
PAGE 1348
UARTS Registers www.ti.com 19.7.1.11 RIS Register (Offset = 3Ch) [reset = X] RIS is shown in Figure 19-14 and described in Table 19-14. Raw Interrupt Status Figure 19-14. RIS Register 31 30 29 28 27 26 25 24 19 18 17 16 10 OERIS R-X 9 BERIS R-X 8 PERIS R-X 2 1 CTSRMIS R-0h 0 RESERVED R-1h RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 RESERVED R-X 12 11 7 FERIS R-X 6 RTRIS R-X 5 TXRIS R-X 4 RXRIS R-X 3 RESERVED R-3h Table 19-14.
PAGE 1349
UARTS Registers www.ti.com Table 19-14. RIS Register Field Descriptions (continued) Bit Field Type Reset Description 5 TXRIS R X Transmit interrupt status: This field returns the raw interrupt state of UART's transmit interrupt. When FIFOs are enabled (LCRH.FEN = 1), the transmit interrupt is asserted if the number of bytes in transmit FIFO is equal to or lower than the programmed trigger level (IFLS.TXSEL).
PAGE 1350
UARTS Registers www.ti.com 19.7.1.12 MIS Register (Offset = 40h) [reset = X] MIS is shown in Figure 19-15 and described in Table 19-15. Masked Interrupt Status Figure 19-15. MIS Register 31 30 29 28 27 26 25 24 19 18 17 16 10 OEMIS R-X 9 BEMIS R-X 8 PEMIS R-X 2 1 CTSMMIS R-X 0 RESERVED R-X RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 RESERVED R-X 12 11 7 FEMIS R-X 6 RTMIS R-X 5 TXMIS R-X 4 RXMIS R-X 3 RESERVED R-X Table 19-15.
PAGE 1351
UARTS Registers www.ti.com 19.7.1.13 ICR Register (Offset = 44h) [reset = 0h] ICR is shown in Figure 19-16 and described in Table 19-16. Interrupt Clear On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. Figure 19-16.
PAGE 1352
UARTS Registers www.ti.com 19.7.1.14 DMACTL Register (Offset = 48h) [reset = X] DMACTL is shown in Figure 19-17 and described in Table 19-17. DMA Control Figure 19-17. DMACTL Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 DMAONERR R/W-X 1 TXDMAE R/W-X 0 RXDMAE R/W-X RESERVED R/W-X 23 22 21 20 RESERVED R/W-X 15 14 13 12 RESERVED R/W-X 7 6 5 RESERVED R/W-X 4 Table 19-17.
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Chapter 20 SWCU117A – February 2015 – Revised March 2015 Synchronous Serial Interface (SSI) This chapter describes the synchronous serial interface. Topic 20.1 20.2 20.3 20.4 20.5 20.6 20.7 ........................................................................................................................... Synchronous Serial Interface ........................................................................... Block Diagram ............................................................................
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Synchronous Serial Interface www.ti.com 20.
PAGE 1355
Block Diagram www.ti.com 20.2 Block Diagram Figure 20-1 shows the SSI block diagram. Figure 20-1.
PAGE 1356
Signal Description www.ti.com 20.3 Signal Description Table 20-1 lists the external signals of the SSI module and describes the function of each. The SSI signals are selected in the IOC module through the [IOCFGxx] registers. For more information on configuring GPIOs, see Chapter 4, Interrupts and Events. Table 20-1.
PAGE 1357
Functional Description www.ti.com In slave mode, the SSI transmits data each time the master initiates a transaction. If the TX FIFO is empty and the master initiates, the slave transmits the eighth most-recent value in the transmit FIFO. If less than eight values are successfully written to the TX FIFO since the power domain for the SSI module is powered up, then 0 is transmitted. User or software is responsible to make valid data available in the FIFO as needed.
PAGE 1358
Functional Description www.ti.com 20.4.4 Frame Formats Each data frame is between 4 and 16 bits long, depending on the size of data programmed, and is transmitted starting with the most significant bit (MSB). Three basic frame types can be selected: • TI synchronous serial • Motorola SPI • National MICROWIRE For all three formats, the serial clock (SSIn_CLK) is held inactive while the SSI is idle and SSIn_CLK transitions at the programmed frequency only during active transmission or reception of data.
PAGE 1359
Functional Description www.ti.com 20.4.4.2 Motorola SPI Frame Format The Motorola SPI interface is a 4-wire interface where the SSIn_FSS signal behaves as a slave select. The main feature of the Motorola SPI format is that the inactive state and phase of the SSIn_CLK signal can be programmed through the SPO and SPH bits in the [SCR0] control register. 20.4.4.2.1 SPO Clock Polarity Bit When the SPO clock polarity control bit is clear, the bit produces a steady-state low value on the SSIn_CLK pin.
PAGE 1360
Functional Description www.ti.com The data is now captured on the rising edges and propagated on the falling edges of the SSIn_CLK signal. For a single-word transmission after all bits of the data word are transferred, the SSIn_FSS line is returned to its IDLE high state one SSIn_CLK period after the last bit is captured.
PAGE 1361
Functional Description www.ti.com 20.4.4.5 Motorola SPI Frame Format With SPO = 1 and SPH = 0 Figure 20-7 and Figure 20-8 show single and continuous transmission signal sequences, respectively, for Motorola SPI format with SPO = 1 and SPH = 0. Figure 20-7. Motorola SPI Frame Format (Single Transfer) With SPO = 1 and SPH = 0 SSIn_Clk SSIn_Fss SSIn_Rx MSB LSB Q 4 to 16 bits LSB MSB SSIn_Tx Note: Q is undefined. Figure 20-8.
PAGE 1362
Functional Description www.ti.com Figure 20-9. Motorola SPI Frame Format With SPO = 1 and SPH = 1 SSIn_Clk SSIn_Fss SSIn_Rx Q MSB LSB Q 4 to 16 bits MSB SSIn_Tx LSB Note: Q is undefined. In • • • • • this configuration, during idle periods: SSIClk is forced high. SSIn_FSS is forced high. The transmit data line SSIn_TX is arbitrarily forced low. When the SSI is configured as a master, it enables the SSIn_CLK pad. When the SSI is configured as a slave, it disables the SSIn_CLK pad.
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Functional Description www.ti.com Writing a control byte to the TX FIFO triggers a transmission. The falling edge of SSIn_FSS transfers the value in the bottom entry of the TX FIFO to the serial shift register of the transmit logic and shifts the MSB of the 8-bit control frame out onto the SSIn_TX pin. SSIn_FSS remains low for the duration of the frame transmission. The SSIn_RX pin remains 3-stated during this transmission.
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DMA Operation www.ti.com 20.5 DMA Operation The SSI peripheral provides an interface to the μDMA controller with separate channels for transmit and receive. The SSI DMA Control [SSI_DMACR] register allows the μDMA to operate the SSI. When μDMA operation is enabled, the SSI asserts a μDMA request on the receive or transmit channel when the associated FIFO can transfer data. For the receive channel, a single transfer request is asserted whenever any data is in the RX FIFO.
PAGE 1365
Initialization and Configuration www.ti.com 20.6 Initialization and Configuration To enable and initialize the SSI, perform the following steps: 1. Ensure the corresponding power domain is powered up properly. For details, refer to Chapter 6, PRCM. 2.
PAGE 1366
SSI Registers www.ti.com Assuming the system clock is 48 MHz, the bit rate calculation is shown in Equation 6. SSIn_CLK = PERDMACLK / (CPSDVSR × (1 + SCR)) 1 × 106 = 20 × 106 / (CPSDVSR × (1 + SCR))1000000 bps = 48000000 Hz / (2 × (1 + 23)) (6) In this case, if CPSDVSR = 0x2, SCR must be 0x18. The configuration sequence is: 1. Ensure that the SSE bit in the [SSI_CR1] register is clear. 2. Write the [SSI_CR1] register with a value of 0x0000 0000. 3.
PAGE 1367
SSI Registers www.ti.com 20.7.1 SSI Registers Table 20-2 lists the memory-mapped registers for the SSI. All register offset addresses not listed in Table 20-2 should be considered as reserved locations and the register contents should not be modified. Table 20-2. SSI Registers Offset Acronym Register Name 0h CR0 Control 0 Section 20.7.1.1 Section 4h CR1 Control 1 Section 20.7.1.2 8h DR Data Section 20.7.1.3 Ch SR Status Section 20.7.1.4 10h CPSR Clock Prescale Section 20.7.1.
PAGE 1368
SSI Registers www.ti.com 20.7.1.1 CR0 Register (Offset = 0h) [reset = X] CR0 is shown in Figure 20-13 and described in Table 20-3. Control 0 Figure 20-13. CR0 Register 31 30 29 28 27 26 25 15 14 13 12 11 SCR R/W-X 10 9 24 23 RESERVED R-X 8 22 7 6 SPH SPO R/W-X R/W-X 21 20 19 18 17 16 5 4 3 2 1 0 FRF R/W-X DSS R/W-X Table 20-3. CR0 Register Field Descriptions Field Type Reset Description 31-16 Bit RESERVED R X Software should not rely on the value of a reserved.
PAGE 1369
SSI Registers www.ti.com 20.7.1.2 CR1 Register (Offset = 4h) [reset = X] CR1 is shown in Figure 20-14 and described in Table 20-4. Control 1 Figure 20-14. CR1 Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 RESERVED R-X 24 23 RESERVED R-X 8 7 22 21 20 6 5 4 19 18 17 16 3 2 1 0 SOD MS SSE LBM R/W-X R/W-X R/W-X R/W-X Table 20-4. CR1 Register Field Descriptions Bit Field Type Reset Description RESERVED R X Software should not rely on the value of a reserved.
PAGE 1370
SSI Registers www.ti.com 20.7.1.3 DR Register (Offset = 8h) [reset = X] DR is shown in Figure 20-15 and described in Table 20-5. Data 16-bits wide data register: When read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer.
PAGE 1371
SSI Registers www.ti.com 20.7.1.4 SR Register (Offset = Ch) [reset = X] SR is shown in Figure 20-16 and described in Table 20-6. Status Figure 20-16. SR Register 31 30 29 28 27 15 14 13 12 11 26 25 10 9 RESERVED R-X 24 23 RESERVED R-X 8 7 22 21 20 19 18 17 16 6 5 4 BSY R-X 3 RFF R-X 2 RNE R-X 1 TNF R-1h 0 TFE R-1h Table 20-6. SR Register Field Descriptions Bit Field Type Reset Description RESERVED R X Software should not rely on the value of a reserved.
PAGE 1372
SSI Registers www.ti.com 20.7.1.5 CPSR Register (Offset = 10h) [reset = X] CPSR is shown in Figure 20-17 and described in Table 20-7. Clock Prescale Figure 20-17. CPSR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 CPSDVSR R/W-X 1 0 Table 20-7. CPSR Register Field Descriptions Field Type Reset Description 31-8 Bit RESERVED R X Software should not rely on the value of a reserved.
PAGE 1373
SSI Registers www.ti.com 20.7.1.6 IMSC Register (Offset = 14h) [reset = X] IMSC is shown in Figure 20-18 and described in Table 20-8. Interrupt Mask Set and Clear Figure 20-18. IMSC Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 TXIM R/W-X 2 RXIM R/W-X 1 RTIM R/W-X 0 RORIM R/W-X RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 4 RESERVED R-X Table 20-8.
PAGE 1374
SSI Registers www.ti.com 20.7.1.7 RIS Register (Offset = 18h) [reset = X] RIS is shown in Figure 20-19 and described in Table 20-9. Raw Interrupt Status Figure 20-19. RIS Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 TXRIS R-1h 2 RXRIS R-X 1 RTRIS R-X 0 RORRIS R-X RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 4 RESERVED R-X Table 20-9.
PAGE 1375
SSI Registers www.ti.com 20.7.1.8 MIS Register (Offset = 1Ch) [reset = X] MIS is shown in Figure 20-20 and described in Table 20-10. Masked Interrupt Status Figure 20-20. MIS Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 TXMIS R-X 2 RXMIS R-X 1 RTMIS R-X 0 RORMIS R-X RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 4 RESERVED R-X Table 20-10.
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SSI Registers www.ti.com 20.7.1.9 ICR Register (Offset = 20h) [reset = X] ICR is shown in Figure 20-21 and described in Table 20-11. Interrupt Clear On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. Figure 20-21. ICR Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 RTIC W-X 0 RORIC W-X RESERVED W-X 23 22 21 20 RESERVED W-X 15 14 13 12 RESERVED W-X 7 6 5 4 RESERVED W-X Table 20-11.
PAGE 1377
SSI Registers www.ti.com 20.7.1.10 DMACR Register (Offset = 24h) [reset = X] DMACR is shown in Figure 20-22 and described in Table 20-12. DMA Control Figure 20-22. DMACR Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 TXDMAE R/W-X 0 RXDMAE R/W-X RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 4 RESERVED R-X Table 20-12.
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Chapter 21 SWCU117A – February 2015 – Revised March 2015 Inter-Integrated Circuit (I2C) Interface This chapter describes the inter-integrated circuit interface. Topic 21.1 21.2 21.3 21.4 21.5 1378 ........................................................................................................................... Inter-Integrated Circuit Interface ....................................................................... Block Diagram ..................................................................
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Inter-Integrated Circuit Interface www.ti.com 21.1 Inter-Integrated Circuit Interface The I2C bus provides bidirectional data transfer through a 2-wire design (a serial data line [SDA] and a serial clock line [SCL]), and interfaces to external I2C devices such as serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so forth. The I2C bus may also be used for system testing and diagnostic purposes in product development and manufacture.
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Functional Description www.ti.com Figure 21-2. I2C Bus Configuration RPUP RPUP SCL I2C Bus SDA I2CSCL I2CSDA SDA SCL SCL Third-party device with I2C interface CC26xx/CC13xx SDA Third-party device with I2C interface 21.3.1 I2C Bus Functional Overview The I2C bus uses only two signals: SDA and SCL, named I2CSDA and I2CSCL on the CC26xx controller. SDA is the bidirectional serial data line and SCL line is the bidirectional serial clock line. The bus is considered idle when both lines are high.
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Functional Description www.ti.com 21.3.1.2 Data Format With 7-Bit Address Data transfers follow the format shown in Figure 21-4. After the Start condition, a slave address is transmitted. This address is 7 bits long followed by an eighth bit, which is a data direction bit (the R/S bit in the [I2C_MSA] register). If the RS bit is clear, it indicates a transmit operation (send), and if it is set, it indicates a request for data (receive).
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Functional Description www.ti.com 21.3.1.5 Arbitration A master may start a transfer only if the bus is idle. Two or more masters can generate a Start condition within minimum hold time of the Start condition. In these situations, an arbitration scheme occurs on the SDA line, while SCL is high. During arbitration, the first of the competing master devices to place 1 (high) on SDA while another master transmits 0 (low) switches off its data output stage, and retires until the bus is idle again.
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Functional Description www.ti.com • • • • • Master bus time-out Slave transaction received Slave transaction requested Stop condition on bus detected Start condition on bus detected The I2C master and I2C slave modules have separate interrupt signals. While both modules can generate interrupts for multiple conditions, only a single interrupt signal is sent to the interrupt controller (INTC). 21.3.3.
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Functional Description www.ti.com 21.3.5.1 I2C Master Command Sequences Figure 21-7 through Figure 21-12 show the command sequences available for the I2C master. Figure 21-7. Master Single TRANSMIT Idle Write slave address to I2C_MSA Sequence may be omitted in a single master system.
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Functional Description www.ti.com Figure 21-8. Master Single RECEIVE Idle Write slave address to I2C_MSA Sequence may be omitted in a single master system.
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Functional Description www.ti.com Figure 21-9. Master TRANSMIT With Repeated Start Condition Idle Read I2C_MSTAT Write slave address to I2C_MSA Write data to I2C_MDR Sequence may be omitted in a single master system.
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Functional Description www.ti.com Figure 21-10. Master RECEIVE With Repeated Start Condition Idle Read I2C_MSTAT Write slave address to I2C_MSA Sequence may be omitted in a single master system.
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Functional Description www.ti.com Figure 21-11. Master RECEIVE With Repeated Start After TRANSMIT With Repeated Start Condition Idle Mater operates in master transmit mode. Stop condition is not generated. Write slave address to I2C_MSA Write 01011 to I2C_MCTRL Repeated Start condition is generated with changing data direction. Master operates in master receive mode.
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Functional Description www.ti.com Figure 21-12. Master TRANSMIT With Repeated Start After RECEIVE With Repeated Start Condition Idle Mater operates in master receive mode. Stop condition is not generated. Write slave address to I2C_MSA Write 0-011 to I2C_MCTRL Master operates in master transmit mode. Repeated Start condition is generated with changing data direction.
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Functional Description www.ti.com 21.3.5.2 I2C Slave Command Sequences Figure 21-13 shows the command sequence available for the I2C slave. Figure 21-13.
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Initialization and Configuration www.ti.com 21.4 Initialization and Configuration The following example shows how to configure the I2C module to transmit a single byte as a master. This assumes the system clock is 24 MHz. 1.
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I2C Registers www.ti.com 21.5.1 I2C Registers Table 21-2 lists the memory-mapped registers for the I2C. All register offset addresses not listed in Table 21-2 should be considered as reserved locations and the register contents should not be modified. Table 21-2. I2C Registers Offset 1392 Acronym Register Name 0h SOAR Slave Own Address Section 21.5.1.1 Section 4h SSTAT Slave Status Section 21.5.1.2 4h SCTL Slave Control Section 21.5.1.3 8h SDR Slave Data Section 21.5.1.
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I2C Registers www.ti.com 21.5.1.1 SOAR Register (Offset = 0h) [reset = X] SOAR is shown in Figure 21-14 and described in Table 21-3. Slave Own Address This register consists of seven address bits that identify this I2C device on the I2C bus. Figure 21-14. SOAR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 OAR R/W-X 1 0 Table 21-3.
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I2C Registers www.ti.com 21.5.1.2 SSTAT Register (Offset = 4h) [reset = X] SSTAT is shown in Figure 21-15 and described in Table 21-4. Slave Status Internal Note: This register shares address with SCTL, meaning that this register functions as a control register when written, and a status register when read. Figure 21-15.
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I2C Registers www.ti.com 21.5.1.3 SCTL Register (Offset = 4h) [reset = X] SCTL is shown in Figure 21-16 and described in Table 21-5. Slave Control Note: This register shares address with SSTAT, meaning that this register functions as a control register when written, and a status register when read. Figure 21-16. SCTL Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 RESERVED W-X 8 7 RESERVED W-X 22 21 20 19 18 17 16 6 5 4 3 2 1 0 DA W-X Table 21-5.
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I2C Registers www.ti.com 21.5.1.4 SDR Register (Offset = 8h) [reset = X] SDR is shown in Figure 21-17 and described in Table 21-6. Slave Data This register contains the data to be transmitted when in the Slave Transmit state, and the data received when in the Slave Receive state. Figure 21-17. SDR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 DATA R/W-X 2 1 0 Table 21-6.
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I2C Registers www.ti.com 21.5.1.5 SIMR Register (Offset = Ch) [reset = X] SIMR is shown in Figure 21-18 and described in Table 21-7. Slave Interrupt Mask This register controls whether a raw interrupt is promoted to a controller interrupt. Figure 21-18. SIMR Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 STOPIM R/W-X 1 STARTIM R/W-X 0 DATAIM R/W-X RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 RESERVED R-X 4 Table 21-7.
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I2C Registers www.ti.com 21.5.1.6 SRIS Register (Offset = 10h) [reset = X] SRIS is shown in Figure 21-19 and described in Table 21-8. Slave Raw Interrupt Status This register shows the unmasked interrupt status. Figure 21-19. SRIS Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 STOPRIS R-X 1 STARTRIS R-X 0 DATARIS R-X RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 RESERVED R-X 4 Table 21-8.
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I2C Registers www.ti.com 21.5.1.7 SMIS Register (Offset = 14h) [reset = X] SMIS is shown in Figure 21-20 and described in Table 21-9. Slave Masked Interrupt Status This register show which interrupt is active (based on result from SRIS and SIMR). Figure 21-20. SMIS Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 STOPMIS R-X 1 STARTMIS R-X 0 DATAMIS R-X RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 RESERVED R-X 4 Table 21-9.
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I2C Registers www.ti.com 21.5.1.8 SICR Register (Offset = 18h) [reset = X] SICR is shown in Figure 21-21 and described in Table 21-10. Slave Interrupt Clear This register clears the raw interrupt SRIS. Figure 21-21. SICR Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 STOPIC W-X 1 STARTIC W-X 0 DATAIC W-X RESERVED W-X 23 22 21 20 RESERVED W-X 15 14 13 12 RESERVED W-X 7 6 5 RESERVED W-X 4 Table 21-10.
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I2C Registers www.ti.com 21.5.1.9 MSA Register (Offset = 800h) [reset = X] MSA is shown in Figure 21-22 and described in Table 21-11. Master Salve Address This register contains seven address bits of the slave to be accessed by the master (a6-a0), and an RS bit determining if the next operation is a receive or transmit. Figure 21-22.
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I2C Registers www.ti.com 21.5.1.10 MSTAT Register (Offset = 804h) [reset = X] MSTAT is shown in Figure 21-23 and described in Table 21-12. Master Status Figure 21-23. MSTAT Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 DATACK_N R-X 2 ADRACK_N R-X 1 ERR R-X 0 BUSY R-X RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 RESERVED R-X 6 BUSBSY R-X 5 IDLE R-1h 4 ARBLST R-X Table 21-12.
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I2C Registers www.ti.com 21.5.1.11 MCTRL Register (Offset = 804h) [reset = X] MCTRL is shown in Figure 21-24 and described in Table 21-13. Master Control This register accesses status bits when read and control bits when written. When read, the status register indicates the state of the I2C bus controller as stated in MSTAT. When written, the control register configures the I2C controller operation.
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I2C Registers www.ti.com 21.5.1.12 MDR Register (Offset = 808h) [reset = X] MDR is shown in Figure 21-25 and described in Table 21-14. Master Data This register contains the data to be transmitted when in the Master Transmit state and the data received when in the Master Receive state. Figure 21-25. MDR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 DATA R/W-X 2 1 0 Table 21-14.
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I2C Registers www.ti.com 21.5.1.13 MTPR Register (Offset = 80Ch) [reset = X] MTPR is shown in Figure 21-26 and described in Table 21-15. I2C Master Timer Period This register specifies the period of the SCL clock. Figure 21-26. MTPR Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 TPR R/W-1h 2 1 0 RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 TPR_7 R/W-X 6 5 4 Table 21-15.
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I2C Registers www.ti.com 21.5.1.14 MIMR Register (Offset = 810h) [reset = X] MIMR is shown in Figure 21-27 and described in Table 21-16. Master Interrupt Mask This register controls whether a raw interrupt is promoted to a controller interrupt. Figure 21-27. MIMR Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 RESERVED R-X 8 7 RESERVED R-X 22 21 20 19 18 17 16 6 5 4 3 2 1 0 IM R/W-X Table 21-16.
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I2C Registers www.ti.com 21.5.1.15 MRIS Register (Offset = 814h) [reset = X] MRIS is shown in Figure 21-28 and described in Table 21-17. Master Raw Interrupt Status This register show the unmasked interrupt status. Figure 21-28. MRIS Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 RESERVED R-X 8 7 RESERVED R-X 22 21 20 19 18 17 16 6 5 4 3 2 1 0 RIS R-X Table 21-17.
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I2C Registers www.ti.com 21.5.1.16 MMIS Register (Offset = 818h) [reset = X] MMIS is shown in Figure 21-29 and described in Table 21-18. Master Masked Interrupt Status This register show which interrupt is active (based on result from MRIS and MIMR). Figure 21-29. MMIS Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 RESERVED R-X 8 7 RESERVED R-X 22 21 20 19 18 17 16 6 5 4 3 2 1 0 MIS R-X Table 21-18.
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I2C Registers www.ti.com 21.5.1.17 MICR Register (Offset = 81Ch) [reset = X] MICR is shown in Figure 21-30 and described in Table 21-19. Master Interrupt Clear This register clears the raw and masked interrupt. Figure 21-30. MICR Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 24 23 RESERVED W-X 8 7 RESERVED W-X 22 21 20 19 18 17 16 6 5 4 3 2 1 0 IC W-X Table 21-19.
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I2C Registers www.ti.com 21.5.1.18 MCR Register (Offset = 820h) [reset = X] MCR is shown in Figure 21-31 and described in Table 21-20. Master Configuration This register configures the mode (Master or Slave) and sets the interface for test mode loopback. Figure 21-31.
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Chapter 22 SWCU117A – February 2015 – Revised March 2015 Integrated Interchip Sound (I2S) Module This chapter describes the Integrated Interchip Sound (I2S) Module. Topic ........................................................................................................................... 22.1 22.2 22.3 22.4 22.5 22.6 22.7 22.8 22.9 22.10 Introduction ................................................................................................... Digital Audio Interface .........................
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Introduction www.ti.com 22.1 Introduction The CC26xx device features an I2S module that supports the I2S, LJF, RJF, and DSP interface formats. This interface can be used to transfer audio sample streams between CC26xx and external audio devices, such as codecs, DACs, and ADCs. The CC26xx can act as either I2S master or I2S slave. 22.2 Digital Audio Interface The I2S interface consists of the signals shown in Figure 22-1.
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Frame Configuration www.ti.com Figure 22-3. DSP Interface Format Example BCLK WCLK ADx (DSP) LSB MSB LSB MSB MSB Channel 0 Channel 1 LSB Channel 2 All samples produced or to be consumed in a sample period must be transferred within a frame, using one or more data lines. Hence, samples transferred within a frame belong to different audio channels.
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Clock Configuration www.ti.com On the I2S serial interface, data and WCLK is sampled and clocked out on opposite edges of BCLK. The [PRCM:I2SCLKCTL: SMPL_ON_POSEDGE] register sets if the sampling or the clocking of WCLK and data should be done on the positive or negative edge of BCLK. Sample edge and phase mode used by the I2S module is set using the [I2S:AIFFMTCFG] register. The clock signals MCLK, BCLK, and WCLK must be enabled using the [PRCM:I2SCLKCTL:EN] register.
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Serial Interface Formats www.ti.com Figure 22-4. I2S Interface Format WCLK BCLK ADx 0 1 n-1 n-2 3 n-3 MSB 2 1 0 n-1 n-2 n-3 3 2 LSB MSB 1 0 LSB Right channel Left channel WCLK period = 1/Fs 22.6.2 Left Justified (LJF) LJF is a dual-phase format, [I2S:AIFFMTCFG:DUAL_PHASE] = 1, with a 50% WCLK duty cycle and MSB of each sample word aligned with the edge of WCLK ; that is, [I2S:AIFFMTCFG:DATA_DELAY] = 0.
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Serial Interface Formats www.ti.com Figure 22-6. RJF Interface Format WCLK BCLK ADx 0 n-1 n-2 n-3 2 0 1 MSB n-1 n-3 n-2 2 MSB LSB 0 1 LSB Right channel Left channel WCLK period = 1/FS 22.6.4 DSP DSP is a single-phase format, [I2S:AIFFMTCFG:DUAL_PHASE] = 0, where WCLK is high for one BCLK period, followed by each audio channel back-to-back. Data is sampled on the falling edge of BCLK and updated on the rising edge of BCLK; this is configured by setting [I2S: AIFFMTCFG:SMPL_EDGE] = 0.
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Memory Interface www.ti.com 22.7 Memory Interface This section describes the register settings that affect the automated memory interface. The relevant registers are: • [I2S:AIFDIRCFG] • [I2S:AIFDMACFG] • [I2S:AIFFMTCFG] • [I2S:AIFWMASKx] • [I2S:AIFINPTRNEXT] • [I2S:AIFOUTPTRNEXT] There are also two observation registers: • [I2S:AIFINPTR] • [I2S:AIFOUTPTR] 22.7.
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Memory Interface www.ti.com 22.7.3 Memory Buffers and Pointers The memory access functionality operates on blocks of frames. There are separate blocks for input samples and output samples. The number of frames per block is configured in the [I2S:AIFDMACFG:END_FRAME_IDX] register. This is the index of the last frame in the block (that is, the block size minus 1). Writing a nonzero value to the [I2S:AIFDMACFG:END_FRAME_IDX] register enables and initializes the interface.
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Samplestamp Generator www.ti.com 22.8.1 Counters and Registers The samplestamp generator contains two different parts that are based on two counters: 1. STMPXCNT counts XOSC (clock) cycles between positive WCLK edges. The counter value can be read from the [I2S:STMPXCNT] register. 2. STMPWCNT counts positive WCLK edges and modulo the size of the sample ring-buffer. The modulo value is given by the [I2S:STMPWPER] register. The counter value can be read from the [I2S:STMPWCNT] register.
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Samplestamp Generator www.ti.com 22.8.2 Starting Input and Output Pins The [I2S:STMPINTRIG] and [I2S:STMPOUTTRIG] registers contain WCLK counter compare values that are used to start the input and output audio streaming, respectively: • When the WCLK counter value reaches the [I2S:STMPINTRIG] register and the [I2S:STMPCTL:IN_RDY] register is set, the memory interface controller begins storing samples to memory in the next frame: ((STMPINTRIG + 1) % STMPWPER).
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Usage www.ti.com 22.9 Usage This section describes the recommended start-up and termination sequences. 22.9.1 Start-up Sequence The configuration of the I2S module should be carried out in the following order: 1. Set up and configure required ADx and clock pins (set externally in the IOC module). 2. Enable I2S peripheral and configure WCLK and MCLK audio clocks (set externally in the PRCM module). 3.
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Usage www.ti.com 22.9.2 Termination Sequence This termination sequence consists of six steps that ensure the I2S module completes all buffers before closing down I/O pins. If this is not important and the system allows read and write access to NULL, step 1, 2, and step 5 may be ignored. 1. Do not update (or write NULL to) the [I2S:AIFINPTRNEXT] or [I2S:AIFOUTPTRNEXT] registers at memory interface in/out interrupt. 2.
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I2S Registers www.ti.com 22.10.1 I2S Registers Table 22-1 lists the memory-mapped registers for the I2S. All register offset addresses not listed in Table 22-1 should be considered as reserved locations and the register contents should not be modified. Table 22-1. I2S Registers Offset Acronym Register Name 0h AIFWCLKSRC WCLK Source Selection Section 22.10.1.1 Section 4h AIFDMACFG DMA Buffer Size Configuration Section 22.10.1.2 8h AIFDIRCFG Pin Direction Section 22.10.1.
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I2S Registers www.ti.com 22.10.1.1 AIFWCLKSRC Register (Offset = 0h) [reset = X] AIFWCLKSRC is shown in Figure 22-8 and described in Table 22-2. WCLK Source Selection Figure 22-8. AIFWCLKSRC Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 WCLK_INV R/W-X 1 RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 RESERVED R-X 4 0 WCLK_SRC R/W-X Table 22-2.
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I2S Registers www.ti.com 22.10.1.2 AIFDMACFG Register (Offset = 4h) [reset = X] AIFDMACFG is shown in Figure 22-9 and described in Table 22-3. DMA Buffer Size Configuration Figure 22-9. AIFDMACFG Register 31 30 29 28 27 26 25 15 14 13 12 11 RESERVED R-X 10 9 24 23 RESERVED R-X 8 7 22 21 6 5 20 19 4 3 END_FRAME_IDX R/W-X 18 17 16 2 1 0 Table 22-3.
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I2S Registers www.ti.com 22.10.1.3 AIFDIRCFG Register (Offset = 8h) [reset = X] AIFDIRCFG is shown in Figure 22-10 and described in Table 22-4. Pin Direction Figure 22-10. AIFDIRCFG Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 4 RESERVED R-X 8 AD2 R/W-X AD1 R/W-X 3 2 RESERVED R-X 1 0 AD0 R/W-X Table 22-4.
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I2S Registers www.ti.com 22.10.1.4 AIFFMTCFG Register (Offset = Ch) [reset = X] AIFFMTCFG is shown in Figure 22-11 and described in Table 22-5. Serial Interface Format Configuration Figure 22-11. AIFFMTCFG Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 WORD_LEN R/W-10h 1 0 RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 DATA_DELAY R/W-1h 7 MEM_LEN_24 R/W-X 6 SMPL_EDGE R/W-1h 5 DUAL_PHASE R/W-1h 4 Table 22-5.
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I2S Registers www.ti.com 22.10.1.5 AIFWMASK0 Register (Offset = 10h) [reset = X] AIFWMASK0 is shown in Figure 22-12 and described in Table 22-6. Word Selection Bit Mask for Pin 0 Figure 22-12. AIFWMASK0 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R/W-X 9 8 7 6 5 4 3 2 MASK R/W-3h 1 0 Table 22-6. AIFWMASK0 Register Field Descriptions Field Type Reset Description 31-8 Bit RESERVED R/W X Software should not rely on the value of a reserved.
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I2S Registers www.ti.com 22.10.1.6 AIFWMASK1 Register (Offset = 14h) [reset = X] AIFWMASK1 is shown in Figure 22-13 and described in Table 22-7. Word Selection Bit Mask for Pin 1 Figure 22-13. AIFWMASK1 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 MASK R/W-3h 1 0 Table 22-7. AIFWMASK1 Register Field Descriptions Field Type Reset Description 31-8 Bit RESERVED R X Software should not rely on the value of a reserved.
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I2S Registers www.ti.com 22.10.1.7 AIFWMASK2 Register (Offset = 18h) [reset = X] AIFWMASK2 is shown in Figure 22-14 and described in Table 22-8. Word Selection Bit Mask for Pin 2 Figure 22-14. AIFWMASK2 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 5 4 3 2 MASK R/W-3h 1 0 Table 22-8. AIFWMASK2 Register Field Descriptions Field Type Reset Description 31-8 Bit RESERVED R X Software should not rely on the value of a reserved.
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I2S Registers www.ti.com 22.10.1.8 AIFPWMVALUE Register (Offset = 1Ch) [reset = X] AIFPWMVALUE is shown in Figure 22-15 and described in Table 22-9. Audio Interface PWM Debug Value Figure 22-15. AIFPWMVALUE Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 RESERVED PULSE_WIDTH R-X R/W-X 5 4 3 2 1 0 Table 22-9. AIFPWMVALUE Register Field Descriptions Field Type Reset Description 31-16 Bit RESERVED R X Software should not rely on the value of a reserved.
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I2S Registers www.ti.com 22.10.1.9 AIFINPTRNEXT Register (Offset = 20h) [reset = X] AIFINPTRNEXT is shown in Figure 22-16 and described in Table 22-10. DMA Input Buffer Next Pointer Figure 22-16. AIFINPTRNEXT Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PTR R/W-X 9 8 7 6 5 4 3 2 1 0 Table 22-10. AIFINPTRNEXT Register Field Descriptions Bit Field Type Reset Description 31-0 PTR R/W X Pointer to the first byte in the next DMA input buffer.
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I2S Registers www.ti.com 22.10.1.10 AIFINPTR Register (Offset = 24h) [reset = X] AIFINPTR is shown in Figure 22-17 and described in Table 22-11. DMA Input Buffer Current Pointer Figure 22-17. AIFINPTR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PTR R/W-X 9 8 7 6 5 4 3 2 1 0 Table 22-11. AIFINPTR Register Field Descriptions Bit Field Type Reset Description 31-0 PTR R/W X Value of the DMA input buffer pointer currently used by the DMA controller.
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I2S Registers www.ti.com 22.10.1.11 AIFOUTPTRNEXT Register (Offset = 28h) [reset = X] AIFOUTPTRNEXT is shown in Figure 22-18 and described in Table 22-12. DMA Output Buffer Next Pointer Figure 22-18. AIFOUTPTRNEXT Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PTR R/W-X 9 8 7 6 5 4 3 2 1 0 Table 22-12. AIFOUTPTRNEXT Register Field Descriptions Bit Field Type Reset Description 31-0 PTR R/W X Pointer to the first byte in the next DMA output buffer.
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I2S Registers www.ti.com 22.10.1.12 AIFOUTPTR Register (Offset = 2Ch) [reset = X] AIFOUTPTR is shown in Figure 22-19 and described in Table 22-13. DMA Output Buffer Current Pointer Figure 22-19. AIFOUTPTR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PTR R/W-X 9 8 7 6 5 4 3 2 1 0 Table 22-13.
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I2S Registers www.ti.com 22.10.1.13 STMPCTL Register (Offset = 34h) [reset = X] STMPCTL is shown in Figure 22-20 and described in Table 22-14. SampleStaMP Generator Control Register Figure 22-20. STMPCTL Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 OUT_RDY R-X 1 IN_RDY R-X 0 STMP_EN R/W-X RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 RESERVED R-X 4 Table 22-14.
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I2S Registers www.ti.com 22.10.1.14 STMPXCNTCAPT0 Register (Offset = 38h) [reset = X] STMPXCNTCAPT0 is shown in Figure 22-21 and described in Table 22-15. Captured XOSC Counter Value, Capture Channel 0 Figure 22-21. STMPXCNTCAPT0 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 CAPT_VALUE R-X 5 4 3 2 1 0 Table 22-15.
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I2S Registers www.ti.com 22.10.1.15 STMPXPER Register (Offset = 3Ch) [reset = X] STMPXPER is shown in Figure 22-22 and described in Table 22-16. XOSC Period Value Figure 22-22. STMPXPER Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 VALUE R-X 6 5 4 3 2 1 0 Table 22-16. STMPXPER Register Field Descriptions Field Type Reset Description 31-16 Bit RESERVED R X Software should not rely on the value of a reserved.
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I2S Registers www.ti.com 22.10.1.16 STMPWCNTCAPT0 Register (Offset = 40h) [reset = X] STMPWCNTCAPT0 is shown in Figure 22-23 and described in Table 22-17. Captured WCLK Counter Value, Capture Channel 0 Figure 22-23. STMPWCNTCAPT0 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 CAPT_VALUE R-X 5 4 3 2 1 0 Table 22-17.
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I2S Registers www.ti.com 22.10.1.17 STMPWPER Register (Offset = 44h) [reset = X] STMPWPER is shown in Figure 22-24 and described in Table 22-18. WCLK Counter Period Value Figure 22-24. STMPWPER Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 VALUE R/W-X 6 5 4 3 2 1 0 Table 22-18. STMPWPER Register Field Descriptions Field Type Reset Description 31-16 Bit RESERVED R X Software should not rely on the value of a reserved.
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I2S Registers www.ti.com 22.10.1.18 STMPINTRIG Register (Offset = 48h) [reset = X] STMPINTRIG is shown in Figure 22-25 and described in Table 22-19. WCLK Counter Trigger Value for Input Pins Figure 22-25. STMPINTRIG Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 RESERVED IN_START_WCNT R-X R/W-X 4 3 2 1 0 Table 22-19.
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I2S Registers www.ti.com 22.10.1.19 STMPOUTTRIG Register (Offset = 4Ch) [reset = X] STMPOUTTRIG is shown in Figure 22-26 and described in Table 22-20. WCLK Counter Trigger Value for Output Pins Figure 22-26. STMPOUTTRIG Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 RESERVED OUT_START_WCNT R-X R/W-X 4 3 2 1 0 Table 22-20.
PAGE 1443
I2S Registers www.ti.com 22.10.1.20 STMPWSET Register (Offset = 50h) [reset = X] STMPWSET is shown in Figure 22-27 and described in Table 22-21. WCLK Counter Set Operation Figure 22-27. STMPWSET Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 VALUE R/W-X 6 5 4 3 2 1 0 Table 22-21. STMPWSET Register Field Descriptions Field Type Reset Description 31-16 Bit RESERVED R X Software should not rely on the value of a reserved.
PAGE 1444
I2S Registers www.ti.com 22.10.1.21 STMPWADD Register (Offset = 54h) [reset = X] STMPWADD is shown in Figure 22-28 and described in Table 22-22. WCLK Counter Add Operation Figure 22-28. STMPWADD Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 VALUE_INC R/W-X 5 4 3 2 1 0 Table 22-22. STMPWADD Register Field Descriptions Field Type Reset Description 31-16 Bit RESERVED R X Software should not rely on the value of a reserved.
PAGE 1445
I2S Registers www.ti.com 22.10.1.22 STMPXPERMIN Register (Offset = 58h) [reset = X] STMPXPERMIN is shown in Figure 22-29 and described in Table 22-23. XOSC Minimum Period Value Minimum Value of STMPXPER Figure 22-29. STMPXPERMIN Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 VALUE R/W-FFFFh 5 4 3 2 1 0 Table 22-23.
PAGE 1446
I2S Registers www.ti.com 22.10.1.23 STMPWCNT Register (Offset = 5Ch) [reset = X] STMPWCNT is shown in Figure 22-30 and described in Table 22-24. Current Value of WCNT Figure 22-30. STMPWCNT Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 CURR_VALUE R-X 5 4 3 2 1 0 Table 22-24. STMPWCNT Register Field Descriptions Field Type Reset Description 31-16 Bit RESERVED R X Software should not rely on the value of a reserved.
PAGE 1447
I2S Registers www.ti.com 22.10.1.24 STMPXCNT Register (Offset = 60h) [reset = X] STMPXCNT is shown in Figure 22-31 and described in Table 22-25. Current Value of XCNT Figure 22-31. STMPXCNT Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 CURR_VALUE R-X 5 4 3 2 1 0 Table 22-25. STMPXCNT Register Field Descriptions Field Type Reset Description 31-16 Bit RESERVED R X Software should not rely on the value of a reserved.
PAGE 1448
I2S Registers www.ti.com 22.10.1.25 STMPXCNTCAPT1 Register (Offset = 64h) [reset = X] STMPXCNTCAPT1 is shown in Figure 22-32 and described in Table 22-26. Captured XOSC Counter Value, Capture Channel 1 Figure 22-32. STMPXCNTCAPT1 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 CAPT_VALUE R-X 5 4 3 2 1 0 Table 22-26.
PAGE 1449
I2S Registers www.ti.com 22.10.1.26 STMPWCNTCAPT1 Register (Offset = 68h) [reset = X] STMPWCNTCAPT1 is shown in Figure 22-33 and described in Table 22-27. Captured WCLK Counter Value, Capture Channel 1 Figure 22-33. STMPWCNTCAPT1 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED R-X 9 8 7 6 CAPT_VALUE R-X 5 4 3 2 1 0 Table 22-27.
PAGE 1450
I2S Registers www.ti.com 22.10.1.27 IRQMASK Register (Offset = 70h) [reset = X] IRQMASK is shown in Figure 22-34 and described in Table 22-28. Masked Interrupt Status Register Figure 22-34. IRQMASK Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 WCLK_TIMEO UT R/W-X 2 BUS_ERR 1 WCLK_ERR 0 PTR_ERR R/W-X R/W-X R/W-X RESERVED R/W-X 23 22 21 20 RESERVED R/W-X 15 14 13 12 RESERVED R/W-X 7 RESERVED 6 5 AIF_DMA_IN 4 AIF_DMA_OUT R/W-X R/W-X R/W-X Table 22-28.
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I2S Registers www.ti.com 22.10.1.28 IRQFLAGS Register (Offset = 74h) [reset = X] IRQFLAGS is shown in Figure 22-35 and described in Table 22-29. Raw Interrupt Status Register Figure 22-35. IRQFLAGS Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 WCLK_TIMEO UT R-X 2 BUS_ERR 1 WCLK_ERR 0 PTR_ERR R-X R-X R-X RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 RESERVED 6 5 AIF_DMA_IN 4 AIF_DMA_OUT R-X R-X R-X Table 22-29.
PAGE 1452
I2S Registers www.ti.com 22.10.1.29 IRQSET Register (Offset = 78h) [reset = X] IRQSET is shown in Figure 22-36 and described in Table 22-30. Interrupt Set Register Figure 22-36. IRQSET Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 WCLK_TIMEO UT W-X 2 BUS_ERR 1 WCLK_ERR 0 PTR_ERR W-X W-X W-X RESERVED W-X 23 22 21 20 RESERVED W-X 15 14 13 12 RESERVED W-X 7 RESERVED 6 5 AIF_DMA_IN 4 AIF_DMA_OUT W-X W-X W-X Table 22-30.
PAGE 1453
I2S Registers www.ti.com 22.10.1.30 IRQCLR Register (Offset = 7Ch) [reset = X] IRQCLR is shown in Figure 22-37 and described in Table 22-31. Interrupt Clear Register Figure 22-37. IRQCLR Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 WCLK_TIMEO UT W-X 2 BUS_ERR 1 WCLK_ERR 0 PTR_ERR W-X W-X W-X RESERVED W-X 23 22 21 20 RESERVED W-X 15 14 13 12 RESERVED W-X 7 RESERVED 6 5 AIF_DMA_IN 4 AIF_DMA_OUT W-X W-X W-X Table 22-31.
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Chapter 23 SWCU117A – February 2015 – Revised March 2015 Radio The CC26xx radio offers a wide variety of different operational modes, covering many different packet formats and supporting data rates up to 5 Mbps. The radio firmware executes from the CC26xx radio domain on an ARM® Cortex-M0™ processor, which can provide extensive baseband automation.
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RF Core www.ti.com 23.1 RF Core The RF core contains an ARM Cortex-M0 that interfaces the analog RF and base-band circuitries, handles data to and from the system side, and assembles the information bits in a given packet structure. The RF core offers a high-level, command-based API to the system CPU (ARM Cortex-M3). The RF core can autonomously handle the time-critical aspects of the radio protocols (802.15.
PAGE 1456
Radio Doorbell www.ti.com Each of the blocks illustrated in Figure 23-1 performs the following functions: System Side • System CPU: Main system processor which runs the user's application, together with the high level protocol stack (for a number of supported configurations) and eventually some higher-level MAC features for some protocols. The system CPU runs code from the boot ROM and the system flash.
PAGE 1457
Radio Doorbell www.ti.com Figure 23-2. Hardware Support for the HAL Radio Doorbell 4 Event Fabric IRQs to System CPU Wake Up IRQ Controller CMDSTA CMDR System RAM System CPU Radio RAM Radio CPU 1 IRQs to Radio CPU L 1 L 2 23.2.1 Operational Description In general, events are signaled on physical lines by a change of the corresponding line from low to high. Interrupts to the system side are edge interrupts, so the line remains high until the relevant interrupt flags have been cleared.
PAGE 1458
RF Core HAL www.ti.com 23.3.2.1 Commands The radio CPU lets the user run a set of high-level primitives or commands from the system CPU. After a command has been issued through the [CMDR] register, the radio CPU examines it and decides a course of action. There are three classes of commands issued: • Radio operation command • Immediate command • Direct command For the first two classes of commands, [CMDR] contains a pointer to a command structure in the radio RAM.
PAGE 1459
RF Core HAL www.ti.com A radio operation command will cause the radio hardware to be accessed. Radio operation commands can do operations such as transmitting or receiving a packet, setting up radio hardware registers, or doing more complex, protocol-dependent operations. A radio operation command can normally only be issued while the radio is idle. An immediate command is a command to change or request status of the radio, or for manipulating TX or RX data queues.
PAGE 1460
RF Core HAL www.ti.com Table 23-1. Values of Result Byte in CMDSTA Register (continued) Value Name Description 0x88 QueueError An operation on a data entry queue was attempted that was not supported by the queue in its current state. 0x89 QueueBusy An operation on a data entry was attempted while that entry was busy. In addition to the command status register, each radio operation command contains a status field (see Table 23-8) . This field may have values in the following categories.
PAGE 1461
RF Core HAL www.ti.com When the system CPU prepares a command structure, the CPU must initialize the status field to Idle. Commands may be set up in a loop. If so, the system CPU must not modify command structures until the radio CPU becomes idle (the system CPU receives a LAST_COMMAND_DONE interrupt; see Section 23.3.2.3, Interrupts), even if the status is Finished or Skipped. 23.3.2.
PAGE 1462
RF Core HAL www.ti.com 23.3.2.5.1 Triggers Triggers can be used to set up a start time, or for other specific purposes in specific radio operation commands. A common trigger byte definition exists, defined in Table 23-3. Table 23-3. Format of Trigger Definition Byte Bit Field Description 0–3 triggerType The type of trigger 4 bEnaCmd 0: No alternative trigger command.
PAGE 1463
RF Core HAL www.ti.com Relative timing can either be relative to time of submitting the command chain, the start of the command, to the start of the previous or first command, or to certain observed events inside the command, to be defined for each command. The following rules apply: • For the first command in a chain, if the start trigger is any of the types 5 through 9, the start is immediate.
PAGE 1464
RF Core HAL www.ti.com Table 23-7.
PAGE 1465
RF Core HAL www.ti.com 23.3.2.6.1 Radio Operation Command Structure Table 23-8 shows the command structure for radio operation commands. Some commands have additional fields appended after this. Table 23-8. Radio Operation Command Format Bytes Field Name 0–1 commandNo Bits Bit Field Name Type Description W The command ID number 2–3 status R/W An integer telling the status of the command. This value is updated by the radio CPU during operation and may be read by the system CPU at any time.
PAGE 1466
RF Core HAL www.ti.com 23.3.2.7.2 Data Entry A data entry queue contains data entries of the type shown in Table 23-10. These entries are organized in a linked list. The first entry of the queue is pointed to by the pCurrEntry field of the queue structure (see Table 23-9). Each pNextEntry field points to the next entry. The last entry in the queue is also pointed to by the pLastEntry field of the queue structure. Table 23-10.
PAGE 1467
RF Core HAL www.ti.com The status field may take the following values: • 0: Pending: The entry is not yet in use by the radio CPU. This is the status to write by the system CPU prior to submitting the entry. • 1: Active: The entry is the entry in the queue currently open for writing (RX) or reading (TX) by the radio CPU. • 2: Busy: An ongoing radio operation is writing or reading an unfinished packet. Certain operations are not allowed while an entry is in this state (see Section 23.3.
PAGE 1468
RF Core HAL www.ti.com An RX entry that is in the Active or Busy state may be read by the system CPU, but cannot be freed or written to, except for data already committed by the radio CPU (in other words, finished). The system CPU may read and modify the data in the RXData buffer up to nextIndex-1, while these bytes are not modified by the radio CPU. When the radio CPU changes the status of the entry from Pending to Busy, it initializes numElements and nextIndex to 0.
PAGE 1469
RF Core HAL www.ti.com Table 23-13. End of Radio Operation Commands Condition Status Code Result Finished operation DONE_OK True Received CMD_STOP while waiting for start trigger DONE_STOPPED False Received CMD_ABORT DONE_ABORT Abort The start trigger occurred in the past with startTrigger.
PAGE 1470
RF Core HAL www.ti.com Table 23-14.
PAGE 1471
RF Core HAL www.ti.com Table 23-15. Format of a Hardware Register Override Entry Bit Index Bit Field Name Description 0–1 entryType 00: Hardware register 01: Array initiator, see Table 23-16 10: ADI register, see Table 23-17, or MCE/RFE override 11: Firmware defined parameter, see Table 23-18 2–15 hwAddr Bits 2–15 of the address to the hardware register. Bits 0–1 of the address are 0. 16–31 value The value to write to the register Table 23-16.
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RF Core HAL www.ti.com Table 23-19.
PAGE 1473
RF Core HAL www.ti.com For hardware registers, bits 2–15 give the address of the hardware register to access, see Table 23-15. The register will be written with a 32-bit write operation, but the 16 most significant bits are always written as 0, while the 16 least significant bits are as given by value. To write a full 32-bit hardware register, use an array operation of length 1. An array initiator signals that the next words must be written to consecutive addresses, see Table 23-16.
PAGE 1474
RF Core HAL www.ti.com 23.3.3.1.3 CMD_FS_POWERUP: Power-Up Frequency Synthesizer Command ID number: 0x080C CMD_FS_POWERUP is a radio operation command. In addition to the parameters listed in Table 23-8, the command structure contains the fields listed in Table 23-22. On start, the radio CPU powers up the frequency synthesizer and applies the register modifications given in pRegOverride. If pRegOverride is NULL, no registers are overridden.
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RF Core HAL www.ti.com The synthesizer is set up in Rx mode or Tx mode, depending on synthConf.bTxMode. This mode may be changed by radio operation commands when setting up Rx or Tx. If synthConf.refFreq is nonzero, a reference frequency of 24 MHz/synthConf.refFreq is used instead of the default one. If the synthesizer is programmed and reports loss of lock after having been in lock, the radio CPU raises the Synth_No_Lock interrupt.
PAGE 1476
RF Core HAL www.ti.com A trigger to end the operation is set up by endTrigger and endTime (see Section 23.3.2.5.1, Triggers). If the trigger that is defined by this parameter occurs, the radio operation ends. The operation ends by one of the causes listed in Table 23-13. The command structure for CMD_RX_TEST contains the fields listed in Table 23-24. Table 23-24.
PAGE 1477
RF Core HAL www.ti.com The transmitter runs until the trigger set up by endTrigger and endTime (see Section 23.3.2.5.1, Triggers) occurs, or until an abort command is issued. If pktConfig.bFsOn is 1, the synthesizer is turned off (corresponding to CMD_FS_OFF; see Section 23.3.3.1.6, CMD_FS_OFF: Turn Off Frequency Synthesizer) after the operation is done; otherwise it is left on. The operation ends by one of the causes listed in Table 23-24.
PAGE 1478
RF Core HAL www.ti.com Table 23-27. CMD_SYNC_START_RAT Command Format Bytes Field Name Bits Bit Field Name Type Description 14–15 Unused 16–19 The desired RAT timer value corresponding to the value the RAT would have had when the RTC was zero.
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RF Core HAL www.ti.com Table 23-30. CMD_SCH_IMM Command Format Bytes Field Name Bits Bit Field Name Type Description 14–15 Reserved 16–19 cmdrVal W Value as would be written to CMDR 20–23 cmdstaVal R Value as would be returned in CMDSTA On start, the radio CPU takes the value in cmdrVal and processes it as if it had been written to CMDR. This command may be a pointer to an immediate command, or it may form a direct command as shown in Figure 23-4.
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RF Core HAL www.ti.com Table 23-33. Additional End Causes for CMD_COUNT_BRANCH Condition Status Code Result Finished operation with counter = 0 when being started DONE_OK TRUE Finished operation with counter > 0 after decrementing DONE_OK TRUE Finished operation with counter = 0 after decrementing DONE_COUNTDO FALSE WN 23.3.3.1.14 CMD_PATTERN_CHECK: Check a Value in Memory Against a Pattern Command ID number: 0x0813 CMD_PATTERN_CHECK is a radio operation command.
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RF Core HAL www.ti.com Table 23-35. Additional end causes for CMD_PATTERN_CHECK Condition Status code Result Comparison result was true DONE_OK TRUE Comparison result was false DONE_FAILED FALSE Command run with patternOpt.bRxVal when no RX data is fully received or partial read RX buffer is being used ERROR_NO_RX Abort 23.3.4 Protocol-Independent Direct and Immediate Commands This section contains immediate commands that can be used across protocols.
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RF Core HAL www.ti.com 23.3.4.3 CMD_GET_RSSI: Read RSSI Command Command ID number: 0x0403 CMD_GET_RSSI is an immediate command that takes no parameters, and can thus be used as a direct command. On reception, the radio CPU reads the RSSI from an underlying receiver. The RSSI is returned in result byte 2 (bit 23:16) of CMDSTA, see Figure 23-5. The RSSI is given on signed form in dBm. If no RSSI is available, this is signaled with a special value of the RSSI (−128, or 0x80).
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RF Core HAL www.ti.com 23.3.4.6 CMD_GET_FW_INFO: Request Information on the Firmware Being Run Command ID number: 0x0002 CMD_GET_FW_INFO is an immediate command that takes the parameters listed in Table 23-38. Table 23-38.
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RF Core HAL www.ti.com On reception, the radio CPU sets the RAT channel given by ratCh in compare mode, and sets the channel compare time to compareTime, which also arms the channel. A channel event occurs at the given time, and this can be enabled as an RF HW interrupt to the system CPU through the RFC_DBELL module. The channel number must indicate a channel that is not reserved for use by the radio CPU. Otherwise, the radio CPU returns ParError in CMDSTA.
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RF Core HAL www.ti.com On reception, the radio CPU disables the RAT channel given by ratCh. This disables previous configurations of that channel done by CMD_SET_RAT_CMP or CMD_SET_RAT_CPT. CMD_DISABLE_RAT_CH may be sent as a direct command. If so, ratCh is given by the parameter in bits 8–15 of CMDR. The channel number must indicate a channel that is not reserved for use by the radio CPU. Otherwise, the radio CPU returns ParError in CMDSTA.
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RF Core HAL www.ti.com 23.3.4.14 CMD_DISARM_RAT_CH: Disarm RAT Channel Command ID number: 0x040A CMD_DISARM_RAT_CH is an immediate command that takes the parameters listed in Table 23-44. Table 23-44. CMD_DISARM_RAT_CH Command Format Bytes Field Name Type Description 0–1 commandNo Bits Bit Field Name W The command ID number 2 ratCh W The radio timer channel number On reception, the radio CPU disarms the RAT channel given by ratCh. CMD_DISABLE_RAT_CH may be sent as a direct command.
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RF Core HAL www.ti.com Table 23-46. CMD_UPDATE_FS Command Format Bytes Field Name Type Description 0–1 commandNo Bits Bit Field Name W The command ID number 2–3 frequency W The frequency in MHz to tune to 4–5 fractFreq W Fractional part of the frequency to tune to On reception, the radio CPU programs a new frequency in the synthesizer without restarting calibration.
PAGE 1488
RF Core HAL www.ti.com Table 23-48. CMD_ADD_DATA_ENTRY Command Format Bytes Field Name 0–1 commandNo Bits Bit Field Name Type Description W The command ID number 2–3 Reserved 4–7 pQueue W Pointer to the queue structure to which the entry will be added 8–11 pEntry W Pointer to the entry On reception, the radio CPU appends the provided data entry to the queue indicated.
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RF Core HAL www.ti.com On reception, the radio CPU flushes the queue indicated, and returns a pointer to the first entry that was removed. The radio CPU performs the following operations: Set pFirstEntry = pQueue->pCurrEntry Set pQueue->pCurrEntry = NULL Set pQueue->pLastEntry = NULL If the pointer pQueue is invalid, the command fails, and the radio CPU sets the result byte of CMDSTA to ParError.
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RF Core HAL www.ti.com Set pQueue->pLastEntry = NULL else Set pFirstEntry = pQueue->pCurrEntry->pNextEntry Set pQueue->pCurrEntry->pNextEntry = NULL Set pQueue->pLastEntry = pQueue->pCurrEntry If the pointer pQueue is invalid, the command fails, and the radio CPU sets the result byte of CMDSTA to ParError. If the queue specified in pQueue is empty, the radio CPU will not need to do any operation, but this is still viewed as a success. The returned pFirstEntry is NULL in this case.
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Data Queue Usage www.ti.com 23.4 Data Queue Usage This section describes how the radio CPU uses data queues. 23.4.1 Operations on Data Queues Only Available for Internal Radio CPU Operations Section 23.3.5, Immediate Commands for Data Queue Manipulation, lists commands used for data queue manipulation. For internal radio CPU operations described, additional operations are available. These operations are described in the following sections. 23.4.1.
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Data Queue Usage www.ti.com 23.4.1.4 PROC_ALLOCATE_RX: Allocate RX Buffer for Storing Data • Pointer to queue, pQueue • Size of entry element to store, size The procedure returns the following: • Pointer to data entry where data is stored, pEntry • Pointer to a finished data entry, or NULL if not finished; pFinishedEntry The procedure returns with error if the first entry of the queue is already busy.
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Data Queue Usage www.ti.com 23.4.1.5 PROC_FINISH_RX: Commit Received Data to RX Data Entry The procedure takes the following input parameters: • Pointer to queue, pQueue • Size of entry element that has been stored, size The procedure returns the following: • Pointer to data entry where data is stored, pEntry • Pointer to a finished data entry, or NULL if not finished; pFinishedEntry The procedure returns with error if the queue is empty or if there is not room for an entry element of the specified size.
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IEEE 802.15.4 www.ti.com 23.5 IEEE 802.15.4 This section describes IEEE 802.15.4-specific command structure, interrupts, data handling, radio operation commands, and immediate commands. 23.5.1 IEEE 802.15.4 Commands The IEEE 802.15.4 specific radio operation commands are defined in Table 23-53 and Table 23-54. Table 23-53. IEEE 802.15.
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IEEE 802.15.4 www.ti.com Table 23-56. IEEE 802.15.
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IEEE 802.15.4 www.ti.com Table 23-58. IEEE 802.15.4 CSMA-CA Command Structure (continued) Bytes Field Name 20 Bits Bit Field Name Type Description BE R/W The BE parameter from the IEEE 802.15.
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IEEE 802.15.4 www.ti.com Table 23-63. IEEE 802.15.4 Modify Frame Filtering Immediate Command Structure Bytes Field Name Type Description 0–1 commandNo W The command number 2–3 newFrameFiltOpt W New value of frameFiltOpt for the running background level operation 4 newFrameTypes W New value of frameTypes for the running background level operation Table 23-64. IEEE 802.15.
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IEEE 802.15.4 www.ti.com Table 23-66. RX Command (continued) Bytes Field Name Type Description 6 nRxOk R/W Number of received frames with CRC error 7 nRxIgnored R/W Number of frames received that are to be ignored 8 nRxBufFull R/W Number of received frames discarded because the RX buffer was full 9 lastRssi R RSSI of last received frame 10 maxRssi R Highest RSSI observed in the operation beaconTimeStamp R 11 12–15 Reserved Time stamp of last received beacon frame 23.5.1.
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IEEE 802.15.4 www.ti.com Table 23-69. Frame Filtering Configuration Bit Field (continued) Bits Bit Field Name Description 4 autoPendEn 0: Auto-pend disabled. 1: Auto-pend enabled 5 defaultPend The value of the pending data bit in auto ACK packets that are not subject to auto-pend 6 bPendDataReqOnly 0: Use auto-pend for any packet. 1: Use auto-pend for data request packets only 7 bPanCoord 0: Device is not PAN coordinator.
PAGE 1500
IEEE 802.15.4 www.ti.com Table 23-72. Extended Address List Structure Bytes Field Name Type Description 0–4K−1 srcMatchEn R/W Words with enable bits for each extAddrEntry; LSB of first word corresponds to entry 0. The array size K = ceil(N/32), where N is the number of entries (given by numExtEntries, see Table 23-56) and ceil denotes rounding upwards 4K–8K−1 srcPendEn R/W Words with pending data bits for each extAddrEntry; LSB of first word corresponds to entry 0.
PAGE 1501
IEEE 802.15.4 www.ti.com 23.5.2 Interrupts The interrupts to be used by the IEEE 802.15.4 commands are listed in Table 23-75. Each interrupt may be enabled individually in the system CPU. Details for when the interrupts are generated are given in Section 23.5.4, Radio Operation Commands. Table 23-75. Interrupt Definitions Applicable to IEEE 802.15.4 Interrupt Number Interrupt Name Description 0 COMMAND_DONE A background level radio operation command has finished.
PAGE 1502
IEEE 802.15.4 www.ti.com Figure 23-6. RX Queue Entry Element (Stapled Fields are Optional) 0±2 bytes Element length 0 or 1 byte PHY header 0±125 bytes MAC header and payload 0 or 2 bytes 0 or 1 byte MAC footer RSSI (FCS) 0 or 1 byte Status 0 or 1 byte Source index 0 or 4 bytes Time stamp 23.5.3.2 Transmit Buffers In the transmit operation, a pointer to a buffer containing the payload is given by pPayload. The length of this buffer is given separately by payloadLen.
PAGE 1503
IEEE 802.15.4 www.ti.com A non-15.4 radio operation may not be run simultaneously with a 15.4 radio operation; if a non-15.4 radio operation is entered while a 15.4 operation is running on either level, scheduling error occurs. Chains of 15.4 and non-15.4 operations can be created, however. When a foreground-level operation finishes, an FG_COMMAND_DONE interrupt is raised. If the command was the last one in a chain, a LAST_FG_COMMAND_DONE interrupt is raised as well (refer to Table 23-75).
PAGE 1504
IEEE 802.15.4 www.ti.com When the demodulator obtains sync on a frame, the PHY header is read first. The 7 least significant bits of this byte give the frame length. The further treatment depends on the setting of frameFiltOpt. If frameFiltOpt.frameFiltEn is 1, further frame filtering is done as explained below. If it is 0, no frame filtering is done. The number of bytes given by the received PHY header are received and stored in the receive queue given by pRXQ.
PAGE 1505
IEEE 802.15.4 www.ti.com 23.5.4.1.1.2 Source Matching Source matching is performed on frames accepted by the frame filtering with a source address present. If the source address was an extended address, the received address is compared against the entries in the list pExtEntryList. If the source address was a short address, the received address and source pan ID are compared against the entries in the list pShortEntryList.
PAGE 1506
IEEE 802.15.4 www.ti.com When a frame has been received, the RSSI observed while receiving the frame is written to pOutput>lastRssi. If the frame was a beacon frame accepted by the frame filtering and with CRC OK, the timestamp at the beginning of the frame is written to pOutput ->beaconTimeStamp. If the timestamp is appended to the RX entry element, see Section 23.6.3.1, Receive Buffers, these two timestamps are the same for a beacon frame.
PAGE 1507
IEEE 802.15.4 www.ti.com If a transmit operation is started in the foreground, the receive operation is suspended. The receiver stops as when aborted, but the synthesizer is left on to the extent possible when switching to transmit mode. When the receiver has stopped, the status field of the command structure is set to IEEE_SUSPENDED. When the transmit command is done, the receiver restarts and the status field of the command structure is set back to RUNNING. Table 23-79.
PAGE 1508
IEEE 802.15.4 • • • www.ti.
PAGE 1509
IEEE 802.15.4 www.ti.com After this wait time, the radio CPU checks the CCA state from the background-level operation, as in Section 23.5.4.1.5, CCA Monitoring. If the CCA state was Invalid, the radio CPU waits before trying again. If csmaConfig.bSlotted = 1, the wait is for one backoff period, otherwise it waits until an RSSI result is available. If the CCA state was Idle, the radio CPU decrements CW by 1, and if this results in a value of zero, the CSMA-CA operation ends with success.
PAGE 1510
IEEE 802.15.4 www.ti.com Figure 23-7.
PAGE 1511
IEEE 802.15.4 www.ti.com For operation according to IEEE 802.15.4, the parameters must be initialized as follows before starting a new CSMA-CA operation: • randomState must be set to a random value • csmaConfig.initCW must be set to 2 for slotted CSMA-CA and 1 for unslotted CSMA-CA • csmaConfig.
PAGE 1512
IEEE 802.15.4 www.ti.com CMD_IEEE_ABORT_FG, and CMD_IEEE_STOP_FG. If CMD_ABORT or CMD_IEEE_ABORT_FG is received, the transmission shall end as soon as possible, in the middle of the packet. If CMD_STOP or CMD_IEEE_STOP_BG is received while the radio CPU is waiting for the start trigger, the operation ends without any transmission; otherwise, the transmission is finished, but the end status and result differ as explained below.
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IEEE 802.15.4 www.ti.com Table 23-82.
PAGE 1514
IEEE 802.15.4 www.ti.com If CMD_ABORT, CMD_IEEE_ABORT_FG, CMD_STOP, or CMD_IEEE_STOP_FG is received while waiting for the start trigger, the operation ends without doing any setup. If CMD_STOP or CMD_IEEE_STOP_FG is received after the start trigger, setup proceeds until finished. If CMD_ABORT or CMD_IEEEE_ABORT_FG is received after the start trigger, the setup process aborts. This leaves the registers in an incomplete state.
PAGE 1515
Bluetooth Low Energy www.ti.com performed. The system CPU may modify the address of a disabled entry, but not an enabled one. If the command is issued without an active or suspended background-level RX operation, the radio CPU returns the result ContextError in CMDSTA. If any of the parameters entered are illegal, for example, pointing to a non-existing entry, the radio CPU returns the result ParError in CMDSTA. Otherwise, the radio CPU returns Done. 23.5.5.
PAGE 1516
Bluetooth Low Energy www.ti.com Table 23-85.
PAGE 1517
Bluetooth Low Energy www.ti.com Table 23-88. Update Advertising Payload Command Bytes Field Name Type Description 0–1 commandNo W The command number 2 payloadType W 0: Advertising data 1: Scan response data 3 newLen W Length of the new payload 4–7 pNewData W Pointer to the buffer containing the new data 8–11 pParams W Pointer to the parameter structure to update 23.6.1.2 Parameter Structures Table 23-89.
PAGE 1518
Bluetooth Low Energy www.ti.com Table 23-91.
PAGE 1519
Bluetooth Low Energy www.ti.com Table 23-92. Scanner Command (continued) Bytes Field Name Bits Bit Field Name Type Description 24–25 Reserved 26 timeoutTrigger W Trigger that causes the device to stop receiving as soon as allowed 27 endTrigger W Trigger that causes the device to stop receiving as soon as allowed 28–31 timeoutTime W Time parameter for timeoutTrigger 32–35 endTime W Time parameter for endTrigger Table 23-93.
PAGE 1520
Bluetooth Low Energy www.ti.com Table 23-94. Generic RX Command (continued) Bytes Field Name Type Description 8–11 accessAddress W Access address used on the connection 12–14 crcInit W CRC initialization value used on the connection 15 endTrigger W Trigger that causes the device to end the RX operation 16–19 endTime W Time parameter for endTrigger Table 23-95.
PAGE 1521
Bluetooth Low Energy www.ti.com Table 23-96.
PAGE 1522
Bluetooth Low Energy www.ti.com Table 23-99.
PAGE 1523
Bluetooth Low Energy www.ti.com Table 23-103. Sequence Number Status Bit Field (continued) Bits Bit Field Name Description 5 bLlCtrlTx 1 if the last transmitted packet was an LL control packet (LLID = 11) 6 bLlCtrlAckRx 1 if the last received packet was the ACK of an LL control packet 7 bLlCtrlAckPending 1 if the last successfully received packet was an LL control packet which has not yet been ACK’ed Table 23-104.
PAGE 1524
Bluetooth Low Energy www.ti.com Table 23-106. Master and Slave Packet Status Byte (continued) Bits Bit Field Name Description 4 bLastCtrl 1 if the last received packet with CRC OK was empty; 0 otherwise 5 bLastMd 1 if the last received packet with CRC OK had MD = 1; 0 otherwise 6 bLastAck 1 if the last received packet with CRC OK was an ACK of a transmitted packet; 0 otherwise 7 Reserved 23.6.2 Interrupts The radio CPU signals events back to the system CPU, using firmware-defined interrupts.
PAGE 1525
Bluetooth Low Energy www.ti.com 23.6.3.1 Receive Buffers A packet being received is stored in a receive buffer. First, a length byte or word is stored, if configured in the RX entry, by config.lenSz. This word is calculated from the length received over the air and the configuration of appended information. Following the optional length field, the received header and payload is stored as received over the air. If RXConfig.
PAGE 1526
Bluetooth Low Energy www.ti.com The whitening parameter indicates the initialization of the 7-bit LFSR used for data whitening in BLE. If whitening.bOverride is 0 and the channel is in the range 0–39, the LFSR initializes with (0x40 | channel). Otherwise, the LFSR initializes with whitening.init. If whitening.init is 0 in this case, no whitening is used. All packets transmitted using BLE radio operation commands have a BLE-compliant CRC appended.
PAGE 1527
Bluetooth Low Energy www.ti.com Table 23-108. BLE Radio Operation Status Codes (continued) Number Name Description 0x1802 BLE_ERROR_NO_SETUP Radio was not set up in BLE mode 0x1803 BLE_ERROR_NO_FS Synth was not programmed when running RX or TX 0x1804 BLE_ERROR_SYNTH_PROG Synth programming failed 0x1805 BLE_ERROR_RXOVF RX overflow observed during operation 0x1806 BLE_ERROR_TXUNF TX underflow observed during operation The conditions for giving each status are listed for each operation.
PAGE 1528
Bluetooth Low Energy www.ti.com Table 23-110.
PAGE 1529
Bluetooth Low Energy www.ti.com • • • – Otherwise, nNack is decremented. – If pParams ->seqStat.nextTXSn was updated and became different from pParams>seqStat.lastTXSn after reception of a packet, and pParams->seqStat.bAutoEmpty = 0, the current TX queue entry is finished and the next one is set as active, and a TX_ENTRY_DONE interrupt is raised. If pParams->seqStat.bLlCtrlTX = 1, an TX_CTRL_ACK interrupt is raised and pParams>seqStat.bLlCtrlAckRX set to 1. – If pParams->seqStat.
PAGE 1530
Bluetooth Low Energy www.ti.com 23.6.4.2 Slave Command A slave radio operation is started by a CMD_BLE_SLAVE command. In the command structure, it has a pParams parameter of the type defined in Table 23-89, and a pOutput parameter of the type defined in Table 23-96. The operation starts with reception. The parameters pParams->timeoutTrigger and pParams>timeoutTime define the time to end the operation if no sync is found by the demodulator.
PAGE 1531
Bluetooth Low Energy www.ti.com A master operation ends due to one of the causes listed in Table 23-112. The status field of the command structure after the operation is ended indicates the reason why the operation ended. In all cases, a COMMAND_DONE interrupt is raised. In each case, it is indicated if the result is True, False, or Abort, which decides the next action. Table 23-112.
PAGE 1532
Bluetooth Low Energy www.ti.com Table 23-113. PDU Types for Different Advertiser Commands Command Type of Advertising Packet Value of PDU Type Bits in Header CMD_BLE_ADV ADV_IND 0000b CMD_BLE_ADV_DIR ADV_DIRECT_IND 0001b CMD_BLE_ADV_NC ADV_NONCONN_IND 0010b CMD_BLE_ADV_SCAN ADV_SCAN_IND 0110b Except when an advertiser is not connectable, the receiver starts after the ADV*_IND packet has been transmitted.
PAGE 1533
Bluetooth Low Energy www.ti.com Table 23-115.
PAGE 1534
Bluetooth Low Energy www.ti.com 23.6.4.4.1 Connectable Undirected-Advertiser Command A connectable undirected-advertiser operation is started by a CMD_BLE_ADV command. In the command structure, it has a pParams parameter of the type defined in Table 23-91, and a pOutput parameter of the type defined in Table 23-97. The operation starts with transmission and operates as described in Section 23.6.4.4, Advertiser.
PAGE 1535
Bluetooth Low Energy www.ti.com Table 23-117.
PAGE 1536
Bluetooth Low Energy www.ti.com Table 23-119.
PAGE 1537
Bluetooth Low Energy www.ti.com Table 23-120.
PAGE 1538
Bluetooth Low Energy www.ti.com After a SCAN_REQ message is transmitted, the radio CPU configures the receiver and looks for a SCAN_RSP from the advertiser to which the SCAN_REQ was sent. If sync is obtained on the demodulator, the header is checked once it is received, and if it is not a SCAN_RSP message, the demodulator is stopped immediately. If it is a SCAN_RSP message, then it is received into the RX queue.
PAGE 1539
Bluetooth Low Energy www.ti.com Two triggers to end the operation are set up by pParams->endTrigger/pParams->endTime and pParams>timeoutTrigger/pParams->timeoutTime, respectively. If either of these triggers occurs, the radio operation ends as soon as possible. If these triggers occur while waiting for sync on an ADV*_IND packet, the operation ends immediately. If they occur at another time, the operation continues until the scan would otherwise be resumed, and then ends.
PAGE 1540
Bluetooth Low Energy www.ti.com Table 23-124.
PAGE 1541
Bluetooth Low Energy www.ti.com Table 23-125. Actions on Received Packets by Initiator (continued) PDU Type CRC Result AdvA Match InitA Match Action Number ADV_DIRECT_IND NOK X X 3 ADV*_IND with invalid length X X X 4 Other X N/A N/A 4 Table 23-126.
PAGE 1542
Bluetooth Low Energy www.ti.com The output structure pOutput contains fields which give information on the command being run. The radio CPU does not initialize the fields, so this must be done by the system CPU when a reset of the counters is desired. The fields are updated by the radio CPU as described below. The list also indicates when interrupts are raised in the system CPU. • If a CONNECT_REQ packet has been transmitted, nTXConnectReq is incremented and a TX_DONE interrupt is raised.
PAGE 1543
Bluetooth Low Energy www.ti.com In a generic receiver operation, the only assumption made on the packet format is that the 6 least significant bits of the second received byte is a length field which indicates the length of the payload following that byte, and that a standard BLE-type CRC is appended to the packet. When tuned to the correct channel, the radio CPU starts listening for a packet. If sync is obtained on the demodulator, the message is received into the RX queue (if any).
PAGE 1544
Bluetooth Low Energy www.ti.com Table 23-128. End of Generic RX Operation (continued) Condition Status Code Result No space in RX buffer to store received packet BLE_ERROR_RXBUF False Illegal value of channel BLE_ERROR_PAR Abort 23.6.4.8 PHY Test Transmit Command The test packet transmitter command may be used to transmit physical layer test packets. A test packet transmitter operation is started by a CMD_BLE_TX_TEST command.
PAGE 1545
Bluetooth Low Energy www.ti.com A trigger to end the operation is set up by pParams->endTrigger and pParams->endTime. If the trigger defined by this parameter occurs, the radio operation ends as soon as possible. If the trigger occurs while waiting between packets, the operation ends immediately. If the trigger occurs at another time, the operation continues until the current packet has been fully transmitted, and then ends.
PAGE 1546
Bluetooth Low Energy www.ti.com 23.6.5 Immediate Commands In addition to the immediate commands from Section 23.3.5, Immediate Commands for Data Queue Manipulation, the following immediate command is supported. 23.6.5.1 Update Advertising Payload Command The CMD_BLE_ADV_PAYLOAD command can change the payload buffer for an advertising command. The command may be issued regardless of whether an advertising command is running or not. The command structure has the format given in Table 23-88.
PAGE 1547
Radio Registers www.ti.com 23.7.1 RFC_DBELL Registers Table 23-131 lists the memory-mapped registers for the RFC_DBELL. All register offset addresses not listed in Table 23-131 should be considered as reserved locations and the register contents should not be modified. Table 23-131. RFC_DBELL Registers Offset Acronym Register Name Section 0h CMDR Doorbell Command Register Section 23.7.1.1 4h CMDSTA Doorbell Command Status Register Section 23.7.1.
PAGE 1548
Radio Registers www.ti.com 23.7.1.1 CMDR Register (Offset = 0h) [reset = X] CMDR is shown in Figure 23-9 and described in Table 23-132. Doorbell Command Register Figure 23-9. CMDR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 CMD R/W-X 9 8 7 6 5 4 3 2 1 0 Table 23-132. CMDR Register Field Descriptions Bit Field Type Reset Description 31-0 CMD R/W X Command register. Raises an interrupt to the Command and packet engine (CPE) upon write.
PAGE 1549
Radio Registers www.ti.com 23.7.1.2 CMDSTA Register (Offset = 4h) [reset = X] CMDSTA is shown in Figure 23-10 and described in Table 23-133. Doorbell Command Status Register Figure 23-10. CMDSTA Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 STAT R-X 9 8 7 6 5 4 3 2 1 0 Table 23-133.
PAGE 1550
Radio Registers www.ti.com 23.7.1.3 RFHWIFG Register (Offset = 8h) [reset = X] RFHWIFG is shown in Figure 23-11 and described in Table 23-134. Interrupt Flags From RF Hardware Modules Figure 23-11.
PAGE 1551
Radio Registers www.ti.com Table 23-134. RFHWIFG Register Field Descriptions (continued) Bit Field Type Reset Description 4 MDMOUT R/W X Modem FIFO output interrupt flag. Write zero to clear flag. Write to one has no effect. 3 MDMIN R/W X Modem FIFO input interrupt flag. Write zero to clear flag. Write to one has no effect. 2 MDMDONE R/W X Modem command done interrupt flag. Write zero to clear flag. Write to one has no effect.
PAGE 1552
Radio Registers www.ti.com 23.7.1.4 RFHWIEN Register (Offset = Ch) [reset = X] RFHWIEN is shown in Figure 23-12 and described in Table 23-135. Interrupt Enable For RF Hardware Modules Figure 23-12.
PAGE 1553
Radio Registers www.ti.com 23.7.1.5 RFCPEIFG Register (Offset = 10h) [reset = X] RFCPEIFG is shown in Figure 23-13 and described in Table 23-136. Interrupt Flags For Command and Packet Engine Generated Interrupts Figure 23-13.
PAGE 1554
Radio Registers www.ti.com Table 23-136. RFCPEIFG Register Field Descriptions (continued) 1554 Bit Field Type Reset Description 20 RX_CTRL R/W X Interrupt flag 20. BLE mode only: LL control packet received with CRC OK, not to be ignored. Write zero to clear flag. Write to one has no effect. 19 RX_EMPTY R/W X Interrupt flag 19. BLE mode only: Packet received with CRC OK, not to be ignored, no payload. Write zero to clear flag. Write to one has no effect.
PAGE 1555
Radio Registers www.ti.com Table 23-136. RFCPEIFG Register Field Descriptions (continued) Bit 0 Field Type Reset Description COMMAND_DONE R/W X Interrupt flag 0. A radio operation has finished. (IEEE 802.15.4 mode: A background level radio operation command has finished.) Write zero to clear flag. Write to one has no effect.
PAGE 1556
Radio Registers www.ti.com 23.7.1.6 RFCPEIEN Register (Offset = 14h) [reset = FFFFFFFFh] RFCPEIEN is shown in Figure 23-14 and described in Table 23-137. Interrupt Enable For Command and Packet Engine Generated Interrupts Figure 23-14.
PAGE 1557
Radio Registers www.ti.com Table 23-137. RFCPEIEN Register Field Descriptions (continued) Bit Field Type Reset Description 10 TX_ENTRY_DONE R/W 1h Interrupt enable for RFCPEIFG.TX_ENTRY_DONE. 9 TX_RETRANS R/W 1h Interrupt enable for RFCPEIFG.TX_RETRANS. 8 TX_CTRL_ACK_ACK R/W 1h Interrupt enable for RFCPEIFG.TX_CTRL_ACK_ACK. 7 TX_CTRL_ACK R/W 1h Interrupt enable for RFCPEIFG.TX_CTRL_ACK. 6 TX_CTRL R/W 1h Interrupt enable for RFCPEIFG.TX_CTRL.
PAGE 1558
Radio Registers www.ti.com 23.7.1.7 RFCPEISL Register (Offset = 18h) [reset = X] RFCPEISL is shown in Figure 23-15 and described in Table 23-138. Interrupt Vector Selection For Command and Packet Engine Generated Interrupts Figure 23-15.
PAGE 1559
Radio Registers www.ti.com Table 23-138. RFCPEISL Register Field Descriptions (continued) Bit Field Type Reset Description 24 RX_DATA_WRITTEN R/W 1h Select which CPU interrupt vector the RFCPEIFG.RX_DATA_WRITTEN interrupt should use. 0h = Associate this interrupt line with INT_RF_CPE0 interrupt vector 1h = Associate this interrupt line with INT_RF_CPE1 interrupt vector 23 RX_ENTRY_DONE R/W 1h Select which CPU interrupt vector the RFCPEIFG.RX_ENTRY_DONE interrupt should use.
PAGE 1560
Radio Registers www.ti.com Table 23-138. RFCPEISL Register Field Descriptions (continued) 1560 Bit Field Type Reset Description 11 TX_BUFFER_CHANGED R/W X Select which CPU interrupt vector the RFCPEIFG.TX_BUFFER_CHANGED interrupt should use. 0h = Associate this interrupt line with INT_RF_CPE0 interrupt vector 1h = Associate this interrupt line with INT_RF_CPE1 interrupt vector 10 TX_ENTRY_DONE R/W X Select which CPU interrupt vector the RFCPEIFG.TX_ENTRY_DONE interrupt should use.
PAGE 1561
Radio Registers www.ti.com 23.7.1.8 RFACKIFG Register (Offset = 1Ch) [reset = X] RFACKIFG is shown in Figure 23-16 and described in Table 23-139. Doorbell Command Acknowledgement Interrupt Flag Figure 23-16. RFACKIFG Register 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ACKFLAG R/W-X RESERVED R-X 23 22 21 20 RESERVED R-X 15 14 13 12 RESERVED R-X 7 6 5 4 RESERVED R-X Table 23-139.
PAGE 1562
Radio Registers www.ti.com 23.7.1.9 SYSGPOCTL Register (Offset = 20h) [reset = X] SYSGPOCTL is shown in Figure 23-17 and described in Table 23-140. RF Core General Purpose Output Control Figure 23-17. SYSGPOCTL Register 31 30 29 28 27 26 25 15 14 13 GPOCTL3 R/W-X 12 11 10 9 GPOCTL2 R/W-X 24 23 RESERVED R-X 8 7 22 21 20 19 18 17 16 6 5 GPOCTL1 R/W-X 4 3 2 1 GPOCTL0 R/W-X 0 Table 23-140.
PAGE 1563
Radio Registers www.ti.com Table 23-140. SYSGPOCTL Register Field Descriptions (continued) Bit Field Type Reset Description 7-4 GPOCTL1 R/W X RF Core GPO control bit 1. Selects which signal to output on the RF Core GPO line 1.
PAGE 1564
Radio Registers 1564 Radio www.ti.
PAGE 1565
Radio Registers www.ti.com 23.7.2 RFC_PWR Registers Table 23-141 lists the memory-mapped registers for the RFC_PWR. All register offset addresses not listed in Table 23-141 should be considered as reserved locations and the register contents should not be modified. Table 23-141.
PAGE 1566
Radio Registers www.ti.com 23.7.2.1 PWMCLKEN Register (Offset = 0h) [reset = X] PWMCLKEN is shown in Figure 23-18 and described in Table 23-142. RF Core Power Management and Clock Enable Figure 23-18.
PAGE 1567
Radio Registers www.ti.
PAGE 1568
Radio Registers www.ti.com 23.7.3 RFC_RAT Registers Table 23-143 lists the memory-mapped registers for the RFC_RAT. All register offset addresses not listed in Table 23-143 should be considered as reserved locations and the register contents should not be modified. Table 23-143. RFC_RAT Registers 1568 Offset Acronym Register Name 4h RATCNT Radio Timer Counter Value Radio Section Section 23.7.3.
PAGE 1569
Radio Registers www.ti.com 23.7.3.1 RATCNT Register (Offset = 4h) [reset = X] RATCNT is shown in Figure 23-19 and described in Table 23-144. Radio Timer Counter Value Figure 23-19. RATCNT Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 CNT R/W-X 9 8 7 6 5 4 3 2 1 0 Table 23-144. RATCNT Register Field Descriptions Bit Field Type Reset Description 31-0 CNT R/W X Counter value. This is not writable while radio timer counter is enabled.
PAGE 1570
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