User manual
Table Of Contents
- Read This First
- Contents
- Figures
- Tables
- Examples
- Cautions
- Introduction
- Architectural Overview
- Central Processing Unit
- Memory and I/O Spaces
- Program Control
- Addressing Modes
- Assembly Language Instructions
- Instruction Set Summary
- How To Use the Instruction Descriptions
- Instruction Descriptions
- ABS
- ABS
- ADD
- ADD
- ADD
- ADD
- ADDC
- ADDC
- ADDS
- ADDS
- ADDT
- ADDT
- ADRK
- AND
- AND
- AND
- APAC
- APAC
- B
- BACC
- BANZ
- BANZ
- BCND
- BCND
- BIT
- BIT
- BITT
- BITT
- BLDD
- BLDD
- BLDD
- BLDD
- BLDD
- BLPD
- BLPD
- BLPD
- BLPD
- CALA
- CALL
- CC
- CC
- CLRC
- CLRC
- CMPL
- CMPR
- DMOV
- DMOV
- IDLE
- IN
- IN
- INTR
- LACC
- LACC
- LACC
- LACL
- LACL
- LACL
- LACT
- LACT
- LAR
- LAR
- LAR
- LDP
- LDP
- LPH
- LPH
- LST
- LST
- LST
- LST
- LT
- LT
- LTA
- LTA
- LTD
- LTD
- LTD
- LTP
- LTP
- LTS
- LTS
- MAC
- MAC
- MAC
- MAC
- MACD
- MACD
- MACD
- MACD
- MACD
- MAR
- MAR
- MPY
- MPY
- MPY
- MPYA
- MPYA
- MPYS
- MPYS
- MPYU
- MPYU
- NEG
- NEG
- NMI
- NOP
- NORM
- NORM
- NORM
- OR
- OR
- OR
- OUT
- OUT
- PAC
- POP
- POP
- POPD
- POPD
- PSHD
- PSHD
- PUSH
- RET
- RETC
- ROL
- ROR
- RPT
- RPT
- SACH
- SACH
- SACL
- SACL
- SAR
- SAR
- SBRK
- SETC
- SETC
- SFL
- SFR
- SFR
- SPAC
- SPH
- SPH
- SPL
- SPL
- SPLK
- SPLK
- SPM
- SQRA
- SQRA
- SQRS
- SQRS
- SST
- SST
- SUB
- SUB
- SUB
- SUB
- SUBB
- SUBB
- SUBC
- SUBC
- SUBS
- SUBS
- SUBT
- SUBT
- TBLR
- TBLR
- TBLR
- TBLW
- TBLW
- TBLW
- TRAP
- XOR
- XOR
- XOR
- ZALR
- ZALR
- On-Chip Peripherals
- Synchronous Serial Port
- Asynchronous Serial Port
- TMS320C209
- Register Summary
- TMS320C1x/C2x/C2xx/C5x Instruction Set Comparison
- Program Examples
- Submitting ROM Codes to TI
- Design Considerations for Using XDS510 Emulator
- E.1 Designing Your Target System’s Emulator Connector (14-Pin Header)
- E.2 Bus Protocol
- E.3 Emulator Cable Pod
- E.4 Emulator Cable Pod Signal Timing
- E.5 Emulation Timing Calculations
- E.6 Connections Between the Emulator and the Target System
- E.7 Physical Dimensions for the 14-Pin Emulator Connector
- E.8 Emulation Design Considerations
- Glossary
- Index

Device-Specific Information
4-32
Figure 4–16. ’C203 Address Map
FFFFh
’C203 Program ’C203 Data
FFFFh
0800h
0400h
03FFh
0300h
02FFh
0200h
01FFh
0080h
007Fh
0060h
005Fh
0000h
External
DARAM B1
§
On-chip
Reserved (CNF = 1)
B0
‡
(CNF = 0);
On-chip DARAM
Reserved
DARAM B2
On-chip
reserved addresses
registers and
Memory-mapped
0000h
FDFFh
FE00h
External (CNF = 0)
Reserved (CNF = 1);
External
FEFFh
FF00h
FFFFh
On-chip DARAM
B0
†
(CNF = 1);
External (CNF = 0)
Reserved
07FFh
003Fh
Interrupts (external)
’C203 I/O
0000h
External
reserved addresses
registers and
I/O-mapped
External
(local and/or global)
FF00h
FEFFh
FF10h
FF0Fh
Reserved for
test/emulation
8000h
7FFFh
†
When CNF = 1, addresses FE00h–FEFFh and FF00h–FFFFh are mapped to the same physical block (B0) in program-memory
space. For example, a write to FE00h will have the same effect as a write to FF00h. For simplicity, addresses FE00h–FEFFh
are referred to here as reserved when CNF = 1.
‡
When CNF = 0, addresses 0100h–01FFh and 0200h–02FFh are mapped to the same physical block (B0) in data-memory
space. For example, a write to 0100h will have the same effect as a write to 0200h. For simplicity, addresses 0100h–01FFh are
referred to here as reserved.
§
Addresses 0300h–03FFh and 0400h–04FFh are mapped to the same physical block (B1) in data-memory space. For example,
a write to 0400h has the same effect as a write to 0300h. For simplicity, addresses 0400h–04FFh are referred to here as
reserved.