User manual
Table Of Contents
- Read This First
- Contents
- Figures
- Tables
- Examples
- Cautions
- Introduction
- Architectural Overview
- Central Processing Unit
- Memory and I/O Spaces
- Program Control
- Addressing Modes
- Assembly Language Instructions
- Instruction Set Summary
- How To Use the Instruction Descriptions
- Instruction Descriptions
- ABS
- ABS
- ADD
- ADD
- ADD
- ADD
- ADDC
- ADDC
- ADDS
- ADDS
- ADDT
- ADDT
- ADRK
- AND
- AND
- AND
- APAC
- APAC
- B
- BACC
- BANZ
- BANZ
- BCND
- BCND
- BIT
- BIT
- BITT
- BITT
- BLDD
- BLDD
- BLDD
- BLDD
- BLDD
- BLPD
- BLPD
- BLPD
- BLPD
- CALA
- CALL
- CC
- CC
- CLRC
- CLRC
- CMPL
- CMPR
- DMOV
- DMOV
- IDLE
- IN
- IN
- INTR
- LACC
- LACC
- LACC
- LACL
- LACL
- LACL
- LACT
- LACT
- LAR
- LAR
- LAR
- LDP
- LDP
- LPH
- LPH
- LST
- LST
- LST
- LST
- LT
- LT
- LTA
- LTA
- LTD
- LTD
- LTD
- LTP
- LTP
- LTS
- LTS
- MAC
- MAC
- MAC
- MAC
- MACD
- MACD
- MACD
- MACD
- MACD
- MAR
- MAR
- MPY
- MPY
- MPY
- MPYA
- MPYA
- MPYS
- MPYS
- MPYU
- MPYU
- NEG
- NEG
- NMI
- NOP
- NORM
- NORM
- NORM
- OR
- OR
- OR
- OUT
- OUT
- PAC
- POP
- POP
- POPD
- POPD
- PSHD
- PSHD
- PUSH
- RET
- RETC
- ROL
- ROR
- RPT
- RPT
- SACH
- SACH
- SACL
- SACL
- SAR
- SAR
- SBRK
- SETC
- SETC
- SFL
- SFR
- SFR
- SPAC
- SPH
- SPH
- SPL
- SPL
- SPLK
- SPLK
- SPM
- SQRA
- SQRA
- SQRS
- SQRS
- SST
- SST
- SUB
- SUB
- SUB
- SUB
- SUBB
- SUBB
- SUBC
- SUBC
- SUBS
- SUBS
- SUBT
- SUBT
- TBLR
- TBLR
- TBLR
- TBLW
- TBLW
- TBLW
- TRAP
- XOR
- XOR
- XOR
- ZALR
- ZALR
- On-Chip Peripherals
- Synchronous Serial Port
- Asynchronous Serial Port
- TMS320C209
- Register Summary
- TMS320C1x/C2x/C2xx/C5x Instruction Set Comparison
- Program Examples
- Submitting ROM Codes to TI
- Design Considerations for Using XDS510 Emulator
- E.1 Designing Your Target System’s Emulator Connector (14-Pin Header)
- E.2 Bus Protocol
- E.3 Emulator Cable Pod
- E.4 Emulator Cable Pod Signal Timing
- E.5 Emulation Timing Calculations
- E.6 Connections Between the Emulator and the Target System
- E.7 Physical Dimensions for the 14-Pin Emulator Connector
- E.8 Emulation Design Considerations
- Glossary
- Index

Direct Memory Access Using the HOLD Operation
4-28
Example 4–1. An Interrupt Service Routine Supporting INT1 and HOLD
.mmregs ;Include c2xx memory–mapped registers.
ICR .set 0FFECh ;Define interrupt control register in I/O space.
ICRSHDW .set 060h ;Define ICRSHDW in scratch pad location.
* Interrupt vectors *
reset B main ;0 – reset , Branch to main program on reset.
Int1h B int1_hold ;1 – external interrupt 1 or HOLD.
.space 40*16 ;Fill 0000 between vectors and main program.
main: SPLK #0001h,imr ;Enable HOLD/INT1 interrupt line.
CLRC INTM
wait: B wait
*********Interrupt service routine for HOLD logic*****************************
int1_hold:
; Perform any desired context save.
LDP #0 ;Set data–memory page to 0.
IN ICRSHDW, ICR ;Save the contents of ICR register.
LACL #010h ;Load accumulator (ACC) with mask for MODE bit.
AND ICRSHDW ;Filter out all bits except MODE bit.
BCND int1, neq ;Branch if MODE bit is 1, else in HOLD mode.
LACC imr, 0 ;Load ACC with interrupt mask register.
SPLK #1, imr ;Mask all interrupts except interrupt1/HOLD.
IDLE ;Enter HOLD mode. Issues HOLDA, and puts
;buses in high impedance. Wait until
;rising edge is seen on HOLD/INT1 pin.
SPLK #1, ifr ;Clear HOLD/INT1 flag in interrupt flag register
;to prevent re–entering HOLD mode.
SACL imr ;Restore interrupt mask register.
; Perform necessary context restore.
CLRC INTM ;Enable all interrupts.
RET ;Return from HOLD interrupt.
int1: NOP ;Replace these NOPs with desired int1 interrupt
NOP ;service routine.
; Perform necessary context restore.
CLRC INTM ;Enable all interrupts.
RET ;Return from interrupts.