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Table Of Contents

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Contents
Figures
Tables
Examples
Cautions
Introduction
- TMS320 Family
  - History, Development, and Advantages of TMS320 DSPs
  - Typical Applications for the TMS320 Family
- TMS320C2xx Generation
- Key Features of the TMS320C2xx
Architectural Overview
- ’C2xx Bus Structure
- Central Processing Unit
- Memory and I/O Spaces
- Program Control
- On-Chip Peripherals
- Scanning-Logic Circuitry
Central Processing Unit
- Input Scaling Section
- Multiplication Section
  - Multiplier
  - Product-Scaling Shifter
- Central Arithmetic Logic Section
- Auxiliary Register Arithmetic Unit (ARAU)
  - ARAU and Auxiliary Register Functions
- Status Registers ST0 and ST1
Memory and I/O Spaces
- Overview of the Memory and I/O Spaces
  - Pins for Interfacing to External Memory and I/O Spaces
- Program Memory
  - Interfacing With External Program Memory
- Local Data Memory
  - Data Page 0 Address Map
  - Interfacing With External Local Data Memory
- Global Data Memory
  - Interfacing With External Global Data Memory
- Boot Loader
- I/O Space
  - Accessing I/O Space
- Direct Memory Access Using the HOLD Operation
  - HOLD During Reset
- Device-Specific Information
  - TMS320C203 Address Maps and Memory Configuration
  - TMS320C204 Address Maps and Memory Configuration
Program Control
- Program-Address Generation
- Pipeline Operation
- Branches, Calls, and Returns
- Conditional Branches, Calls, and Returns
- Repeating a Single Instruction
- Interrupts
- Reset Operation
- Power-Down Mode
  - Normal Termination of Power-Down Mode
  - Termination of Power-Down During a HOLD Operation
Addressing Modes
- Immediate Addressing Mode
  - Examples of Immediate Addressing
- Direct Addressing Mode
  - Using Direct Addressing Mode
  - Examples of Direct Addressing
- Indirect Addressing Mode
Assembly Language Instructions
- Instruction Set Summary
- How To Use the Instruction Descriptions
- Instruction Descriptions
  - ABS
  - ABS
  - ADD
  - ADD
  - ADD
  - ADD
  - ADDC
  - ADDC
  - ADDS
  - ADDS
  - ADDT
  - ADDT
  - ADRK
  - AND
  - AND
  - AND
  - APAC
  - APAC
  - B
  - BACC
  - BANZ
  - BANZ
  - BCND
  - BCND
  - BIT
  - BIT
  - BITT
  - BITT
  - BLDD
  - BLDD
  - BLDD
  - BLDD
  - BLDD
  - BLPD
  - BLPD
  - BLPD
  - BLPD
  - CALA
  - CALL
  - CC
  - CC
  - CLRC
  - CLRC
  - CMPL
  - CMPR
  - DMOV
  - DMOV
  - IDLE
  - IN
  - IN
  - INTR
  - LACC
  - LACC
  - LACC
  - LACL
  - LACL
  - LACL
  - LACT
  - LACT
  - LAR
  - LAR
  - LAR
  - LDP
  - LDP
  - LPH
  - LPH
  - LST
  - LST
  - LST
  - LST
  - LT
  - LT
  - LTA
  - LTA
  - LTD
  - LTD
  - LTD
  - LTP
  - LTP
  - LTS
  - LTS
  - MAC
  - MAC
  - MAC
  - MAC
  - MACD
  - MACD
  - MACD
  - MACD
  - MACD
  - MAR
  - MAR
  - MPY
  - MPY
  - MPY
  - MPYA
  - MPYA
  - MPYS
  - MPYS
  - MPYU
  - MPYU
  - NEG
  - NEG
  - NMI
  - NOP
  - NORM
  - NORM
  - NORM
  - OR
  - OR
  - OR
  - OUT
  - OUT
  - PAC
  - POP
  - POP
  - POPD
  - POPD
  - PSHD
  - PSHD
  - PUSH
  - RET
  - RETC
  - ROL
  - ROR
  - RPT
  - RPT
  - SACH
  - SACH
  - SACL
  - SACL
  - SAR
  - SAR
  - SBRK
  - SETC
  - SETC
  - SFL
  - SFR
  - SFR
  - SPAC
  - SPH
  - SPH
  - SPL
  - SPL
  - SPLK
  - SPLK
  - SPM
  - SQRA
  - SQRA
  - SQRS
  - SQRS
  - SST
  - SST
  - SUB
  - SUB
  - SUB
  - SUB
  - SUBB
  - SUBB
  - SUBC
  - SUBC
  - SUBS
  - SUBS
  - SUBT
  - SUBT
  - TBLR
  - TBLR
  - TBLR
  - TBLW
  - TBLW
  - TBLW
  - TRAP
  - XOR
  - XOR
  - XOR
  - ZALR
  - ZALR
On-Chip Peripherals
- Control of On-Chip Peripherals
- Clock Generator
  - Clock Generator Options
- CLKOUT1-Pin Control (CLK) Register
- Timer
- Wait-State Generator
  - Generating Wait States With the READY Signal
  - Generating Wait States With the ’C2xx Wait-State Generator
- General-Purpose I/O Pins
Synchronous Serial Port
- Overview of the Synchronous Serial Port
- Components and Basic Operation
- Controlling and Resetting the Port
- Managing the Contents of the FIFO Buffers
- Transmitter Operation
- Receiver Operation
  - Burst Mode Reception
  - Continuous Mode Reception
- Troubleshooting
Asynchronous Serial Port
- Overview of the Asynchronous Serial Port
- Components and Basic Operation
- Controlling and Resetting the Port
- Transmitter Operation
- Receiver Operation
TMS320C209
- ’C209 Versus Other ’C2xx Devices
- ’C209 Memory and I/O Spaces
- ’C209 Interrupts
  - ’C209 Interrupt Registers
  - IACK Pin
- ’C209 On-Chip Peripherals
Register Summary
- A.1 Addresses and Reset Values
- A.2 Register Descriptions
TMS320C1x/C2x/C2xx/C5x Instruction Set Comparison
- B.1 Using the Instruction Set Comparison Table
  - B.1.1 An Example of a Table Entry
  - B.1.2 Symbols and Acronyms Used in the Table
- B.2 Enhanced Instructions
- B.3 Instruction Set Comparison Table
Program Examples
- C.1 About These Program Examples
- C.2 Shared Program Code
- C.3 Task-Specific Program Code
- C.4 Introduction to Generating Boot Loader Code
Submitting ROM Codes to TI
Design Considerations for Using XDS510 Emulator
- E.1 Designing Your Target System’s Emulator Connector (14-Pin Header)
- E.2 Bus Protocol
- E.3 Emulator Cable Pod
- E.4 Emulator Cable Pod Signal Timing
- E.5 Emulation Timing Calculations
- E.6 Connections Between the Emulator and the Target System
- E.7 Physical Dimensions for the 14-Pin Emulator Connector
- E.8 Emulation Design Considerations
Glossary
Index

Index

Index-5

bus request pin (BR

)

definition 4-3

shown in figure 4-13, 4-15

buses

block diagram 2-4

data read bus (DRDB) 2-3

data write bus (DWEB) 2-3

data-read address bus (DRAB) 2-3

data-write address bus (DWAB) 2-3

program address bus (PAB)

definition 2-3

used in program-memory address genera-

tion 5-3

program read bus (PRDB) 2-3

C (carry bit)

affected during SFL and SFR instruc-

tions 7-157 to 7-159

definition 3-16

involved in accumulator events 3-10

used during ROL and ROR instruc-

tions 7-144 to 7-146

’C209 device 11-1 to 11-18

comparison to other ’C2xx devices 11-2

differences in interrupts 11-3

differences in memory and I/O spaces 11-3

differences in peripherals 11-2

similarities 11-2

interrupts 11-10

locating ’C209 information in this manual

(table) 11-3

memory and I/O spaces 11-5

on-chip peripherals 11-14

cable, target system to emulator E-1 to E-25

cable pod E-5, E-6

CAD bit 10-8

CALA instruction 7-58

CALL instruction 7-59

call instructions

call subroutine at location specified by accumula-

tor (CALA) 7-58

call subroutine conditionally (CC) 7-60

call subroutine unconditionally (CALL) 7-59

conditional, overview 5-12

unconditional, overview 5-8

CALU (central arithmetic logic unit)

definition F-4

description 3-9

carry bit (C)

affected during SFL and SFR instruc-

tions 7-157 to 7-159

definition 3-16

involved in accumulator events 3-10

used during ROL and ROR instruc-

tions 7-144 to 7-146

CC instruction 7-60

central arithmetic logic section of CPU 3-8

central arithmetic logic unit (CALU).

See

CALU

central processing unit.

See

CPU

CIO0–CIO3 (bits), configuring pins IO0–IO3 as in-

puts/outputs 10-15

CLK register

description 8-7

quick reference A-11

reset condition 5-34

CLKIN signal 8-4 to 8-6

CLKMOD pin 11-14, F-4

CLKOUT1 bit 8-7

CLKOUT1 signal 8-4 to 8-6

definition F-4

turning CLKOUT1 pin on and off 8-7

CLKOUT1-pin control (CLK) register

description 8-7

quick reference A-11

reset condition 5-34

CLKR pin

as bit input (IN0 bit) 9-10

definition 9-4

CLKX pin 9-4

clock generator 8-4 to 8-6

’C209 clock options 11-14 to 11-18

introduction 2-11

modes

’C203/C204 8-5

’C209 11-14 to 11-18

clock mode bit (MCM) 9-11

clock modes

clock generator

’C203/C204 8-5

’C209 11-14

synchronous serial port 9-11

CLRC instruction 7-62

CMPL instruction 7-64