User manual

Central Arithmetic Logic Section
3-10
Status bits. Four status bits are associated with the accumulator:
Carry bit (C). C (bit 9 of status register ST1) is affected during:
Additions to and subtractions from the accumulator:
C = 0 When the result of a subtraction generates a borrow.
When the result of an addition does not generate a carry. (Ex-
ception: When the ADD instruction is used with a shift of 16 and
no carry is generated, the ADD instruction has no affect on C.)
C = 1 When the result of an addition generates a carry.
When the result of a subtraction does not generate a borrow.
(Exception: When the SUB instruction is used with a shift of 16
and no borrow is generated, the SUB instruction has no effect
on C.)
Single-bit shifts and rotations of the accumulator value. During a left
shift or rotation, the most significant bit of the accumulator is passed to
C; during a right shift or rotation, the least significant bit is passed to C.
Overflow mode bit (OVM). OVM (bit 11 of status register ST0) determines
how the accumulator will reflect arithmetic overflows. When the processor
is in overflow mode (OVM = 1) and an overflow occurs, the accumulator
is filled with one of two specific values:
If the overflow is in the positive direction, the accumulator is filled with
its most positive value (7FFF FFFFh).
If the overflow is in the negative direction, the accumulator is filled with
its most negative value (8000 0000h).
Overflow flag bit (OV). OV is bit 12 of status register ST0. When no accu-
mulator overflow is detected, OV is latched at 0. When overflow (positive
or negative) occurs, OV is set to 1 and latched.
Test/control flag bit (TC). TC (bit 11 of status register ST1) is set to 0 or 1
depending on the value of a tested bit. In the case of the NORM instruction,
if the exclusive-OR of the two MSBs of the accumulator is true, TC is set
to 1.
A number of branch instructions are implemented based on the status of bits
C, OV, and TC, and on the value in the accumulator (as compared to zero). For
more information about these instructions, see Section 5.4,
Conditional
Branches, Calls, and Returns
, on page 5-10.