User manual

F-3 Glossary
B
B0: An on-chip block of dual-access RAM that can be configured as either
data memory or program memory, depending on the value of the CNF
bit in status register ST1.
B1: An on-chip block of dual-access RAM available for data memory.
B2: An on-chip block of dual-access RAM available for data memory.
baud-rate divisor register (BRD): A register for the asynchronous serial
port that is used to set the serial port’s baud rate.
BI bit:
Break interrupt bit . Bit 13 of the I/O status register (IOSR); indicates
when a break is detected on the asynchronous receive (RX) pin.
BIO
pin: A general-purpose input pin that can be tested by conditional
instructions that cause a branch when an external device drives BIO
low.
bit-reversed indexed addressing: A method of indirect addressing that
allows efficient I/O operations by resequencing the data points in a
radix-2 FFT program. The direction of carry propagation in the ARAU is
reversed.
boot loader: A built-in segment of code that transfers code from an 8-bit
external source to a 16-bit external program destination at reset.
BOOT
pin: The pin that enables the on-chip boot loader. When BOOT is held
low, the processor executes the boot loader program after a hardware
reset. When BOOT
is held high, the processor skips execution of the boot
loader and accesses off-chip program-memory at reset.
BR
: Bus request pin . This pin is tied to the BR signal, which is asserted when
a global data memory access is initiated.
branch: A switching of program control to a nonsequential program-
memory address.
BRD: See
baud-rate divisor register (BRD).
burst mode: A synchronous serial port mode in which the transmission or
reception of each word is preceded by a frame synchronization pulse.
See also
continuous mode .
C
C bit: See carry bit (C).
CAD bit: Calibrate A detect bit . Bit 5 of the ASPCR; enables and disables
the automatic baud-rate detection logic of the on-chip asynchronous
serial port.
Glossary