User manual

Emulation Design Considerations
E-16
E.8 Emulation Design Considerations
This section describes the use and application of the scan path linker (SPL),
which can simultaneously add all four secondary JTAG scan paths to the main
scan path. It also describes the use of the emulation pins and the configuration
of multiple processors.
E.8.1 Using Scan Path Linkers
You can use the TI ACT8997 scan path linker (SPL) to divide the JTAG
emulation scan path into smaller, logically connected groups of 4 to 16
devices. As described in the
Advanced Logic and Bus Interface Logic Data
Book
, the SPL is compatible with the JTAG emulation scanning. The SPL is
capable of adding any combination of its four secondary scan paths into the
main scan path.
A system of multiple, secondary JTAG scan paths has better fault tolerance
and isolation than a single scan path. Since an SPL has the capability of adding
all secondary scan paths to the main scan path simultaneously, it can support
global emulation operations, such as starting or stopping a selected group of
processors.
TI emulators do not support the nesting of SPLs (for example, an SPL
connected to the secondary scan path of another SPL). However, you can
have multiple SPLs on the main scan path.
Scan path selectors are not supported by this emulation system. The TI
ACT8999 scan path selector is similar to the SPL, but it can add only one of
its secondary scan paths at a time to the main JTAG scan path. Thus, global
emulation operations are not assured with the scan path selector.
You can insert an SPL on a backplane so that you can add up to four device
boards to the system without the jumper wiring required with nonbackplane
devices. You connect an SPL to the main JTAG scan path in the same way you
connect any other device. Figure E–10 shows how to connect a secondary
scan path to an SPL.