User manual
Table Of Contents
- Read This First
- Contents
- Figures
- Tables
- Examples
- Cautions
- Introduction
- Architectural Overview
- Central Processing Unit
- Memory and I/O Spaces
- Program Control
- Addressing Modes
- Assembly Language Instructions
- Instruction Set Summary
- How To Use the Instruction Descriptions
- Instruction Descriptions
- ABS
- ABS
- ADD
- ADD
- ADD
- ADD
- ADDC
- ADDC
- ADDS
- ADDS
- ADDT
- ADDT
- ADRK
- AND
- AND
- AND
- APAC
- APAC
- B
- BACC
- BANZ
- BANZ
- BCND
- BCND
- BIT
- BIT
- BITT
- BITT
- BLDD
- BLDD
- BLDD
- BLDD
- BLDD
- BLPD
- BLPD
- BLPD
- BLPD
- CALA
- CALL
- CC
- CC
- CLRC
- CLRC
- CMPL
- CMPR
- DMOV
- DMOV
- IDLE
- IN
- IN
- INTR
- LACC
- LACC
- LACC
- LACL
- LACL
- LACL
- LACT
- LACT
- LAR
- LAR
- LAR
- LDP
- LDP
- LPH
- LPH
- LST
- LST
- LST
- LST
- LT
- LT
- LTA
- LTA
- LTD
- LTD
- LTD
- LTP
- LTP
- LTS
- LTS
- MAC
- MAC
- MAC
- MAC
- MACD
- MACD
- MACD
- MACD
- MACD
- MAR
- MAR
- MPY
- MPY
- MPY
- MPYA
- MPYA
- MPYS
- MPYS
- MPYU
- MPYU
- NEG
- NEG
- NMI
- NOP
- NORM
- NORM
- NORM
- OR
- OR
- OR
- OUT
- OUT
- PAC
- POP
- POP
- POPD
- POPD
- PSHD
- PSHD
- PUSH
- RET
- RETC
- ROL
- ROR
- RPT
- RPT
- SACH
- SACH
- SACL
- SACL
- SAR
- SAR
- SBRK
- SETC
- SETC
- SFL
- SFR
- SFR
- SPAC
- SPH
- SPH
- SPL
- SPL
- SPLK
- SPLK
- SPM
- SQRA
- SQRA
- SQRS
- SQRS
- SST
- SST
- SUB
- SUB
- SUB
- SUB
- SUBB
- SUBB
- SUBC
- SUBC
- SUBS
- SUBS
- SUBT
- SUBT
- TBLR
- TBLR
- TBLR
- TBLW
- TBLW
- TBLW
- TRAP
- XOR
- XOR
- XOR
- ZALR
- ZALR
- On-Chip Peripherals
- Synchronous Serial Port
- Asynchronous Serial Port
- TMS320C209
- Register Summary
- TMS320C1x/C2x/C2xx/C5x Instruction Set Comparison
- Program Examples
- Submitting ROM Codes to TI
- Design Considerations for Using XDS510 Emulator
- E.1 Designing Your Target System’s Emulator Connector (14-Pin Header)
- E.2 Bus Protocol
- E.3 Emulator Cable Pod
- E.4 Emulator Cable Pod Signal Timing
- E.5 Emulation Timing Calculations
- E.6 Connections Between the Emulator and the Target System
- E.7 Physical Dimensions for the 14-Pin Emulator Connector
- E.8 Emulation Design Considerations
- Glossary
- Index

Task-Specific Program Code
C-12
Example C–8. Testing and Using Interrupts INT2 and INT3 (intr23.asm)
* File: intr23.asm *
* Function: Interrupt test code *
* Interrupt on INT2 or INT3 will toggle IO3 and IO2 bits *
* and icr value copied in the Buffer @300 *
.title ” Interrupt 2/3 Test” ; Title
.copy ”init.h” ; Variable and register declaration
.copy ”vector.h” ; Vector label declaration
.text
start: clrc CNF ; Map block B0 to data memory
ldp #0h ; set DP=0
setc INTM ; Disable all interrupts
splk #0ffffh, ifr ; clear interrupts
splk #0002h, imr ; Enable int1 interrupts
splk #0003h, 60h
out 60h, icr ; Enable Int2 and 3 in ICR
splk #0000h, 60h
out 60h, wsgr ; Set zero wait states
splk #0e00ch, 60h ; configure the I03 and IO2 as outputs
out 60h, aspcr ; set the aspcr for the above
mar *, ar1 ; ARP=ar1
lar ar1, #rxbuf
lar ar0, #size ; set counter limit
splk #0004h, 61h ; set bit I/O 2
splk #0008h, 62h ; set bit I/O 3
splk #0063h, 63h ; set tx data
clrc intm
clrc xf
wait: out 61h, iosr ; toggle I/O 2
idle
clrc xf ; toggle xf bit
b wait
inpt23: in 65h, icr ; Read icr
in *+, icr ; Capture icr in buffer @300
mar *,ar0
banz skip, ar1
lar ar1, #rxbuf
lar ar0, #size
skip: out 62h, iosr ; toggle IO2/3
setc xf ; toggle xf
out 65h, icr ; clear interrupt 2/3 flag bit
clrc intm
ret
timer: ret
inpt1: ret
uart: ret
codtx: ret
codrx: ret
.end ; Assembler module end directive
; –optional