User manual
Table Of Contents
- Read This First
- Contents
- Figures
- Tables
- Examples
- Cautions
- Introduction
- Architectural Overview
- Central Processing Unit
- Memory and I/O Spaces
- Program Control
- Addressing Modes
- Assembly Language Instructions
- Instruction Set Summary
- How To Use the Instruction Descriptions
- Instruction Descriptions
- ABS
- ABS
- ADD
- ADD
- ADD
- ADD
- ADDC
- ADDC
- ADDS
- ADDS
- ADDT
- ADDT
- ADRK
- AND
- AND
- AND
- APAC
- APAC
- B
- BACC
- BANZ
- BANZ
- BCND
- BCND
- BIT
- BIT
- BITT
- BITT
- BLDD
- BLDD
- BLDD
- BLDD
- BLDD
- BLPD
- BLPD
- BLPD
- BLPD
- CALA
- CALL
- CC
- CC
- CLRC
- CLRC
- CMPL
- CMPR
- DMOV
- DMOV
- IDLE
- IN
- IN
- INTR
- LACC
- LACC
- LACC
- LACL
- LACL
- LACL
- LACT
- LACT
- LAR
- LAR
- LAR
- LDP
- LDP
- LPH
- LPH
- LST
- LST
- LST
- LST
- LT
- LT
- LTA
- LTA
- LTD
- LTD
- LTD
- LTP
- LTP
- LTS
- LTS
- MAC
- MAC
- MAC
- MAC
- MACD
- MACD
- MACD
- MACD
- MACD
- MAR
- MAR
- MPY
- MPY
- MPY
- MPYA
- MPYA
- MPYS
- MPYS
- MPYU
- MPYU
- NEG
- NEG
- NMI
- NOP
- NORM
- NORM
- NORM
- OR
- OR
- OR
- OUT
- OUT
- PAC
- POP
- POP
- POPD
- POPD
- PSHD
- PSHD
- PUSH
- RET
- RETC
- ROL
- ROR
- RPT
- RPT
- SACH
- SACH
- SACL
- SACL
- SAR
- SAR
- SBRK
- SETC
- SETC
- SFL
- SFR
- SFR
- SPAC
- SPH
- SPH
- SPL
- SPL
- SPLK
- SPLK
- SPM
- SQRA
- SQRA
- SQRS
- SQRS
- SST
- SST
- SUB
- SUB
- SUB
- SUB
- SUBB
- SUBB
- SUBC
- SUBC
- SUBS
- SUBS
- SUBT
- SUBT
- TBLR
- TBLR
- TBLR
- TBLW
- TBLW
- TBLW
- TRAP
- XOR
- XOR
- XOR
- ZALR
- ZALR
- On-Chip Peripherals
- Synchronous Serial Port
- Asynchronous Serial Port
- TMS320C209
- Register Summary
- TMS320C1x/C2x/C2xx/C5x Instruction Set Comparison
- Program Examples
- Submitting ROM Codes to TI
- Design Considerations for Using XDS510 Emulator
- E.1 Designing Your Target System’s Emulator Connector (14-Pin Header)
- E.2 Bus Protocol
- E.3 Emulator Cable Pod
- E.4 Emulator Cable Pod Signal Timing
- E.5 Emulation Timing Calculations
- E.6 Connections Between the Emulator and the Target System
- E.7 Physical Dimensions for the 14-Pin Emulator Connector
- E.8 Emulation Design Considerations
- Glossary
- Index

Instruction Set Comparison Table
B-26
Syntax
Description5x2xx2x1x
POPD
dma
POPD {
ind
} [
, next ARP
]
√
√
√
√
√
√
Pop Top of Stack to Data Memory
Transfer the value on the top of the stack into the ad-
dressed data-memory location and then pop the stack
one level.
PSHD
dma
PSHD {
ind
} [
, next ARP
]
√
√
√
√
√
√
Push Data-Memory Value Onto Stack
Copy the addressed data-memory location onto the
top of the stack. The stack is pushed down one level
before the value is copied.
PUSH
√ √ √ √
Push Low Accumulator Onto Stack
Copy the contents of the 12 (TMS320C1x) or 16
(TMS320C2x/2xx/5x) LSBs of the accumulator onto
the top of the hardware stack. The stack is pushed
down one level before the value is copied.
RC
√ √ √
Reset Carry Bit
Reset the C status bit to 0.
RET
√ √ √
Return From Subroutine
Copy the contents of the top of the stack into the PC
and pop the stack one level.
RET[
D
]
√
Return From Subroutine With Optional Delay
Copy the contents of the top of the stack into the PC
and pop the stack one level.
If you specify a delayed branch (RETD), the next two
instruction words (two 1-word instructions or one
2-word instruction) are fetched and executed before
the return.
RETC
cond
1
[
, cond
2
] [, ...]
√
Return Conditionally
If the specified conditions are met, RETC performs a
standard return. Not all combinations of conditions are
meaningful.
RETC[
D
]
cond
1
[
, cond
2
] [, ...]
√
Return Conditionally With Optional Delay
If the specified conditions are met, RETC performs a
standard return. Not all combinations of conditions are
meaningful.
If you specify a delayed branch (RETCD), the next two
instruction words (two 1-word instructions or one
2-word instruction) are fetched and executed before
the return.