User manual
Table Of Contents
- Read This First
- Contents
- Figures
- Tables
- Examples
- Cautions
- Introduction
- Architectural Overview
- Central Processing Unit
- Memory and I/O Spaces
- Program Control
- Addressing Modes
- Assembly Language Instructions
- Instruction Set Summary
- How To Use the Instruction Descriptions
- Instruction Descriptions
- ABS
- ABS
- ADD
- ADD
- ADD
- ADD
- ADDC
- ADDC
- ADDS
- ADDS
- ADDT
- ADDT
- ADRK
- AND
- AND
- AND
- APAC
- APAC
- B
- BACC
- BANZ
- BANZ
- BCND
- BCND
- BIT
- BIT
- BITT
- BITT
- BLDD
- BLDD
- BLDD
- BLDD
- BLDD
- BLPD
- BLPD
- BLPD
- BLPD
- CALA
- CALL
- CC
- CC
- CLRC
- CLRC
- CMPL
- CMPR
- DMOV
- DMOV
- IDLE
- IN
- IN
- INTR
- LACC
- LACC
- LACC
- LACL
- LACL
- LACL
- LACT
- LACT
- LAR
- LAR
- LAR
- LDP
- LDP
- LPH
- LPH
- LST
- LST
- LST
- LST
- LT
- LT
- LTA
- LTA
- LTD
- LTD
- LTD
- LTP
- LTP
- LTS
- LTS
- MAC
- MAC
- MAC
- MAC
- MACD
- MACD
- MACD
- MACD
- MACD
- MAR
- MAR
- MPY
- MPY
- MPY
- MPYA
- MPYA
- MPYS
- MPYS
- MPYU
- MPYU
- NEG
- NEG
- NMI
- NOP
- NORM
- NORM
- NORM
- OR
- OR
- OR
- OUT
- OUT
- PAC
- POP
- POP
- POPD
- POPD
- PSHD
- PSHD
- PUSH
- RET
- RETC
- ROL
- ROR
- RPT
- RPT
- SACH
- SACH
- SACL
- SACL
- SAR
- SAR
- SBRK
- SETC
- SETC
- SFL
- SFR
- SFR
- SPAC
- SPH
- SPH
- SPL
- SPL
- SPLK
- SPLK
- SPM
- SQRA
- SQRA
- SQRS
- SQRS
- SST
- SST
- SUB
- SUB
- SUB
- SUB
- SUBB
- SUBB
- SUBC
- SUBC
- SUBS
- SUBS
- SUBT
- SUBT
- TBLR
- TBLR
- TBLR
- TBLW
- TBLW
- TBLW
- TRAP
- XOR
- XOR
- XOR
- ZALR
- ZALR
- On-Chip Peripherals
- Synchronous Serial Port
- Asynchronous Serial Port
- TMS320C209
- Register Summary
- TMS320C1x/C2x/C2xx/C5x Instruction Set Comparison
- Program Examples
- Submitting ROM Codes to TI
- Design Considerations for Using XDS510 Emulator
- E.1 Designing Your Target System’s Emulator Connector (14-Pin Header)
- E.2 Bus Protocol
- E.3 Emulator Cable Pod
- E.4 Emulator Cable Pod Signal Timing
- E.5 Emulation Timing Calculations
- E.6 Connections Between the Emulator and the Target System
- E.7 Physical Dimensions for the 14-Pin Emulator Connector
- E.8 Emulation Design Considerations
- Glossary
- Index

Instruction Set Comparison Table
B-25
TMS320C1x/C2x/C2xx/C5x Instruction Set Comparison
Syntax
Description5x2xx2x1x
OR
dma
OR {
ind
} [
, next ARP
]
OR #
lk
[
, shift
]
√
√
√
√
√
√
√
√
√
√
OR With Accumulator
TMS320C1x and TMS320C2x devices: OR the 16
LSBs of the accumulator with the contents of the ad-
dressed data-memory location. The 16 MSBs of the
accumulator are ORed with 0s.
TMS320C2xx and TMS320C5x devices: OR the 16
LSBs of the accumulator or a 16-bit immediate value
with the contents of the addressed data-memory loca-
tion. If a shift is specified, left-shift before ORing. Low-
order bits below and high-order bits above the shifted
value are treated as 0s.
ORB
√
OR ACCB With Accumulator
OR the contents of the ACCB with the contents of the
accumulator. ORB places the result in the accumula-
tor.
ORK #
lk
[
, shift
]
√ √ √
OR Immediate With Accumulator with Shift
OR a 16-bit immediate value with the contents of the
accumulator. If a shift is specified, left-shift the con-
stant before ORing. Low-order bits below and high-
order bits above the shifted value are treated as 0s.
OUT
dma, PA
OUT {
ind
}
, PA
[
, next ARP
]
√
√
√
√
√
√
√
√
Output Data to Port
Write a 16-bit value from a data-memory location to the
specified I/O port.
TMS320C1x devices: The first cycle of this instruction
places the port address onto address lines
A2/PA2–A0/PA0. During the same cycle, WE goes low
and the data word is placed on the data bus D15–D0.
TMS320C2x, TMS320C2xx, and TMS320C5x de-
vices: The IS
line goes low to indicate an I/O access;
the STRB
, R/W, and READY timings are the same as
for an external data-memory write.
PAC
√ √ √ √
Load Accumulator With P Register
Load the contents of the P register into the accumula-
tor.
TMS320C2x, TMS320C2xx, and TMS320C5x de-
vices: Before the load, shift the P register as specified
by the PM status bits.
POP
√ √ √ √
Pop Top of Stack to Low Accumulator
Copy the contents of the top of the stack into the 12
(TMS320C1x) or 16 (TMS320C2x/2xx/5x) LSBs of the
accumulator and then pop the stack one level. The
MSBs of the accumulator are zeroed.