User manual
Table Of Contents
- Read This First
- Contents
- Figures
- Tables
- Examples
- Cautions
- Introduction
- Architectural Overview
- Central Processing Unit
- Memory and I/O Spaces
- Program Control
- Addressing Modes
- Assembly Language Instructions
- Instruction Set Summary
- How To Use the Instruction Descriptions
- Instruction Descriptions
- ABS
- ABS
- ADD
- ADD
- ADD
- ADD
- ADDC
- ADDC
- ADDS
- ADDS
- ADDT
- ADDT
- ADRK
- AND
- AND
- AND
- APAC
- APAC
- B
- BACC
- BANZ
- BANZ
- BCND
- BCND
- BIT
- BIT
- BITT
- BITT
- BLDD
- BLDD
- BLDD
- BLDD
- BLDD
- BLPD
- BLPD
- BLPD
- BLPD
- CALA
- CALL
- CC
- CC
- CLRC
- CLRC
- CMPL
- CMPR
- DMOV
- DMOV
- IDLE
- IN
- IN
- INTR
- LACC
- LACC
- LACC
- LACL
- LACL
- LACL
- LACT
- LACT
- LAR
- LAR
- LAR
- LDP
- LDP
- LPH
- LPH
- LST
- LST
- LST
- LST
- LT
- LT
- LTA
- LTA
- LTD
- LTD
- LTD
- LTP
- LTP
- LTS
- LTS
- MAC
- MAC
- MAC
- MAC
- MACD
- MACD
- MACD
- MACD
- MACD
- MAR
- MAR
- MPY
- MPY
- MPY
- MPYA
- MPYA
- MPYS
- MPYS
- MPYU
- MPYU
- NEG
- NEG
- NMI
- NOP
- NORM
- NORM
- NORM
- OR
- OR
- OR
- OUT
- OUT
- PAC
- POP
- POP
- POPD
- POPD
- PSHD
- PSHD
- PUSH
- RET
- RETC
- ROL
- ROR
- RPT
- RPT
- SACH
- SACH
- SACL
- SACL
- SAR
- SAR
- SBRK
- SETC
- SETC
- SFL
- SFR
- SFR
- SPAC
- SPH
- SPH
- SPL
- SPL
- SPLK
- SPLK
- SPM
- SQRA
- SQRA
- SQRS
- SQRS
- SST
- SST
- SUB
- SUB
- SUB
- SUB
- SUBB
- SUBB
- SUBC
- SUBC
- SUBS
- SUBS
- SUBT
- SUBT
- TBLR
- TBLR
- TBLR
- TBLW
- TBLW
- TBLW
- TRAP
- XOR
- XOR
- XOR
- ZALR
- ZALR
- On-Chip Peripherals
- Synchronous Serial Port
- Asynchronous Serial Port
- TMS320C209
- Register Summary
- TMS320C1x/C2x/C2xx/C5x Instruction Set Comparison
- Program Examples
- Submitting ROM Codes to TI
- Design Considerations for Using XDS510 Emulator
- E.1 Designing Your Target System’s Emulator Connector (14-Pin Header)
- E.2 Bus Protocol
- E.3 Emulator Cable Pod
- E.4 Emulator Cable Pod Signal Timing
- E.5 Emulation Timing Calculations
- E.6 Connections Between the Emulator and the Target System
- E.7 Physical Dimensions for the 14-Pin Emulator Connector
- E.8 Emulation Design Considerations
- Glossary
- Index

Register Descriptions
A-12
Synchronous Serial Port Control Register (SSPCR) — I/O Address FFF1h
15 14 13 12
11 10 9 8
0 0 0 0 0 0 0 0
FREE SOFT TCOMP RFNE FT1 FT0 FR1 FR0
0
1
0
1
Immediate stop
Stop after completion of word
Free run
Free run
0
0
1
1
0
1
Transmit buffer empty.
Transmit buffer not empty.
0
1
Receive buffer empty.
Receive buffer holds data.
0
1
0
1
Transmit buffer can accept 1 or more words.
Transmit buffer can accept 2 or more words.
Transmit buffer can accept 3 or 4 words.
Transmit buffer empty (can accept 4 words).
0
0
1
1
0
1
0
1
Receive buffer not empty.
Receive buffer holds 2 or more words.
Receive buffer holds 3 or 4 words.
Receive buffer full.
0
0
1
1
Emulation/run mode
Generate XINT when . . .
Generate RINT when . . .
R/WR/W
RR
R/WR/W R/W R/W
Transmit FIFO buffer status
Receive FIFO buffer status
7 6 5 4
3 2 1 0
0 0 1 1 0 0 0 0
OVF IN0 XRST RRST TXM MCM FSM DLB
0
1
No overflow condition
Overflow detected in receive buffer
0
1
Level on CLKR pin is low.
Level on CLKR pin is high.
0
1
Transmitter in reset
Transmitter enabled
0
1
Receiver in reset
Receiver enabled
0
1
External frame sync source
Internal frame sync source
0
1
External clock source
Internal clock source
0
1
Continuous mode
Burst mode
0
1
Digital loopback mode disabled
Digital loopback mode enabled
R/W R/W R/W R/WR/WR R R/W
Overflow flag
CLKR pin status
Transmitter reset
Receiver reset
Transmit frame sync source
Transmit clock source
Frame sync mode
Digital loopback mode