User manual

’C209 On-Chip Peripherals
11-14
11.4 ’C209 On-Chip Peripherals
The ’C209 has these on-chip peripherals:
Clock generator. The clock generator is fundamentally the same on all
’C2xx devices, including the ’C209. However, the ’C209 is limited to the
two clock modes described in subsection 11.4.1.
Timer. The timer is also fundamentally the same. The difference here is
that the timer control register (TCR) on the ’C209 does not offer bits for
configuring timer emulation modes. Subsection 11.4.2 describes the
’C209 TCR.
Wait-state generator. The wait-state generators of the ’C2xx devices op-
erate similarly; however, the ’C209 wait-state generator is different from
that of other ’C2xx devices in these ways:
It offers zero or one wait states (not zero to seven).
It cannot produce separate wait states for the lower (0000h–7FFFh)
and upper (8000h–FFFFh) halves of program space.
It provides a bit for enabling or disabling address visibility mode. In this
mode (not available on other ’C2xx devices), the ’C209 passes the in-
ternal program address to the external address bus when this bus is
not used for an external access.
The ’C209 generator is programmable by way of the ’C209 wait-state gen-
erator control register (WSGR) and is described subsection 11.4.3.
11.4.1 ’C209 Clock Generator Options
The ’C209 includes two clock modes: divide-by-2 (÷2) and multiply-by-2 (×2).
The
÷2 mode operates the CPU at half the input clock rate. The ×2 option
doubles the input clock and phase-locks the output clock with the input clock.
To enable the
÷2 mode, tie the CLKMOD pin low. To enable the ×2 mode, tie
CLKMOD high. For each clock mode, Table 11–5 shows the generated CPU
clock rate and shows the state of CLKMOD, the internal oscillator, and the in-
ternal phase lock loop (PLL).
Notes:
Change CLKMOD only while the reset signal (RS or RS) is active.
The PLL requires approximately 2200 cycles to lock the output clock sig-
nal to the input clock signal. When setting the ×2 mode, keep the reset
(RS
or RS) signal active until at least three cycles after the PLL has stabi-
lized.