User manual
Table Of Contents
- Read This First
- Contents
- Figures
- Tables
- Examples
- Cautions
- Introduction
- Architectural Overview
- Central Processing Unit
- Memory and I/O Spaces
- Program Control
- Addressing Modes
- Assembly Language Instructions
- Instruction Set Summary
- How To Use the Instruction Descriptions
- Instruction Descriptions
- ABS
- ABS
- ADD
- ADD
- ADD
- ADD
- ADDC
- ADDC
- ADDS
- ADDS
- ADDT
- ADDT
- ADRK
- AND
- AND
- AND
- APAC
- APAC
- B
- BACC
- BANZ
- BANZ
- BCND
- BCND
- BIT
- BIT
- BITT
- BITT
- BLDD
- BLDD
- BLDD
- BLDD
- BLDD
- BLPD
- BLPD
- BLPD
- BLPD
- CALA
- CALL
- CC
- CC
- CLRC
- CLRC
- CMPL
- CMPR
- DMOV
- DMOV
- IDLE
- IN
- IN
- INTR
- LACC
- LACC
- LACC
- LACL
- LACL
- LACL
- LACT
- LACT
- LAR
- LAR
- LAR
- LDP
- LDP
- LPH
- LPH
- LST
- LST
- LST
- LST
- LT
- LT
- LTA
- LTA
- LTD
- LTD
- LTD
- LTP
- LTP
- LTS
- LTS
- MAC
- MAC
- MAC
- MAC
- MACD
- MACD
- MACD
- MACD
- MACD
- MAR
- MAR
- MPY
- MPY
- MPY
- MPYA
- MPYA
- MPYS
- MPYS
- MPYU
- MPYU
- NEG
- NEG
- NMI
- NOP
- NORM
- NORM
- NORM
- OR
- OR
- OR
- OUT
- OUT
- PAC
- POP
- POP
- POPD
- POPD
- PSHD
- PSHD
- PUSH
- RET
- RETC
- ROL
- ROR
- RPT
- RPT
- SACH
- SACH
- SACL
- SACL
- SAR
- SAR
- SBRK
- SETC
- SETC
- SFL
- SFR
- SFR
- SPAC
- SPH
- SPH
- SPL
- SPL
- SPLK
- SPLK
- SPM
- SQRA
- SQRA
- SQRS
- SQRS
- SST
- SST
- SUB
- SUB
- SUB
- SUB
- SUBB
- SUBB
- SUBC
- SUBC
- SUBS
- SUBS
- SUBT
- SUBT
- TBLR
- TBLR
- TBLR
- TBLW
- TBLW
- TBLW
- TRAP
- XOR
- XOR
- XOR
- ZALR
- ZALR
- On-Chip Peripherals
- Synchronous Serial Port
- Asynchronous Serial Port
- TMS320C209
- Register Summary
- TMS320C1x/C2x/C2xx/C5x Instruction Set Comparison
- Program Examples
- Submitting ROM Codes to TI
- Design Considerations for Using XDS510 Emulator
- E.1 Designing Your Target System’s Emulator Connector (14-Pin Header)
- E.2 Bus Protocol
- E.3 Emulator Cable Pod
- E.4 Emulator Cable Pod Signal Timing
- E.5 Emulation Timing Calculations
- E.6 Connections Between the Emulator and the Target System
- E.7 Physical Dimensions for the 14-Pin Emulator Connector
- E.8 Emulation Design Considerations
- Glossary
- Index

Controlling and Resetting the Port
10-17
Asynchronous Serial Port
10.3.6 Using Interrupts
The asynchronous serial port interrupt (TXRXINT) can be generated by three
types of interrupts:
Transmit interrupts. A transmit interrupt is generated when the ADTR
empties during transmission. This indicates that the port is ready to accept
a new transmit character. In addition to generating the interrupt, the port
sets the THRE bit of the IOSR to 1. Transmit interrupts can be disabled by
the TIM bit of the ASPCR.
Receive interrupts. Any one of the following events will generate a re-
ceive interrupt:
The ADTR holds a new character. This event is also indicated by the
DR bit of the IOSR (DR = 1).
Overrun occurs. The last character in the ADTR was not read before
the next character overwrote it. Overrun also sets the OE bit of the
IOSR to 1.
A framing error occurs. The character received did not have a valid
(logic 1) stop bit. This event is also indicated by the FE bit of the IOSR
(FE = 1).
A break has been detected on the RX pin. This event also sets the BI
bit of the IOSR to 1.
The character A or a has been detected in the ADTR by the auto-baud
detect logic. This event also sets the ADC bit of the IOSR to 1. This
interrupt will occur regardless of the values of the DIM, TIM, and RIM
bits of the ASPCR.
With the exception of the A detect interrupt, receive interrupts can be dis-
abled by the RIM bit of the ASPCR.
Delta interrupts. This type of interrupt is generated if a change takes
place on one of the I/O lines (IO0, IO1, IO2, or IO3) when the lines are used
for ASP control (when DIM = 1 in the ASPCR). The event is also indicated
by the corresponding detect bit (DIO0, DIO1, DIO2, or DIO3) in the IOSR.
Delta interrupts can be disabled by the DIM bit of the ASPCR.