User manual
Table Of Contents
- Read This First
- Contents
- Figures
- Tables
- Examples
- Cautions
- Introduction
- Architectural Overview
- Central Processing Unit
- Memory and I/O Spaces
- Program Control
- Addressing Modes
- Assembly Language Instructions
- Instruction Set Summary
- How To Use the Instruction Descriptions
- Instruction Descriptions
- ABS
- ABS
- ADD
- ADD
- ADD
- ADD
- ADDC
- ADDC
- ADDS
- ADDS
- ADDT
- ADDT
- ADRK
- AND
- AND
- AND
- APAC
- APAC
- B
- BACC
- BANZ
- BANZ
- BCND
- BCND
- BIT
- BIT
- BITT
- BITT
- BLDD
- BLDD
- BLDD
- BLDD
- BLDD
- BLPD
- BLPD
- BLPD
- BLPD
- CALA
- CALL
- CC
- CC
- CLRC
- CLRC
- CMPL
- CMPR
- DMOV
- DMOV
- IDLE
- IN
- IN
- INTR
- LACC
- LACC
- LACC
- LACL
- LACL
- LACL
- LACT
- LACT
- LAR
- LAR
- LAR
- LDP
- LDP
- LPH
- LPH
- LST
- LST
- LST
- LST
- LT
- LT
- LTA
- LTA
- LTD
- LTD
- LTD
- LTP
- LTP
- LTS
- LTS
- MAC
- MAC
- MAC
- MAC
- MACD
- MACD
- MACD
- MACD
- MACD
- MAR
- MAR
- MPY
- MPY
- MPY
- MPYA
- MPYA
- MPYS
- MPYS
- MPYU
- MPYU
- NEG
- NEG
- NMI
- NOP
- NORM
- NORM
- NORM
- OR
- OR
- OR
- OUT
- OUT
- PAC
- POP
- POP
- POPD
- POPD
- PSHD
- PSHD
- PUSH
- RET
- RETC
- ROL
- ROR
- RPT
- RPT
- SACH
- SACH
- SACL
- SACL
- SAR
- SAR
- SBRK
- SETC
- SETC
- SFL
- SFR
- SFR
- SPAC
- SPH
- SPH
- SPL
- SPL
- SPLK
- SPLK
- SPM
- SQRA
- SQRA
- SQRS
- SQRS
- SST
- SST
- SUB
- SUB
- SUB
- SUB
- SUBB
- SUBB
- SUBC
- SUBC
- SUBS
- SUBS
- SUBT
- SUBT
- TBLR
- TBLR
- TBLR
- TBLW
- TBLW
- TBLW
- TRAP
- XOR
- XOR
- XOR
- ZALR
- ZALR
- On-Chip Peripherals
- Synchronous Serial Port
- Asynchronous Serial Port
- TMS320C209
- Register Summary
- TMS320C1x/C2x/C2xx/C5x Instruction Set Comparison
- Program Examples
- Submitting ROM Codes to TI
- Design Considerations for Using XDS510 Emulator
- E.1 Designing Your Target System’s Emulator Connector (14-Pin Header)
- E.2 Bus Protocol
- E.3 Emulator Cable Pod
- E.4 Emulator Cable Pod Signal Timing
- E.5 Emulation Timing Calculations
- E.6 Connections Between the Emulator and the Target System
- E.7 Physical Dimensions for the 14-Pin Emulator Connector
- E.8 Emulation Design Considerations
- Glossary
- Index

Transmitter Operation
9-18
9.5.2 Burst Mode Transmission With External Frame Sync (FSM = 1, TXM = 0)
Use burst mode transmission with external frame sync to transfer short pack-
ets at rates lower than maximum packet frequency while using an external
frame sync generator. Place the transmitter in burst mode with external frame
sync by setting the FSM bit to 1 and the TXM bit to 0.
This mode of operation offers several features:
A frame sync pulse initiates transmission.
If a frame sync pulse occurs after the initial one, then transmission
restarts.
Transmission can be initiated by an external event (for example, an exter-
nal interrupt) or by a serial port receive interrupt (RINT).
Generally, the transmit clock and the receive clock have the same source. This
allows each bit to be transmitted from another device on a rising edge of the
clock signal and received by the ’C2xx on the next falling edge of the clock sig-
nal.
Burst mode transmission with external frame sync involves the following order
of events (see Figure 9–5):
1) A frame sync pulse initiates the transmission. The pulse is sampled on the
falling edge of CLKX. After the falling edge of CLKX, the contents of the
first entry in the FIFO buffer are transferred to the XSR. If the FIFO buffer
becomes empty during this operation, it generates a XINT to request more
data.
2) On the next rising edge of CLKX after FSX goes high, DX is driven with
the first bit (MSB) of the word to be transmitted.
3) The frame sync goes low (and remains low during word transmission).
4) Once FSX goes low, the rest of the bits are shifted out.
5) When all of the bits in the word are transferred, the port waits for a new
frame sync pulse.
If the SDTR is loaded with a new word while the transmit FIFO buffer is full, the
new word will be lost; the FIFO buffer will not accept any more than four words.
If a frame sync pulse occurs during transmission, transmission is restarted. If
another value has been written to the SDTR, a new word is sent; otherwise,
the last word in the XSR is sent.
The burst mode can be discontinued (changed to continuous mode) only by
a serial-port or device reset. Changing the FSM bit during transmit or halt will
not necessarily cause a switch to continuous mode.